Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T31

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T31

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	932350	0	0
SrcPulseCheck_M	2147483647	929350	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	932350
T1	1551972	9123
T2	0	342
T3	0	976
T4	275489	264
T5	496605	752
T7	9004	0
T9	0	1966
T10	0	7909
T11	0	460
T16	5030	0
T17	190906	268
T18	9545	0
T19	8567	0
T20	34755	0
T22	0	2
T23	0	960
T24	13375	0
T27	0	6
T29	3962	22
T31	14648	4
T32	7256	27
T33	4956	4
T42	3300	2
T43	11466	8
T44	0	34
T64	21781	26
T65	0	17
T66	13279	0
T71	4324	0
T78	1487	0
T79	1333	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	929350
T1	792430	9124
T2	0	342
T3	0	976
T4	166905	264
T5	195079	752
T7	3742	0
T9	0	1966
T10	0	7804
T11	0	460
T16	1991	0
T17	37087	268
T18	3539	0
T19	3274	0
T20	4754	0
T22	0	2
T23	0	960
T24	4102	0
T27	0	6
T29	3962	22
T31	14648	4
T32	7256	27
T33	4956	4
T42	3300	3
T43	11466	8
T44	0	34
T64	26879	26
T65	0	17
T66	25477	0
T71	9831	0
T78	1376	0
T79	599	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	467261723	24674	0	0
SrcPulseCheck_M	162395068	24674	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	467261723	24674
T1	463664	523
T2	0	34
T3	0	60
T4	47556	12
T5	139944	32
T7	2136	0
T9	0	90
T16	1543	0
T17	54360	12
T18	2743	0
T19	2515	0
T20	8614	0
T22	0	2
T23	0	40
T24	3393	0
T27	0	6

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	162395068	24674
T1	198814	523
T2	0	34
T3	0	60
T4	71335	12
T5	193779	32
T7	1045	0
T9	0	90
T16	1543	0
T17	36567	12
T18	2743	0
T19	2542	0
T20	2242	0
T22	0	2
T23	0	40
T24	742	0
T27	0	6

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T32

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T29,T31

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	467261723	30711	0	0
SrcPulseCheck_M	162395068	30731	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	467261723	30711
T4	47556	12
T7	2136	0
T24	3393	0
T29	2654	21
T31	26754	2
T32	9719	28
T33	8672	3
T42	4306	3
T43	17897	19
T44	0	34
T64	22243	24
T65	0	39

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	162395068	30731
T4	71335	12
T7	1045	0
T24	742	0
T29	2654	21
T31	1392	2
T32	2429	28
T33	632	3
T42	1256	3
T43	2983	19
T44	0	34
T64	5561	24
T65	0	39

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T32

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T29,T31

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	30693	0	0
SrcPulseCheck_M	467261723	30718	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	30693
T4	71335	12
T7	1045	0
T24	742	0
T29	2654	21
T31	1392	2
T32	2429	28
T33	632	3
T42	1256	3
T43	2983	18
T44	0	34
T64	5561	24
T65	0	38

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	467261723	30718
T4	47556	12
T7	2136	0
T24	3393	0
T29	2654	21
T31	26754	2
T32	9719	28
T33	8672	3
T42	4306	3
T43	17897	19
T44	0	34
T64	22243	24
T65	0	39

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	232908476	24673	0	0
SrcPulseCheck_M	162395068	24673	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	232908476	24673
T1	232044	523
T2	0	34
T3	0	60
T4	23731	12
T5	69953	32
T7	1028	0
T9	0	90
T16	752	0
T17	27168	12
T18	1578	0
T19	1373	0
T20	6868	0
T22	0	2
T23	0	40
T24	1630	0
T27	0	6

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	162395068	24673
T1	198814	523
T2	0	34
T3	0	60
T4	71335	12
T5	193779	32
T7	1045	0
T9	0	90
T16	1543	0
T17	36567	12
T18	2743	0
T19	2542	0
T20	2242	0
T22	0	2
T23	0	40
T24	742	0
T27	0	6

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T31

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T31

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	232908476	30822	0	0
SrcPulseCheck_M	162395068	30846	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	232908476	30822
T4	23731	12
T7	1028	0
T24	1630	0
T29	1308	22
T31	13256	4
T32	4827	27
T33	4324	4
T42	2044	3
T43	8483	8
T44	0	34
T64	10659	26
T65	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	162395068	30846
T4	71335	12
T7	1045	0
T24	742	0
T29	2654	22
T31	1392	4
T32	2429	27
T33	632	4
T42	1256	3
T43	2983	8
T44	0	34
T64	5561	27
T65	0	17

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T31

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T31

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	30811	0	0
SrcPulseCheck_M	232908476	30827	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	30811
T4	71335	12
T7	1045	0
T24	742	0
T29	2654	22
T31	1392	4
T32	2429	27
T33	632	4
T42	1256	2
T43	2983	8
T44	0	34
T64	5561	26
T65	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	232908476	30827
T4	23731	12
T7	1028	0
T24	1630	0
T29	1308	22
T31	13256	4
T32	4827	27
T33	4324	4
T42	2044	3
T43	8483	8
T44	0	34
T64	10659	26
T65	0	17

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	116453505	24673	0	0
SrcPulseCheck_M	162395068	24673	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	116453505	24673
T1	116021	523
T2	0	34
T3	0	60
T4	11866	12
T5	34976	32
T7	514	0
T9	0	90
T16	376	0
T17	13584	12
T18	788	0
T19	685	0
T20	3432	0
T22	0	2
T23	0	40
T24	815	0
T27	0	6

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	162395068	24673
T1	198814	523
T2	0	34
T3	0	60
T4	71335	12
T5	193779	32
T7	1045	0
T9	0	90
T16	1543	0
T17	36567	12
T18	2743	0
T19	2542	0
T20	2242	0
T22	0	2
T23	0	40
T24	742	0
T27	0	6

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T31

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T31

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	116453505	30703	0	0
SrcPulseCheck_M	162395068	30737	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	116453505	30703
T4	11866	12
T7	514	0
T24	815	0
T29	654	4
T31	6628	4
T32	2413	22
T33	2162	3
T42	1023	3
T43	4244	17
T44	0	33
T64	5329	24
T65	0	50

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	162395068	30737
T4	71335	12
T7	1045	0
T24	742	0
T29	2654	4
T31	1392	4
T32	2429	22
T33	632	3
T42	1256	3
T43	2983	17
T44	0	33
T64	5561	24
T65	0	50

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T31

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T31

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	30698	0	0
SrcPulseCheck_M	116453505	30707	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	30698
T4	71335	12
T7	1045	0
T24	742	0
T29	2654	4
T31	1392	4
T32	2429	22
T33	632	3
T42	1256	3
T43	2983	17
T44	0	33
T64	5561	24
T65	0	49

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	116453505	30707
T4	11866	12
T7	514	0
T24	815	0
T29	654	4
T31	6628	4
T32	2413	22
T33	2162	3
T42	1023	3
T43	4244	17
T44	0	33
T64	5329	24
T65	0	50

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	497821414	24672	0	0
SrcPulseCheck_M	162395068	24672	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	497821414	24672
T1	508199	523
T2	0	34
T3	0	60
T4	73539	12
T5	181779	32
T7	2225	0
T9	0	90
T16	1607	0
T17	68626	12
T18	2858	0
T19	2621	0
T20	8973	0
T22	0	2
T23	0	40
T24	3535	0
T27	0	6

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	162395068	24672
T1	198814	523
T2	0	34
T3	0	60
T4	71335	12
T5	193779	32
T7	1045	0
T9	0	90
T16	1543	0
T17	36567	12
T18	2743	0
T19	2542	0
T20	2242	0
T22	0	2
T23	0	40
T24	742	0
T27	0	6

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T32

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T29,T31

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	497821414	30598	0	0
SrcPulseCheck_M	162395068	30616	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	497821414	30598
T4	73539	12
T7	2225	0
T24	3535	0
T29	2765	7
T31	27869	2
T32	10125	6
T33	9033	4
T42	4485	3
T43	18644	20
T44	0	37
T64	23172	25
T65	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	162395068	30616
T4	71335	12
T7	1045	0
T24	742	0
T29	2654	7
T31	1392	2
T32	2429	6
T33	632	4
T42	1256	3
T43	2983	20
T44	0	37
T64	5561	25
T65	0	15

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T32

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T29,T31

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	30581	0	0
SrcPulseCheck_M	497821414	30603	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	30581
T4	71335	12
T7	1045	0
T24	742	0
T29	2654	7
T31	1392	2
T32	2429	6
T33	632	4
T42	1256	3
T43	2983	19
T44	0	37
T64	5561	25
T65	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	497821414	30603
T4	73539	12
T7	2225	0
T24	3535	0
T29	2765	7
T31	27869	2
T32	10125	6
T33	9033	4
T42	4485	3
T43	18644	20
T44	0	37
T64	23172	25
T65	0	15

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	238816711	24293	0	0
SrcPulseCheck_M	162395068	24671	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	238816711	24293
T1	244515	523
T2	0	34
T3	0	60
T4	32419	12
T5	81495	32
T7	1068	0
T9	0	90
T16	772	0
T17	35821	12
T18	1371	0
T19	1257	0
T20	4307	0
T22	0	1
T23	0	40
T24	1697	0
T27	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	162395068	24671
T1	198814	523
T2	0	34
T3	0	60
T4	71335	12
T5	193779	32
T7	1045	0
T9	0	90
T16	1543	0
T17	36567	12
T18	2743	0
T19	2542	0
T20	2242	0
T22	0	2
T23	0	40
T24	742	0
T27	0	6

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T32

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T29,T31

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	238816711	30527	0	0
SrcPulseCheck_M	162395068	30691	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	238816711	30527
T4	32419	12
T7	1068	0
T24	1697	0
T29	1327	15
T31	13377	2
T32	4859	5
T33	4336	4
T42	2152	3
T43	8949	24
T44	0	35
T64	11122	8
T65	0	32

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	162395068	30691
T4	71335	12
T7	1045	0
T24	742	0
T29	2654	15
T31	1392	2
T32	2429	5
T33	632	4
T42	1256	3
T43	2983	24
T44	0	35
T64	5561	8
T65	0	32

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T29,T32

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T29,T31
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T29,T31

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	30407	0	0
SrcPulseCheck_M	238816711	30576	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	30407
T4	71335	12
T7	1045	0
T24	742	0
T29	2654	15
T31	1392	2
T32	2429	5
T33	632	4
T42	1256	3
T43	2983	24
T44	0	35
T64	5561	8
T65	0	32

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	238816711	30576
T4	32419	12
T7	1068	0
T24	1697	0
T29	1327	15
T31	13377	2
T32	4859	5
T33	4336	4
T42	2152	3
T43	8949	24
T44	0	35
T64	11122	8
T65	0	32

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T65,T67
1	0	Covered	T43,T65,T67
1	1	Covered	T120,T121,T122

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T65,T67
1	0	Covered	T120,T121,T122
1	1	Covered	T43,T65,T67

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	36	0	0
SrcPulseCheck_M	467261723	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	36
T43	2983	1
T65	7378	1
T67	8309	1
T70	9135	1
T87	1238	0
T88	1095	0
T89	2172	0
T90	4097	0
T91	948	0
T120	0	2
T121	0	3
T122	0	3
T123	0	3
T124	0	3
T125	0	2
T126	1908	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	467261723	36
T43	17897	1
T65	54481	1
T67	16279	1
T70	17898	1
T87	1251	0
T88	4382	0
T89	2085	0
T90	8027	0
T91	3643	0
T120	0	2
T121	0	3
T122	0	3
T123	0	3
T124	0	3
T125	0	2
T126	1888	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T65,T67
1	0	Covered	T43,T65,T67
1	1	Covered	T121,T122

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T65,T67
1	0	Covered	T121,T122
1	1	Covered	T43,T65,T67

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	33	0	0
SrcPulseCheck_M	467261723	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	33
T43	2983	1
T65	7378	1
T67	8309	1
T70	9135	1
T72	0	1
T87	1238	0
T88	1095	0
T89	2172	0
T90	4097	0
T91	948	0
T120	0	2
T121	0	3
T123	0	2
T124	0	1
T126	1908	0
T127	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	467261723	33
T43	17897	1
T65	54481	1
T67	16279	1
T70	17898	1
T72	0	1
T87	1251	0
T88	4382	0
T89	2085	0
T90	8027	0
T91	3643	0
T120	0	2
T121	0	3
T123	0	2
T124	0	1
T126	1888	0
T127	0	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T64,T71,T69
1	0	Covered	T64,T71,T69
1	1	Covered	T70,T120,T122

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T64,T71,T69
1	0	Covered	T70,T120,T122
1	1	Covered	T64,T71,T69

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	28	0	0
SrcPulseCheck_M	232908476	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	28
T46	2590	0
T64	5561	1
T66	13279	0
T68	5279	0
T69	3591	1
T70	0	4
T71	4324	1
T73	1988	0
T78	1487	0
T79	1333	0
T80	816	0
T120	0	2
T123	0	1
T124	0	1
T127	0	1
T128	0	1
T129	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	232908476	28
T46	2529	0
T64	10659	1
T66	25477	0
T68	4889	0
T69	9230	1
T70	0	4
T71	9831	1
T73	2512	0
T78	1376	0
T79	599	0
T80	1549	0
T120	0	2
T123	0	1
T124	0	1
T127	0	1
T128	0	1
T129	0	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T64,T71,T69
1	0	Covered	T64,T71,T69
1	1	Covered	T71,T70,T120

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T64,T71,T69
1	0	Covered	T71,T70,T120
1	1	Covered	T64,T71,T69

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	29	0	0
SrcPulseCheck_M	232908476	29	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	29
T46	2590	0
T64	5561	2
T66	13279	0
T68	5279	0
T69	3591	1
T70	0	3
T71	4324	2
T73	1988	0
T78	1487	0
T79	1333	0
T80	816	0
T120	0	2
T121	0	1
T123	0	2
T124	0	1
T127	0	2
T129	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	232908476	29
T46	2529	0
T64	10659	2
T66	25477	0
T68	4889	0
T69	9230	1
T70	0	3
T71	9831	2
T73	2512	0
T78	1376	0
T79	599	0
T80	1549	0
T120	0	2
T121	0	1
T123	0	2
T124	0	1
T127	0	2
T129	0	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T65,T69
1	0	Covered	T43,T65,T69
1	1	Covered	T65

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T65,T69
1	0	Covered	T65
1	1	Covered	T43,T65,T69

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	28	0	0
SrcPulseCheck_M	116453505	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	28
T43	2983	1
T46	2590	0
T65	7378	4
T68	5279	2
T69	3591	1
T70	9135	1
T72	0	2
T73	1988	0
T80	816	0
T87	1238	0
T88	1095	0
T122	0	1
T123	0	1
T125	0	1
T129	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	116453505	28
T43	4244	1
T46	1265	0
T65	13199	4
T68	2445	2
T69	4616	1
T70	4063	1
T72	0	2
T73	1256	0
T80	775	0
T87	303	0
T88	1089	0
T122	0	1
T123	0	1
T125	0	1
T129	0	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T65,T69
1	0	Covered	T43,T65,T69
1	1	Covered	T65,T130

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T65,T69
1	0	Covered	T65,T130
1	1	Covered	T43,T65,T69

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	27	0	0
SrcPulseCheck_M	116453505	27	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	27
T43	2983	1
T46	2590	0
T65	7378	4
T68	5279	0
T69	3591	1
T70	9135	1
T72	0	2
T73	1988	0
T80	816	0
T87	1238	0
T88	1095	0
T122	0	1
T123	0	1
T127	0	1
T129	0	2
T131	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	116453505	27
T43	4244	1
T46	1265	0
T65	13199	4
T68	2445	0
T69	4616	1
T70	4063	1
T72	0	2
T73	1256	0
T80	775	0
T87	303	0
T88	1089	0
T122	0	1
T123	0	1
T127	0	1
T129	0	2
T131	0	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T64,T65
1	0	Covered	T43,T64,T65
1	1	Covered	T64,T128,T132

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T64,T65
1	0	Covered	T64,T128,T132
1	1	Covered	T43,T64,T65

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	31	0	0
SrcPulseCheck_M	497821414	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	31
T43	2983	1
T64	5561	2
T65	7378	1
T66	13279	0
T68	0	1
T69	3591	1
T70	0	1
T71	4324	1
T72	0	1
T73	1988	0
T78	1487	0
T79	1333	0
T80	816	0
T120	0	1
T128	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	497821414	31
T43	18644	1
T64	23172	2
T65	56754	1
T66	53118	0
T68	0	1
T69	19955	1
T70	0	1
T71	21621	1
T72	0	1
T73	5372	0
T78	3035	0
T79	1389	0
T80	3267	0
T120	0	1
T128	0	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T68,T70
1	0	Covered	T43,T68,T70
1	1	Covered	T43,T128,T133

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T68,T70
1	0	Covered	T43,T128,T133
1	1	Covered	T43,T68,T70

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	31	0	0
SrcPulseCheck_M	497821414	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	31
T43	2983	2
T68	5279	1
T70	9135	1
T72	0	1
T82	7760	0
T87	1238	0
T88	1095	0
T89	2172	0
T90	4097	0
T91	948	0
T120	0	1
T122	0	1
T124	0	1
T126	1908	0
T128	0	3
T134	0	1
T135	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	497821414	31
T43	18644	2
T68	11477	1
T70	18645	1
T72	0	1
T82	7760	0
T87	1303	0
T88	4565	0
T89	2172	0
T90	8361	0
T91	3794	0
T120	0	1
T122	0	1
T124	0	1
T126	1966	0
T128	0	3
T134	0	1
T135	0	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T65,T67
1	0	Covered	T43,T65,T67
1	1	Covered	T70,T123,T127

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T65,T67
1	0	Covered	T70,T123,T127
1	1	Covered	T43,T65,T67

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	35	0	0
SrcPulseCheck_M	238816711	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	35
T43	2983	1
T46	2590	0
T65	7378	2
T67	8309	2
T68	5279	1
T69	3591	1
T70	9135	2
T73	1988	0
T80	816	0
T87	1238	0
T123	0	3
T124	0	3
T127	0	4
T128	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	238816711	35
T43	8949	1
T46	2590	0
T65	27242	2
T67	8140	2
T68	5508	1
T69	9579	1
T70	8950	2
T73	2578	0
T80	1568	0
T87	625	0
T123	0	3
T124	0	3
T127	0	4
T128	0	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T65,T67
1	0	Covered	T43,T65,T67
1	1	Covered	T129,T136

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T43,T65,T67
1	0	Covered	T129,T136
1	1	Covered	T43,T65,T67

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	162395068	32	0	0
SrcPulseCheck_M	238816711	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	162395068	32
T43	2983	1
T46	2590	0
T65	7378	2
T67	8309	2
T68	5279	0
T69	3591	2
T70	9135	1
T73	1988	0
T80	816	0
T87	1238	0
T120	0	2
T123	0	3
T124	0	2
T127	0	2
T128	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	238816711	32
T43	8949	1
T46	2590	0
T65	27242	2
T67	8140	2
T68	5508	0
T69	9579	2
T70	8950	1
T73	2578	0
T80	1568	0
T87	625	0
T120	0	2
T123	0	3
T124	0	2
T127	0	2
T128	0	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	464905655	94162	0	0
SrcPulseCheck_M	19423354	93485	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	464905655	94162
T1	463664	2043
T2	0	77
T3	0	202
T4	47556	48
T5	139944	162
T7	2136	0
T9	0	448
T10	0	1861
T11	0	115
T16	1543	0
T17	54360	58
T18	2743	0
T19	2515	0
T20	8614	0
T23	0	224
T24	3393	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	19423354	93485
T1	148278	2043
T2	0	77
T3	0	202
T4	114	48
T5	307	162
T7	156	0
T9	0	448
T10	0	1826
T11	0	115
T16	112	0
T17	124	58
T18	199	0
T19	183	0
T20	628	0
T23	0	224
T24	247	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	231778285	93305	0	0
SrcPulseCheck_M	19423354	92635	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	231778285	93305
T1	232044	2031
T2	0	77
T3	0	202
T4	23731	48
T5	69953	162
T7	1028	0
T9	0	448
T10	0	1861
T11	0	115
T16	752	0
T17	27168	58
T18	1578	0
T19	1373	0
T20	6868	0
T23	0	224
T24	1630	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	19423354	92635
T1	148278	2031
T2	0	77
T3	0	202
T4	114	48
T5	307	162
T7	156	0
T9	0	448
T10	0	1826
T11	0	115
T16	112	0
T17	124	58
T18	199	0
T19	183	0
T20	628	0
T23	0	224
T24	247	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	115888420	91930	0	0
SrcPulseCheck_M	19423354	91281	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	115888420	91930
T1	116021	2015
T2	0	77
T3	0	202
T4	11866	48
T5	34976	162
T7	514	0
T9	0	448
T10	0	1861
T11	0	115
T16	376	0
T17	13584	58
T18	788	0
T19	685	0
T20	3432	0
T23	0	224
T24	815	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	19423354	91281
T1	148278	2015
T2	0	77
T3	0	202
T4	114	48
T5	307	162
T7	156	0
T9	0	448
T10	0	1826
T11	0	115
T16	112	0
T17	124	58
T18	199	0
T19	183	0
T20	628	0
T23	0	224
T24	247	0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	495367080	112658	0	0
SrcPulseCheck_M	19862585	112481	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	495367080	112658
T1	508199	2511
T2	0	77
T3	0	310
T4	73539	96
T5	181779	234
T7	2225	0
T9	0	532
T10	0	2326
T11	0	115
T16	1607	0
T17	68626	82
T18	2858	0
T19	2621	0
T20	8973	0
T23	0	248
T24	3535	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	19862585	112481
T1	148782	2512
T2	0	77
T3	0	310
T4	162	96
T5	379	234
T7	156	0
T9	0	532
T10	0	2326
T11	0	115
T16	112	0
T17	148	82
T18	199	0
T19	183	0
T20	628	0
T23	0	248
T24	247	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	237638660	110449	0	0
SrcPulseCheck_M	19581848	108743	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	237638660	110449
T1	244515	2486
T2	0	77
T3	0	322
T4	32419	84
T5	81495	210
T7	1068	0
T9	0	580
T10	0	2205
T11	0	115
T16	772	0
T17	35821	94
T18	1371	0
T19	1257	0
T20	4307	0
T23	0	308
T24	1697	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	19581848	108743
T1	148806	2486
T2	0	77
T3	0	322
T4	150	84
T5	355	210
T7	156	0
T9	0	580
T10	0	2206
T11	0	115
T16	112	0
T17	160	94
T18	199	0
T19	183	0
T20	628	0
T23	0	308
T24	247	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb