Module Definition
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Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.36 97.74 86.76 94.92 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 87.44 96.94 84.78 93.02 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Module : prim_reg_cdc
TotalCoveredPercent
Conditions151386.67
Logical151386.67
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT29,T31,T32
10CoveredT4,T29,T31

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT4,T29,T31
11CoveredT4,T29,T31

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT1,T2,T3
10CoveredT4,T29,T31

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T29,T31
11CoveredT4,T29,T31

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT6,T4,T7
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T29,T31
0 0 1 Covered T4,T29,T31
0 0 0 Covered T6,T4,T7


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T29,T31
0 0 1 Covered T4,T29,T31
0 0 0 Covered T6,T4,T7


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1623950680 1436226 0 0
DstReqKnown_A 2147483647 2147483647 0 0
SrcAckBusyChk_A 1623950680 276169 0 0
SrcBusyKnown_A 1623950680 1600992880 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1623950680 1436226 0 0
T1 994070 11521 0 0
T2 0 1417 0 0
T3 0 2496 0 0
T4 713350 976 0 0
T5 968895 1346 0 0
T7 10450 0 0 0
T9 0 1652 0 0
T16 7715 0 0 0
T17 182835 339 0 0
T18 13715 0 0 0
T19 12710 0 0 0
T20 11210 0 0 0
T22 0 27 0 0
T23 0 1615 0 0
T24 7420 0 0 0
T27 0 78 0 0
T29 13270 560 0 0
T31 6960 42 0 0
T32 12145 308 0 0
T33 3160 36 0 0
T42 6280 61 0 0
T43 14915 257 0 0
T44 0 1394 0 0
T64 27805 366 0 0
T65 0 442 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T4 378222 377296 0 0
T6 12356 11836 0 0
T7 13942 13082 0 0
T24 22140 20910 0 0
T28 451176 450660 0 0
T29 17416 16856 0 0
T30 17536 16612 0 0
T31 175768 172718 0 0
T32 63886 63276 0 0
T33 57054 56024 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1623950680 276169 0 0
T1 994070 2615 0 0
T2 0 170 0 0
T3 0 300 0 0
T4 713350 120 0 0
T5 968895 160 0 0
T7 10450 0 0 0
T9 0 450 0 0
T16 7715 0 0 0
T17 182835 60 0 0
T18 13715 0 0 0
T19 12710 0 0 0
T20 11210 0 0 0
T22 0 9 0 0
T23 0 200 0 0
T24 7420 0 0 0
T27 0 27 0 0
T29 13270 69 0 0
T31 6960 14 0 0
T32 12145 88 0 0
T33 3160 18 0 0
T42 6280 14 0 0
T43 14915 86 0 0
T44 0 173 0 0
T64 27805 107 0 0
T65 0 152 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1623950680 1600992880 0 0
T4 713350 711710 0 0
T6 9660 9180 0 0
T7 10450 9730 0 0
T24 7420 6950 0 0
T28 64270 64180 0 0
T29 26540 25600 0 0
T30 5870 5520 0 0
T31 13920 13650 0 0
T32 24290 24030 0 0
T33 6320 6210 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT6,T4,T7
01Unreachable
10CoveredT4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT1,T2,T3
10CoveredT4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT6,T4,T7
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T1,T5
0 0 1 Covered T4,T1,T5
0 0 0 Covered T6,T4,T7


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T1,T5
0 0 1 Covered T4,T1,T5
0 0 0 Covered T6,T4,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 162395068 88663 0 0
DstReqKnown_A 467261723 463145407 0 0
SrcAckBusyChk_A 162395068 24674 0 0
SrcBusyKnown_A 162395068 160099288 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 88663 0 0
T1 198814 1700 0 0
T2 0 173 0 0
T3 0 314 0 0
T4 71335 60 0 0
T5 193779 164 0 0
T7 1045 0 0 0
T9 0 239 0 0
T16 1543 0 0 0
T17 36567 46 0 0
T18 2743 0 0 0
T19 2542 0 0 0
T20 2242 0 0 0
T22 0 5 0 0
T23 0 232 0 0
T24 742 0 0 0
T27 0 14 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467261723 463145407 0 0
T4 47556 47394 0 0
T6 1892 1798 0 0
T7 2136 1987 0 0
T24 3393 3176 0 0
T28 68547 68453 0 0
T29 2654 2560 0 0
T30 2685 2523 0 0
T31 26754 26235 0 0
T32 9719 9611 0 0
T33 8672 8510 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 24674 0 0
T1 198814 523 0 0
T2 0 34 0 0
T3 0 60 0 0
T4 71335 12 0 0
T5 193779 32 0 0
T7 1045 0 0 0
T9 0 90 0 0
T16 1543 0 0 0
T17 36567 12 0 0
T18 2743 0 0 0
T19 2542 0 0 0
T20 2242 0 0 0
T22 0 2 0 0
T23 0 40 0 0
T24 742 0 0 0
T27 0 6 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 160099288 0 0
T4 71335 71171 0 0
T6 966 918 0 0
T7 1045 973 0 0
T24 742 695 0 0
T28 6427 6418 0 0
T29 2654 2560 0 0
T30 587 552 0 0
T31 1392 1365 0 0
T32 2429 2403 0 0
T33 632 621 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT6,T4,T7
01Unreachable
10CoveredT4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT1,T2,T3
10CoveredT4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT6,T4,T7
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T1,T5
0 0 1 Covered T4,T1,T5
0 0 0 Covered T6,T4,T7


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T1,T5
0 0 1 Covered T4,T1,T5
0 0 0 Covered T6,T4,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 162395068 127247 0 0
DstReqKnown_A 232908476 231874690 0 0
SrcAckBusyChk_A 162395068 24673 0 0
SrcBusyKnown_A 162395068 160099288 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 127247 0 0
T1 198814 2300 0 0
T2 0 276 0 0
T3 0 497 0 0
T4 71335 96 0 0
T5 193779 262 0 0
T7 1045 0 0 0
T9 0 347 0 0
T16 1543 0 0 0
T17 36567 68 0 0
T18 2743 0 0 0
T19 2542 0 0 0
T20 2242 0 0 0
T22 0 6 0 0
T23 0 330 0 0
T24 742 0 0 0
T27 0 17 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 232908476 231874690 0 0
T4 23731 23697 0 0
T6 913 899 0 0
T7 1028 993 0 0
T24 1630 1588 0 0
T28 34241 34227 0 0
T29 1308 1280 0 0
T30 1296 1262 0 0
T31 13256 13118 0 0
T32 4827 4806 0 0
T33 4324 4255 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 24673 0 0
T1 198814 523 0 0
T2 0 34 0 0
T3 0 60 0 0
T4 71335 12 0 0
T5 193779 32 0 0
T7 1045 0 0 0
T9 0 90 0 0
T16 1543 0 0 0
T17 36567 12 0 0
T18 2743 0 0 0
T19 2542 0 0 0
T20 2242 0 0 0
T22 0 2 0 0
T23 0 40 0 0
T24 742 0 0 0
T27 0 6 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 160099288 0 0
T4 71335 71171 0 0
T6 966 918 0 0
T7 1045 973 0 0
T24 742 695 0 0
T28 6427 6418 0 0
T29 2654 2560 0 0
T30 587 552 0 0
T31 1392 1365 0 0
T32 2429 2403 0 0
T33 632 621 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT6,T4,T7
01Unreachable
10CoveredT4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT1,T2,T3
10CoveredT4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT6,T4,T7
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T1,T5
0 0 1 Covered T4,T1,T5
0 0 0 Covered T6,T4,T7


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T1,T5
0 0 1 Covered T4,T1,T5
0 0 0 Covered T6,T4,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 162395068 204389 0 0
DstReqKnown_A 116453505 115936708 0 0
SrcAckBusyChk_A 162395068 24673 0 0
SrcBusyKnown_A 162395068 160099288 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 204389 0 0
T1 198814 3560 0 0
T2 0 490 0 0
T3 0 878 0 0
T4 71335 177 0 0
T5 193779 463 0 0
T7 1045 0 0 0
T9 0 484 0 0
T16 1543 0 0 0
T17 36567 111 0 0
T18 2743 0 0 0
T19 2542 0 0 0
T20 2242 0 0 0
T22 0 8 0 0
T23 0 557 0 0
T24 742 0 0 0
T27 0 22 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 116453505 115936708 0 0
T4 11866 11849 0 0
T6 456 449 0 0
T7 514 497 0 0
T24 815 794 0 0
T28 17120 17113 0 0
T29 654 640 0 0
T30 648 631 0 0
T31 6628 6559 0 0
T32 2413 2402 0 0
T33 2162 2128 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 24673 0 0
T1 198814 523 0 0
T2 0 34 0 0
T3 0 60 0 0
T4 71335 12 0 0
T5 193779 32 0 0
T7 1045 0 0 0
T9 0 90 0 0
T16 1543 0 0 0
T17 36567 12 0 0
T18 2743 0 0 0
T19 2542 0 0 0
T20 2242 0 0 0
T22 0 2 0 0
T23 0 40 0 0
T24 742 0 0 0
T27 0 6 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 160099288 0 0
T4 71335 71171 0 0
T6 966 918 0 0
T7 1045 973 0 0
T24 742 695 0 0
T28 6427 6418 0 0
T29 2654 2560 0 0
T30 587 552 0 0
T31 1392 1365 0 0
T32 2429 2403 0 0
T33 632 621 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT6,T4,T7
01Unreachable
10CoveredT4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT1,T2,T3
10CoveredT4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT6,T4,T7
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T1,T5
0 0 1 Covered T4,T1,T5
0 0 0 Covered T6,T4,T7


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T1,T5
0 0 1 Covered T4,T1,T5
0 0 0 Covered T6,T4,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 162395068 87985 0 0
DstReqKnown_A 497821414 493494270 0 0
SrcAckBusyChk_A 162395068 24672 0 0
SrcBusyKnown_A 162395068 160099288 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 87985 0 0
T1 198814 1688 0 0
T2 0 202 0 0
T3 0 307 0 0
T4 71335 59 0 0
T5 193779 192 0 0
T7 1045 0 0 0
T9 0 238 0 0
T16 1543 0 0 0
T17 36567 46 0 0
T18 2743 0 0 0
T19 2542 0 0 0
T20 2242 0 0 0
T22 0 5 0 0
T23 0 191 0 0
T24 742 0 0 0
T27 0 14 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 497821414 493494270 0 0
T4 73539 73370 0 0
T6 1971 1873 0 0
T7 2225 2070 0 0
T24 3535 3309 0 0
T28 71405 71308 0 0
T29 2765 2668 0 0
T30 2797 2628 0 0
T31 27869 27330 0 0
T32 10125 10013 0 0
T33 9033 8864 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 24672 0 0
T1 198814 523 0 0
T2 0 34 0 0
T3 0 60 0 0
T4 71335 12 0 0
T5 193779 32 0 0
T7 1045 0 0 0
T9 0 90 0 0
T16 1543 0 0 0
T17 36567 12 0 0
T18 2743 0 0 0
T19 2542 0 0 0
T20 2242 0 0 0
T22 0 2 0 0
T23 0 40 0 0
T24 742 0 0 0
T27 0 6 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 160099288 0 0
T4 71335 71171 0 0
T6 966 918 0 0
T7 1045 973 0 0
T24 742 695 0 0
T28 6427 6418 0 0
T29 2654 2560 0 0
T30 587 552 0 0
T31 1392 1365 0 0
T32 2429 2403 0 0
T33 632 621 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT6,T4,T7
01Unreachable
10CoveredT4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT1,T2,T3
10CoveredT4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT6,T4,T7
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T1,T5
0 0 1 Covered T4,T1,T5
0 0 0 Covered T6,T4,T7


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T1,T5
0 0 1 Covered T4,T1,T5
0 0 0 Covered T6,T4,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 162395068 125870 0 0
DstReqKnown_A 238816711 236753154 0 0
SrcAckBusyChk_A 162395068 24248 0 0
SrcBusyKnown_A 162395068 160099288 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 125870 0 0
T1 198814 2273 0 0
T2 0 276 0 0
T3 0 500 0 0
T4 71335 101 0 0
T5 193779 265 0 0
T7 1045 0 0 0
T9 0 344 0 0
T16 1543 0 0 0
T17 36567 68 0 0
T18 2743 0 0 0
T19 2542 0 0 0
T20 2242 0 0 0
T22 0 3 0 0
T23 0 305 0 0
T24 742 0 0 0
T27 0 11 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238816711 236753154 0 0
T4 32419 32338 0 0
T6 946 899 0 0
T7 1068 994 0 0
T24 1697 1588 0 0
T28 34275 34229 0 0
T29 1327 1280 0 0
T30 1342 1262 0 0
T31 13377 13117 0 0
T32 4859 4806 0 0
T33 4336 4255 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 24248 0 0
T1 198814 523 0 0
T2 0 34 0 0
T3 0 60 0 0
T4 71335 12 0 0
T5 193779 32 0 0
T7 1045 0 0 0
T9 0 90 0 0
T16 1543 0 0 0
T17 36567 12 0 0
T18 2743 0 0 0
T19 2542 0 0 0
T20 2242 0 0 0
T22 0 1 0 0
T23 0 40 0 0
T24 742 0 0 0
T27 0 3 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 160099288 0 0
T4 71335 71171 0 0
T6 966 918 0 0
T7 1045 973 0 0
T24 742 695 0 0
T28 6427 6418 0 0
T29 2654 2560 0 0
T30 587 552 0 0
T31 1392 1365 0 0
T32 2429 2403 0 0
T33 632 621 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT29,T31,T32
10CoveredT4,T29,T32

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT4,T29,T31
11CoveredT4,T29,T31

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT6,T4,T7
01Unreachable
10CoveredT4,T29,T31

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T29,T31
11CoveredT4,T29,T31

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT6,T4,T7
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T29,T31
0 0 1 Covered T4,T29,T31
0 0 0 Covered T6,T4,T7


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T29,T31
0 0 1 Covered T4,T29,T31
0 0 0 Covered T6,T4,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 162395068 111849 0 0
DstReqKnown_A 467261723 463145407 0 0
SrcAckBusyChk_A 162395068 30699 0 0
SrcBusyKnown_A 162395068 160099288 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 111849 0 0
T4 71335 60 0 0
T7 1045 0 0 0
T24 742 0 0 0
T29 2654 131 0 0
T31 1392 6 0 0
T32 2429 69 0 0
T33 632 6 0 0
T42 1256 8 0 0
T43 2983 46 0 0
T44 0 177 0 0
T64 5561 59 0 0
T65 0 96 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467261723 463145407 0 0
T4 47556 47394 0 0
T6 1892 1798 0 0
T7 2136 1987 0 0
T24 3393 3176 0 0
T28 68547 68453 0 0
T29 2654 2560 0 0
T30 2685 2523 0 0
T31 26754 26235 0 0
T32 9719 9611 0 0
T33 8672 8510 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 30699 0 0
T4 71335 12 0 0
T7 1045 0 0 0
T24 742 0 0 0
T29 2654 21 0 0
T31 1392 2 0 0
T32 2429 28 0 0
T33 632 3 0 0
T42 1256 3 0 0
T43 2983 18 0 0
T44 0 34 0 0
T64 5561 24 0 0
T65 0 38 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 160099288 0 0
T4 71335 71171 0 0
T6 966 918 0 0
T7 1045 973 0 0
T24 742 695 0 0
T28 6427 6418 0 0
T29 2654 2560 0 0
T30 587 552 0 0
T31 1392 1365 0 0
T32 2429 2403 0 0
T33 632 621 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT29,T31,T32
10CoveredT4,T29,T31

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT4,T29,T31
11CoveredT4,T29,T31

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT6,T4,T7
01Unreachable
10CoveredT4,T29,T31

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T29,T31
11CoveredT4,T29,T31

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT6,T4,T7
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T29,T31
0 0 1 Covered T4,T29,T31
0 0 0 Covered T6,T4,T7


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T29,T31
0 0 1 Covered T4,T29,T31
0 0 0 Covered T6,T4,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 162395068 161197 0 0
DstReqKnown_A 232908476 231874690 0 0
SrcAckBusyChk_A 162395068 30815 0 0
SrcBusyKnown_A 162395068 160099288 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 161197 0 0
T4 71335 96 0 0
T7 1045 0 0 0
T24 742 0 0 0
T29 2654 188 0 0
T31 1392 12 0 0
T32 2429 94 0 0
T33 632 8 0 0
T42 1256 13 0 0
T43 2983 26 0 0
T44 0 279 0 0
T64 5561 93 0 0
T65 0 45 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 232908476 231874690 0 0
T4 23731 23697 0 0
T6 913 899 0 0
T7 1028 993 0 0
T24 1630 1588 0 0
T28 34241 34227 0 0
T29 1308 1280 0 0
T30 1296 1262 0 0
T31 13256 13118 0 0
T32 4827 4806 0 0
T33 4324 4255 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 30815 0 0
T4 71335 12 0 0
T7 1045 0 0 0
T24 742 0 0 0
T29 2654 22 0 0
T31 1392 4 0 0
T32 2429 27 0 0
T33 632 4 0 0
T42 1256 2 0 0
T43 2983 8 0 0
T44 0 34 0 0
T64 5561 26 0 0
T65 0 17 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 160099288 0 0
T4 71335 71171 0 0
T6 966 918 0 0
T7 1045 973 0 0
T24 742 695 0 0
T28 6427 6418 0 0
T29 2654 2560 0 0
T30 587 552 0 0
T31 1392 1365 0 0
T32 2429 2403 0 0
T33 632 621 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT29,T31,T32
10CoveredT4,T29,T31

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT4,T29,T31
11CoveredT4,T29,T31

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT6,T4,T7
01Unreachable
10CoveredT4,T29,T31

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T29,T31
11CoveredT4,T29,T31

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT6,T4,T7
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T29,T31
0 0 1 Covered T4,T29,T31
0 0 0 Covered T6,T4,T7


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T29,T31
0 0 1 Covered T4,T29,T31
0 0 0 Covered T6,T4,T7


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 162395068 259123 0 0
DstReqKnown_A 116453505 115936708 0 0
SrcAckBusyChk_A 162395068 30701 0 0
SrcBusyKnown_A 162395068 160099288 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 259123 0 0
T4 71335 168 0 0
T7 1045 0 0 0
T24 742 0 0 0
T29 2654 71 0 0
T31 1392 12 0 0
T32 2429 110 0 0
T33 632 6 0 0
T42 1256 17 0 0
T43 2983 67 0 0
T44 0 468 0 0
T64 5561 120 0 0
T65 0 178 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 116453505 115936708 0 0
T4 11866 11849 0 0
T6 456 449 0 0
T7 514 497 0 0
T24 815 794 0 0
T28 17120 17113 0 0
T29 654 640 0 0
T30 648 631 0 0
T31 6628 6559 0 0
T32 2413 2402 0 0
T33 2162 2128 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 30701 0 0
T4 71335 12 0 0
T7 1045 0 0 0
T24 742 0 0 0
T29 2654 4 0 0
T31 1392 4 0 0
T32 2429 22 0 0
T33 632 3 0 0
T42 1256 3 0 0
T43 2983 17 0 0
T44 0 33 0 0
T64 5561 24 0 0
T65 0 50 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 160099288 0 0
T4 71335 71171 0 0
T6 966 918 0 0
T7 1045 973 0 0
T24 742 695 0 0
T28 6427 6418 0 0
T29 2654 2560 0 0
T30 587 552 0 0
T31 1392 1365 0 0
T32 2429 2403 0 0
T33 632 621 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT29,T31,T32
10CoveredT4,T29,T32

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT4,T29,T31
11CoveredT4,T29,T31

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT6,T4,T7
01Unreachable
10CoveredT4,T29,T31

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T29,T31
11CoveredT4,T29,T31

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT6,T4,T7
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T29,T31
0 0 1 Covered T4,T29,T31
0 0 0 Covered T6,T4,T7


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T29,T31
0 0 1 Covered T4,T29,T31
0 0 0 Covered T6,T4,T7


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 162395068 109948 0 0
DstReqKnown_A 497821414 493494270 0 0
SrcAckBusyChk_A 162395068 30583 0 0
SrcBusyKnown_A 162395068 160099288 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 109948 0 0
T4 71335 60 0 0
T7 1045 0 0 0
T24 742 0 0 0
T29 2654 38 0 0
T31 1392 6 0 0
T32 2429 16 0 0
T33 632 8 0 0
T42 1256 10 0 0
T43 2983 48 0 0
T44 0 182 0 0
T64 5561 65 0 0
T65 0 40 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 497821414 493494270 0 0
T4 73539 73370 0 0
T6 1971 1873 0 0
T7 2225 2070 0 0
T24 3535 3309 0 0
T28 71405 71308 0 0
T29 2765 2668 0 0
T30 2797 2628 0 0
T31 27869 27330 0 0
T32 10125 10013 0 0
T33 9033 8864 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 30583 0 0
T4 71335 12 0 0
T7 1045 0 0 0
T24 742 0 0 0
T29 2654 7 0 0
T31 1392 2 0 0
T32 2429 6 0 0
T33 632 4 0 0
T42 1256 3 0 0
T43 2983 19 0 0
T44 0 37 0 0
T64 5561 25 0 0
T65 0 15 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 160099288 0 0
T4 71335 71171 0 0
T6 966 918 0 0
T7 1045 973 0 0
T24 742 695 0 0
T28 6427 6418 0 0
T29 2654 2560 0 0
T30 587 552 0 0
T31 1392 1365 0 0
T32 2429 2403 0 0
T33 632 621 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT29,T31,T32
10CoveredT4,T29,T32

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT4,T29,T31
11CoveredT4,T29,T31

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT6,T4,T7
01Unreachable
10CoveredT4,T29,T31

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T29,T31
11CoveredT4,T29,T31

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT6,T4,T7
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T29,T31
0 0 1 Covered T4,T29,T31
0 0 0 Covered T6,T4,T7


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T4,T7
0 1 - Covered T4,T29,T31
0 0 1 Covered T4,T29,T31
0 0 0 Covered T6,T4,T7


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 162395068 159955 0 0
DstReqKnown_A 238816711 236753154 0 0
SrcAckBusyChk_A 162395068 30431 0 0
SrcBusyKnown_A 162395068 160099288 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 159955 0 0
T4 71335 99 0 0
T7 1045 0 0 0
T24 742 0 0 0
T29 2654 132 0 0
T31 1392 6 0 0
T32 2429 19 0 0
T33 632 8 0 0
T42 1256 13 0 0
T43 2983 70 0 0
T44 0 288 0 0
T64 5561 29 0 0
T65 0 83 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238816711 236753154 0 0
T4 32419 32338 0 0
T6 946 899 0 0
T7 1068 994 0 0
T24 1697 1588 0 0
T28 34275 34229 0 0
T29 1327 1280 0 0
T30 1342 1262 0 0
T31 13377 13117 0 0
T32 4859 4806 0 0
T33 4336 4255 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 30431 0 0
T4 71335 12 0 0
T7 1045 0 0 0
T24 742 0 0 0
T29 2654 15 0 0
T31 1392 2 0 0
T32 2429 5 0 0
T33 632 4 0 0
T42 1256 3 0 0
T43 2983 24 0 0
T44 0 35 0 0
T64 5561 8 0 0
T65 0 32 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 162395068 160099288 0 0
T4 71335 71171 0 0
T6 966 918 0 0
T7 1045 973 0 0
T24 742 695 0 0
T28 6427 6418 0 0
T29 2654 2560 0 0
T30 587 552 0 0
T31 1392 1365 0 0
T32 2429 2403 0 0
T33 632 621 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%