Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	724452430	65519	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724452430	65519	0	0
T1	1200270	1080	0	0
T2	117895	40	0	0
T3	0	406	0	0
T4	116320	0	0	0
T5	85245	0	0	0
T10	0	306	0	0
T11	0	344	0	0
T12	0	150	0	0
T13	0	129	0	0
T14	0	30	0	0
T15	0	1114	0	0
T16	0	1291	0	0
T17	5185	0	0	0
T18	23315	0	0	0
T19	4640	0	0	0
T20	4820	0	0	0
T21	5685	0	0	0
T22	11410	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	144890486	9654	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144890486	9654	0	0
T1	240054	159	0	0
T2	23579	7	0	0
T3	0	63	0	0
T4	23264	0	0	0
T5	17049	0	0	0
T10	0	49	0	0
T11	0	50	0	0
T12	0	24	0	0
T13	0	19	0	0
T14	0	6	0	0
T15	0	220	0	0
T16	0	181	0	0
T17	1037	0	0	0
T18	4663	0	0	0
T19	928	0	0	0
T20	964	0	0	0
T21	1137	0	0	0
T22	2282	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	144890486	13155	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144890486	13155	0	0
T1	240054	223	0	0
T2	23579	8	0	0
T3	0	83	0	0
T4	23264	0	0	0
T5	17049	0	0	0
T10	0	63	0	0
T11	0	68	0	0
T12	0	30	0	0
T13	0	25	0	0
T14	0	6	0	0
T15	0	220	0	0
T16	0	256	0	0
T17	1037	0	0	0
T18	4663	0	0	0
T19	928	0	0	0
T20	964	0	0	0
T21	1137	0	0	0
T22	2282	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	144890486	20129	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144890486	20129	0	0
T1	240054	356	0	0
T2	23579	11	0	0
T3	0	114	0	0
T4	23264	0	0	0
T5	17049	0	0	0
T10	0	85	0	0
T11	0	107	0	0
T12	0	42	0	0
T13	0	38	0	0
T14	0	6	0	0
T15	0	234	0	0
T16	0	416	0	0
T17	1037	0	0	0
T18	4663	0	0	0
T19	928	0	0	0
T20	964	0	0	0
T21	1137	0	0	0
T22	2282	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	144890486	9434	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144890486	9434	0	0
T1	240054	134	0	0
T2	23579	6	0	0
T3	0	63	0	0
T4	23264	0	0	0
T5	17049	0	0	0
T10	0	47	0	0
T11	0	50	0	0
T12	0	23	0	0
T13	0	18	0	0
T14	0	6	0	0
T15	0	220	0	0
T16	0	180	0	0
T17	1037	0	0	0
T18	4663	0	0	0
T19	928	0	0	0
T20	964	0	0	0
T21	1137	0	0	0
T22	2282	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	144890486	13147	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144890486	13147	0	0
T1	240054	208	0	0
T2	23579	8	0	0
T3	0	83	0	0
T4	23264	0	0	0
T5	17049	0	0	0
T10	0	62	0	0
T11	0	69	0	0
T12	0	31	0	0
T13	0	29	0	0
T14	0	6	0	0
T15	0	220	0	0
T16	0	258	0	0
T17	1037	0	0	0
T18	4663	0	0	0
T19	928	0	0	0
T20	964	0	0	0
T21	1137	0	0	0
T22	2282	0	0	0