Module Definition
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Module : clkmgr
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.66 100.00 93.15 90.16 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 98.63 100.00 93.15 100.00 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.63 100.00 93.15 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.47 99.15 95.84 100.00 100.00 98.81 97.01


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
clkmgr_aes_trans_sva_if 100.00 100.00
clkmgr_aon_cg_aon_peri 100.00 100.00
clkmgr_aon_cg_aon_powerup 100.00 100.00
clkmgr_aon_cg_aon_secure 100.00 100.00
clkmgr_aon_cg_aon_timers 100.00 100.00
clkmgr_aon_cg_io_div2_powerup 100.00 100.00
clkmgr_aon_cg_io_div4_powerup 100.00 100.00
clkmgr_aon_cg_io_powerup 100.00 100.00
clkmgr_aon_cg_main_powerup 100.00 100.00
clkmgr_aon_cg_usb_powerup 100.00 100.00
clkmgr_cg_io_div2_infra 100.00 100.00 100.00 100.00
clkmgr_cg_io_div2_peri 100.00 100.00 100.00 100.00
clkmgr_cg_io_div4_infra 100.00 100.00 100.00 100.00
clkmgr_cg_io_div4_peri 100.00 100.00 100.00 100.00
clkmgr_cg_io_div4_secure 100.00 100.00 100.00 100.00
clkmgr_cg_io_div4_timers 100.00 100.00 100.00 100.00
clkmgr_cg_io_infra 100.00 100.00 100.00 100.00
clkmgr_cg_io_peri 100.00 100.00 100.00 100.00
clkmgr_cg_main_aes 100.00 100.00 100.00 100.00
clkmgr_cg_main_hmac 100.00 100.00 100.00 100.00
clkmgr_cg_main_infra 100.00 100.00 100.00 100.00
clkmgr_cg_main_kmac 100.00 100.00 100.00 100.00
clkmgr_cg_main_otbn 100.00 100.00 100.00 100.00
clkmgr_cg_main_secure 100.00 100.00 100.00 100.00
clkmgr_cg_usb_peri 100.00 100.00 100.00 100.00
clkmgr_csr_assert 100.00 100.00
clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
clkmgr_div4_sva_if 100.00 100.00 100.00 100.00
clkmgr_extclk_sva_if 100.00 100.00 100.00 100.00
clkmgr_hmac_trans_sva_if 100.00 100.00
clkmgr_io_div2_peri_sva_if 100.00 100.00 100.00 100.00
clkmgr_io_div4_peri_sva_if 100.00 100.00 100.00 100.00
clkmgr_io_peri_sva_if 100.00 100.00 100.00 100.00
clkmgr_kmac_trans_sva_if 100.00 100.00
clkmgr_lost_calib_io_ctrl_en_sva_if 100.00 100.00
clkmgr_lost_calib_io_div2_ctrl_en_sva_if 100.00 100.00
clkmgr_lost_calib_io_div4_ctrl_en_sva_if 100.00 100.00
clkmgr_lost_calib_main_ctrl_en_sva_if 100.00 100.00
clkmgr_lost_calib_regwen_sva_if 100.00 100.00
clkmgr_lost_calib_usb_ctrl_en_sva_if 100.00 100.00
clkmgr_otbn_trans_sva_if 100.00 100.00
clkmgr_pwrmgr_sva_if 100.00 100.00
clkmgr_sec_cm_checker_assert 100.00 100.00 100.00 100.00
clkmgr_usb_peri_sva_if 100.00 100.00 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 99.30 100.00 100.00 97.90
u_calib_rdy_sync 100.00 100.00 100.00 100.00
u_clk_aon_peri_buf 100.00 100.00
u_clk_aon_powerup_buf 100.00 100.00
u_clk_aon_secure_buf 100.00 100.00
u_clk_aon_timers_buf 100.00 100.00
u_clk_io_div2_peri_cg 100.00 100.00 100.00 100.00
u_clk_io_div2_peri_scanmode_sync 100.00 100.00 100.00
u_clk_io_div2_peri_sw_en_sync 100.00 100.00 100.00
u_clk_io_div2_powerup_buf 100.00 100.00
u_clk_io_div4_peri_cg 100.00 100.00 100.00 100.00
u_clk_io_div4_peri_scanmode_sync 100.00 100.00 100.00
u_clk_io_div4_peri_sw_en_sync 100.00 100.00 100.00
u_clk_io_div4_powerup_buf 100.00 100.00
u_clk_io_peri_cg 100.00 100.00 100.00 100.00
u_clk_io_peri_scanmode_sync 100.00 100.00 100.00
u_clk_io_peri_sw_en_sync 100.00 100.00 100.00
u_clk_io_powerup_buf 100.00 100.00
u_clk_main_aes_trans 100.00 100.00 100.00 100.00 100.00 100.00
u_clk_main_hmac_trans 100.00 100.00 100.00 100.00 100.00 100.00
u_clk_main_kmac_trans 100.00 100.00 100.00 100.00 100.00 100.00
u_clk_main_otbn_trans 100.00 100.00 100.00 100.00 100.00 100.00
u_clk_main_powerup_buf 100.00 100.00
u_clk_usb_peri_cg 100.00 100.00 100.00 100.00
u_clk_usb_peri_scanmode_sync 100.00 100.00 100.00
u_clk_usb_peri_sw_en_sync 100.00 100.00 100.00
u_clk_usb_powerup_buf 100.00 100.00
u_clkmgr_byp 100.00 100.00 100.00 100.00 100.00
u_io_div2_div_scanmode_sync 100.00 100.00 100.00
u_io_div2_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_io_div2_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_io_div4_div_scanmode_sync 100.00 100.00 100.00
u_io_div4_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_io_div4_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_io_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_io_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_io_status 100.00 100.00 100.00
u_io_step_down_req_sync 100.00 100.00 100.00 100.00 100.00
u_main_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_main_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_main_status 100.00 100.00 100.00
u_no_scan_io_div2_div 100.00 100.00 100.00 100.00 100.00
u_no_scan_io_div4_div 100.00 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div2_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div2_peri 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div4_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div4_peri 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div4_secure 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div4_timers 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_peri 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_main_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_main_secure 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_usb_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_usb_peri 100.00 100.00 100.00 100.00
u_reg 97.64 98.39 95.43 100.00 97.91 96.48
u_usb_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_usb_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_usb_status 100.00 100.00 100.00

Line Coverage for Module : clkmgr
Line No.TotalCoveredPercent
TOTAL3434100.00
CONT_ASSIGN23511100.00
CONT_ASSIGN24111100.00
CONT_ASSIGN25411100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN38311100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN38911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN43711100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN48611100.00
ALWAYS52755100.00
CONT_ASSIGN67411100.00
CONT_ASSIGN68511100.00
CONT_ASSIGN69611100.00
CONT_ASSIGN70711100.00
CONT_ASSIGN71811100.00
CONT_ASSIGN72911100.00
CONT_ASSIGN74011100.00
CONT_ASSIGN75111100.00
CONT_ASSIGN79411100.00
CONT_ASSIGN83611100.00
CONT_ASSIGN87811100.00
CONT_ASSIGN92011100.00
CONT_ASSIGN103711100.00
CONT_ASSIGN104611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr.sv' or '../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
235 1 1
241 1 1
254 1 1
284 1 1
285 1 1
383 1 1
388 1 1
389 1 1
390 1 1
393 1 1
412 1 1
437 1 1
449 1 1
461 1 1
486 1 1
527 1 1
528 1 1
530 1 1
531 1 1
532 1 1
MISSING_ELSE
674 1 1
685 1 1
696 1 1
707 1 1
718 1 1
729 1 1
740 1 1
751 1 1
794 1 1
836 1 1
878 1 1
920 1 1
1037 1 1
1046 1 1


Cond Coverage for Module : clkmgr
TotalCoveredPercent
Conditions14613693.15
Logical14613693.15
Non-Logical00
Event00

 LINE       28
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       37
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       46
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       55
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       65
 EXPRESSION (idle_i[0] == MuBi4True)
            ------------1-----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       65
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       75
 EXPRESSION (idle_i[1] == MuBi4True)
            ------------1-----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       75
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       85
 EXPRESSION (idle_i[2] == MuBi4True)
            ------------1-----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       85
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       95
 EXPRESSION (idle_i[3] == MuBi4True)
            ------------1-----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       95
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       119
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T8,T1

 LINE       119
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       130
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T8,T1

 LINE       130
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       139
 EXPRESSION (cg_en_o.aon_peri == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       143
 EXPRESSION (cg_en_o.aon_powerup == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       147
 EXPRESSION (cg_en_o.aon_secure == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       151
 EXPRESSION (cg_en_o.aon_timers == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       155
 EXPRESSION (cg_en_o.io_powerup == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       159
 EXPRESSION (cg_en_o.io_div2_powerup == MuBi4True)
            -------------------1------------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       165
 EXPRESSION (cg_en_o.io_div4_powerup == MuBi4True)
            -------------------1------------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       171
 EXPRESSION (cg_en_o.main_powerup == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       175
 EXPRESSION (cg_en_o.usb_powerup == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       180
 EXPRESSION (cg_en_o.io_div2_infra == MuBi4True)
            ------------------1-----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       189
 EXPRESSION (cg_en_o.io_div4_infra == MuBi4True)
            ------------------1-----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       198
 EXPRESSION (cg_en_o.io_infra == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       207
 EXPRESSION (cg_en_o.main_infra == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       216
 EXPRESSION (cg_en_o.io_div4_secure == MuBi4True)
            ------------------1------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       225
 EXPRESSION (cg_en_o.main_secure == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       234
 EXPRESSION (cg_en_o.io_div4_timers == MuBi4True)
            ------------------1------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       235
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe)
                 ---------------1---------------   ----------------2---------------
-1--2-StatusTests
01CoveredT37,T38,T39
10CoveredT6,T7,T8
11CoveredT37,T38,T39

 LINE       235
 SUB-EXPRESSION (reg2hw.alert_test.recov_fault.q & reg2hw.alert_test.recov_fault.qe)
                 ---------------1---------------   ----------------2---------------
-1--2-StatusTests
01CoveredT37,T38,T39
10CoveredT6,T7,T8
11CoveredT37,T38,T39

 LINE       241
 EXPRESSION 
 Number  Term
      1  hw2reg.recov_err_code.io_measure_err.de | 
      2  hw2reg.recov_err_code.io_timeout_err.de | 
      3  hw2reg.recov_err_code.io_div2_measure_err.de | 
      4  hw2reg.recov_err_code.io_div2_timeout_err.de | 
      5  hw2reg.recov_err_code.io_div4_measure_err.de | 
      6  hw2reg.recov_err_code.io_div4_timeout_err.de | 
      7  hw2reg.recov_err_code.main_measure_err.de | 
      8  hw2reg.recov_err_code.main_timeout_err.de | 
      9  hw2reg.recov_err_code.usb_measure_err.de | 
     10  hw2reg.recov_err_code.usb_timeout_err.de | 
     11  hw2reg.recov_err_code.shadow_update_err.de)
-1--2--3--4--5--6--7--8--9--10--11-StatusTests
00000000000CoveredT6,T7,T8
00000000001Not Covered
00000000010CoveredT1,T27,T10
00000000100CoveredT1,T2,T3
00000001000CoveredT1,T10,T11
00000010000CoveredT1,T3,T10
00000100000CoveredT1,T27,T10
00001000000CoveredT1,T2,T3
00010000000CoveredT40,T41,T42
00100000000CoveredT1,T2,T3
01000000000CoveredT40,T41,T42
10000000000CoveredT1,T2,T3

 LINE       243
 EXPRESSION (cg_en_o.io_div2_peri == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       252
 EXPRESSION (cg_en_o.io_div4_peri == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       261
 EXPRESSION (cg_en_o.io_peri == MuBi4True)
            ---------------1--------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       270
 EXPRESSION (cg_en_o.usb_peri == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       279
 EXPRESSION (clkmgr.u_clk_main_aes_trans.sw_hint_synced || ((!clkmgr.u_clk_main_aes_trans.idle_valid)))
             ---------------------1--------------------    ---------------------2---------------------
-1--2-StatusTests
00CoveredT6,T1,T18
01CoveredT6,T7,T8
10CoveredT6,T7,T8

 LINE       279
 EXPRESSION (cg_en_o.main_aes == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       288
 EXPRESSION (clkmgr.u_clk_main_hmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_hmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------
-1--2-StatusTests
00CoveredT6,T1,T18
01CoveredT6,T7,T8
10CoveredT6,T7,T8

 LINE       288
 EXPRESSION (cg_en_o.main_hmac == MuBi4True)
            ----------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       297
 EXPRESSION (clkmgr.u_clk_main_kmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_kmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------
-1--2-StatusTests
00CoveredT6,T1,T18
01CoveredT6,T7,T8
10CoveredT6,T7,T8

 LINE       297
 EXPRESSION (cg_en_o.main_kmac == MuBi4True)
            ----------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       306
 EXPRESSION (clkmgr.u_clk_main_otbn_trans.sw_hint_synced || ((!clkmgr.u_clk_main_otbn_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------
-1--2-StatusTests
00CoveredT6,T1,T18
01CoveredT6,T7,T8
10CoveredT6,T7,T8

 LINE       306
 EXPRESSION (cg_en_o.main_otbn == MuBi4True)
            ----------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       679
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       690
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       701
 EXPRESSION (clk_usb_en ? MuBi4False : MuBi4True)
             -----1----
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       712
 EXPRESSION (clk_io_en ? MuBi4False : MuBi4True)
             ----1----
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       723
 EXPRESSION (clk_io_div2_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       734
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       745
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       756
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       794
 EXPRESSION (clk_io_div4_peri_sw_en & clk_io_div4_en)
             -----------1----------   -------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT43,T44,T45
11CoveredT6,T7,T8

 LINE       807
 EXPRESSION (clk_io_div4_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       836
 EXPRESSION (clk_io_div2_peri_sw_en & clk_io_div2_en)
             -----------1----------   -------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT43,T44,T45
11CoveredT6,T7,T8

 LINE       849
 EXPRESSION (clk_io_div2_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       878
 EXPRESSION (clk_io_peri_sw_en & clk_io_en)
             --------1--------   ----2----
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT43,T44,T45
11CoveredT6,T7,T8

 LINE       891
 EXPRESSION (clk_io_peri_combined_en ? MuBi4False : MuBi4True)
             -----------1-----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       920
 EXPRESSION (clk_usb_peri_sw_en & clk_usb_en)
             ---------1--------   -----2----
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT43,T44,T45
11CoveredT6,T7,T8

 LINE       933
 EXPRESSION (clk_usb_peri_combined_en ? MuBi4False : MuBi4True)
             ------------1-----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

Toggle Coverage for Module : clkmgr
TotalCoveredPercent
Totals 115 106 92.17
Total Bits 732 660 90.16
Total Bits 0->1 366 330 90.16
Total Bits 1->0 366 330 90.16

Ports 115 106 92.17
Port Bits 732 660 90.16
Port Bits 0->1 366 330 90.16
Port Bits 1->0 366 330 90.16

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
rst_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_shadowed_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
clk_main_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
rst_main_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
clk_io_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
rst_io_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
clk_usb_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
rst_usb_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
clk_aon_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
rst_aon_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_io_div2_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_io_div4_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_root_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_root_main_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_root_io_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_root_io_div2_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_root_io_div4_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_root_usb_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
tl_i.d_ready Yes Yes T6,T7,T30 Yes T6,T7,T8 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T8,T30,T31 Yes T8,T30,T31 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_mask[3:0] Yes Yes T6,T8,T30 Yes T6,T8,T30 INPUT
tl_i.a_address[31:0] Yes Yes T6,T8,T30 Yes T6,T8,T30 INPUT
tl_i.a_source[7:0] Yes Yes T6,T8,T30 Yes T6,T8,T30 INPUT
tl_i.a_size[1:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_valid Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_o.a_ready Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
tl_o.d_error Yes Yes T34,T46,T47 Yes T34,T48,T46 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T6,T8,T30 Yes T6,T8,T30 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T6,*T7,*T8 Yes T6,T7,T8 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T6,T8,T30 Yes T6,T7,T8 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T6,T8,T30 Yes T6,T8,T30 OUTPUT
tl_o.d_size[1:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T6,*T8,*T30 Yes T6,T8,T30 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
alert_rx_i[0].ack_n Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
alert_rx_i[0].ack_p Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
alert_rx_i[1].ack_p Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
alert_tx_o[0].alert_p Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
alert_tx_o[1].alert_n Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
alert_tx_o[1].alert_p Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
pwr_i.usb_ip_clk_en Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
pwr_i.io_ip_clk_en Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
pwr_i.main_ip_clk_en Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
pwr_o.usb_status Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
pwr_o.io_status Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
pwr_o.main_status Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
scanmode_i[3:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 INPUT
lc_clk_byp_req_i[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 INPUT
lc_clk_byp_ack_o[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 OUTPUT
io_clk_byp_req_o[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 OUTPUT
io_clk_byp_ack_i[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 INPUT
all_clk_byp_req_o[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 OUTPUT
all_clk_byp_ack_i[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 INPUT
hi_speed_sel_o[3:0] Yes Yes T6,T8,T30 Yes T6,T7,T8 OUTPUT
calib_rdy_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jitter_en_o[3:0] Yes Yes T49,T50,T51 Yes T50,T52,T53 OUTPUT
div_step_down_req_i[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 INPUT
cg_en_o.usb_peri[3:0] Yes Yes T6,T7,T30 Yes T6,T7,T8 OUTPUT
cg_en_o.io_peri[3:0] Yes Yes T6,T7,T30 Yes T6,T7,T8 OUTPUT
cg_en_o.io_div2_peri[3:0] Yes Yes T6,T7,T30 Yes T6,T7,T8 OUTPUT
cg_en_o.io_div4_peri[3:0] Yes Yes T6,T7,T30 Yes T6,T7,T8 OUTPUT
cg_en_o.io_div4_timers[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.main_secure[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.io_div4_secure[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.io_div2_infra[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.io_infra[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.usb_infra[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.main_infra[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.io_div4_infra[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.main_otbn[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.main_kmac[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.main_hmac[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.main_aes[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.aon_timers[3:0] No No No OUTPUT
cg_en_o.aon_peri[3:0] No No No OUTPUT
cg_en_o.aon_secure[3:0] No No No OUTPUT
cg_en_o.io_div2_powerup[3:0] No No No OUTPUT
cg_en_o.usb_powerup[3:0] No No No OUTPUT
cg_en_o.io_powerup[3:0] No No No OUTPUT
cg_en_o.main_powerup[3:0] No No No OUTPUT
cg_en_o.aon_powerup[3:0] No No No OUTPUT
cg_en_o.io_div4_powerup[3:0] No No No OUTPUT
clocks_o.clk_usb_peri Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_peri Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div2_peri Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div4_peri Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div4_timers Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_secure Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div4_secure Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div2_infra Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_infra Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_usb_infra Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_infra Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div4_infra Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_otbn Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_kmac Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_hmac Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_aes Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_aon_timers Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_aon_peri Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_aon_secure Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div2_powerup Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_usb_powerup Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_powerup Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_powerup Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_aon_powerup Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div4_powerup Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : clkmgr
Line No.TotalCoveredPercent
Branches 26 26 100.00
TERNARY 679 2 2 100.00
TERNARY 690 2 2 100.00
TERNARY 701 2 2 100.00
TERNARY 712 2 2 100.00
TERNARY 723 2 2 100.00
TERNARY 734 2 2 100.00
TERNARY 745 2 2 100.00
TERNARY 756 2 2 100.00
TERNARY 807 2 2 100.00
TERNARY 849 2 2 100.00
TERNARY 891 2 2 100.00
TERNARY 933 2 2 100.00
IF 530 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr.sv' or '../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 679 (clk_io_div4_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 690 (clk_main_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 701 (clk_usb_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 712 (clk_io_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 723 (clk_io_div2_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 734 (clk_io_div4_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 745 (clk_main_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 756 (clk_io_div4_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 807 (clk_io_div4_peri_combined_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 849 (clk_io_div2_peri_combined_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 891 (clk_io_peri_combined_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 933 (clk_usb_peri_combined_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 530 if (prim_mubi_pkg::mubi4_test_false_strict(calib_rdy[BaseIdx]))

Branches:
-1-StatusTests
1 Covered T6,T1,T18
0 Covered T6,T7,T8


Assert Coverage for Module : clkmgr
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnownO_A 144890486 142484600 0 0
AllClkBypReqKnownO_A 144890486 142484600 0 0
CgEnKnownO_A 144890486 142484600 0 0
ClocksKownO_A 144890486 142484600 0 0
FpvSecCmClkMainAesCountCheck_A 144890486 15 0 0
FpvSecCmClkMainHmacCountCheck_A 144890486 20 0 0
FpvSecCmClkMainKmacCountCheck_A 144890486 16 0 0
FpvSecCmClkMainOtbnCountCheck_A 144890486 17 0 0
FpvSecCmRegWeOnehotCheck_A 144890486 80 0 0
IoClkBypReqKnownO_A 144890486 142484600 0 0
JitterEnableKnownO_A 144890486 142484600 0 0
LcCtrlClkBypAckKnownO_A 144890486 142484600 0 0
PwrMgrKnownO_A 144890486 142484600 0 0
TlAReadyKnownO_A 144890486 142484600 0 0
TlDValidKnownO_A 144890486 142484600 0 0


AlertsKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

AllClkBypReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

CgEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

ClocksKownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

FpvSecCmClkMainAesCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 15 0 0
T54 14252 5 0 0
T55 0 10 0 0
T56 1027 0 0 0
T57 2529 0 0 0
T58 2194 0 0 0
T59 1204 0 0 0
T60 98149 0 0 0
T61 1036 0 0 0
T62 1554 0 0 0
T63 2269 0 0 0
T64 151435 0 0 0

FpvSecCmClkMainHmacCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 20 0 0
T54 14252 10 0 0
T55 0 10 0 0
T56 1027 0 0 0
T57 2529 0 0 0
T58 2194 0 0 0
T59 1204 0 0 0
T60 98149 0 0 0
T61 1036 0 0 0
T62 1554 0 0 0
T63 2269 0 0 0
T64 151435 0 0 0

FpvSecCmClkMainKmacCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 16 0 0
T54 14252 5 0 0
T55 0 10 0 0
T56 1027 0 0 0
T57 2529 0 0 0
T58 2194 0 0 0
T59 1204 0 0 0
T60 98149 0 0 0
T61 1036 0 0 0
T62 1554 0 0 0
T63 2269 0 0 0
T64 151435 0 0 0
T65 0 1 0 0

FpvSecCmClkMainOtbnCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 17 0 0
T54 14252 7 0 0
T55 0 10 0 0
T56 1027 0 0 0
T57 2529 0 0 0
T58 2194 0 0 0
T59 1204 0 0 0
T60 98149 0 0 0
T61 1036 0 0 0
T62 1554 0 0 0
T63 2269 0 0 0
T64 151435 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 80 0 0
T54 14252 20 0 0
T55 0 10 0 0
T56 1027 0 0 0
T57 2529 0 0 0
T58 2194 0 0 0
T59 1204 0 0 0
T60 98149 0 0 0
T61 1036 0 0 0
T62 1554 0 0 0
T63 2269 0 0 0
T64 151435 0 0 0
T65 0 10 0 0
T66 0 20 0 0
T67 0 20 0 0

IoClkBypReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

JitterEnableKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

LcCtrlClkBypAckKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

PwrMgrKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL3434100.00
CONT_ASSIGN23511100.00
CONT_ASSIGN24111100.00
CONT_ASSIGN25411100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN38311100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN38911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN43711100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN48611100.00
ALWAYS52755100.00
CONT_ASSIGN67411100.00
CONT_ASSIGN68511100.00
CONT_ASSIGN69611100.00
CONT_ASSIGN70711100.00
CONT_ASSIGN71811100.00
CONT_ASSIGN72911100.00
CONT_ASSIGN74011100.00
CONT_ASSIGN75111100.00
CONT_ASSIGN79411100.00
CONT_ASSIGN83611100.00
CONT_ASSIGN87811100.00
CONT_ASSIGN92011100.00
CONT_ASSIGN103711100.00
CONT_ASSIGN104611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr.sv' or '../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
235 1 1
241 1 1
254 1 1
284 1 1
285 1 1
383 1 1
388 1 1
389 1 1
390 1 1
393 1 1
412 1 1
437 1 1
449 1 1
461 1 1
486 1 1
527 1 1
528 1 1
530 1 1
531 1 1
532 1 1
MISSING_ELSE
674 1 1
685 1 1
696 1 1
707 1 1
718 1 1
729 1 1
740 1 1
751 1 1
794 1 1
836 1 1
878 1 1
920 1 1
1037 1 1
1046 1 1


Cond Coverage for Instance : tb.dut
TotalCoveredPercent
Conditions14613693.15
Logical14613693.15
Non-Logical00
Event00

 LINE       28
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       37
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       46
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       55
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       65
 EXPRESSION (idle_i[0] == MuBi4True)
            ------------1-----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       65
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       75
 EXPRESSION (idle_i[1] == MuBi4True)
            ------------1-----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       75
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       85
 EXPRESSION (idle_i[2] == MuBi4True)
            ------------1-----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       85
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       95
 EXPRESSION (idle_i[3] == MuBi4True)
            ------------1-----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       95
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       119
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T8,T1

 LINE       119
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       130
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T8,T1

 LINE       130
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       139
 EXPRESSION (cg_en_o.aon_peri == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       143
 EXPRESSION (cg_en_o.aon_powerup == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       147
 EXPRESSION (cg_en_o.aon_secure == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       151
 EXPRESSION (cg_en_o.aon_timers == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       155
 EXPRESSION (cg_en_o.io_powerup == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       159
 EXPRESSION (cg_en_o.io_div2_powerup == MuBi4True)
            -------------------1------------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       165
 EXPRESSION (cg_en_o.io_div4_powerup == MuBi4True)
            -------------------1------------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       171
 EXPRESSION (cg_en_o.main_powerup == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       175
 EXPRESSION (cg_en_o.usb_powerup == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1Not Covered

 LINE       180
 EXPRESSION (cg_en_o.io_div2_infra == MuBi4True)
            ------------------1-----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       189
 EXPRESSION (cg_en_o.io_div4_infra == MuBi4True)
            ------------------1-----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       198
 EXPRESSION (cg_en_o.io_infra == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       207
 EXPRESSION (cg_en_o.main_infra == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       216
 EXPRESSION (cg_en_o.io_div4_secure == MuBi4True)
            ------------------1------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       225
 EXPRESSION (cg_en_o.main_secure == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       234
 EXPRESSION (cg_en_o.io_div4_timers == MuBi4True)
            ------------------1------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       235
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe)
                 ---------------1---------------   ----------------2---------------
-1--2-StatusTests
01CoveredT37,T38,T39
10CoveredT6,T7,T8
11CoveredT37,T38,T39

 LINE       235
 SUB-EXPRESSION (reg2hw.alert_test.recov_fault.q & reg2hw.alert_test.recov_fault.qe)
                 ---------------1---------------   ----------------2---------------
-1--2-StatusTests
01CoveredT37,T38,T39
10CoveredT6,T7,T8
11CoveredT37,T38,T39

 LINE       241
 EXPRESSION 
 Number  Term
      1  hw2reg.recov_err_code.io_measure_err.de | 
      2  hw2reg.recov_err_code.io_timeout_err.de | 
      3  hw2reg.recov_err_code.io_div2_measure_err.de | 
      4  hw2reg.recov_err_code.io_div2_timeout_err.de | 
      5  hw2reg.recov_err_code.io_div4_measure_err.de | 
      6  hw2reg.recov_err_code.io_div4_timeout_err.de | 
      7  hw2reg.recov_err_code.main_measure_err.de | 
      8  hw2reg.recov_err_code.main_timeout_err.de | 
      9  hw2reg.recov_err_code.usb_measure_err.de | 
     10  hw2reg.recov_err_code.usb_timeout_err.de | 
     11  hw2reg.recov_err_code.shadow_update_err.de)
-1--2--3--4--5--6--7--8--9--10--11-StatusTests
00000000000CoveredT6,T7,T8
00000000001Not Covered
00000000010CoveredT1,T27,T10
00000000100CoveredT1,T2,T3
00000001000CoveredT1,T10,T11
00000010000CoveredT1,T3,T10
00000100000CoveredT1,T27,T10
00001000000CoveredT1,T2,T3
00010000000CoveredT40,T41,T42
00100000000CoveredT1,T2,T3
01000000000CoveredT40,T41,T42
10000000000CoveredT1,T2,T3

 LINE       243
 EXPRESSION (cg_en_o.io_div2_peri == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       252
 EXPRESSION (cg_en_o.io_div4_peri == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       261
 EXPRESSION (cg_en_o.io_peri == MuBi4True)
            ---------------1--------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       270
 EXPRESSION (cg_en_o.usb_peri == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       279
 EXPRESSION (clkmgr.u_clk_main_aes_trans.sw_hint_synced || ((!clkmgr.u_clk_main_aes_trans.idle_valid)))
             ---------------------1--------------------    ---------------------2---------------------
-1--2-StatusTests
00CoveredT6,T1,T18
01CoveredT6,T7,T8
10CoveredT6,T7,T8

 LINE       279
 EXPRESSION (cg_en_o.main_aes == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       288
 EXPRESSION (clkmgr.u_clk_main_hmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_hmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------
-1--2-StatusTests
00CoveredT6,T1,T18
01CoveredT6,T7,T8
10CoveredT6,T7,T8

 LINE       288
 EXPRESSION (cg_en_o.main_hmac == MuBi4True)
            ----------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       297
 EXPRESSION (clkmgr.u_clk_main_kmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_kmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------
-1--2-StatusTests
00CoveredT6,T1,T18
01CoveredT6,T7,T8
10CoveredT6,T7,T8

 LINE       297
 EXPRESSION (cg_en_o.main_kmac == MuBi4True)
            ----------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       306
 EXPRESSION (clkmgr.u_clk_main_otbn_trans.sw_hint_synced || ((!clkmgr.u_clk_main_otbn_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------
-1--2-StatusTests
00CoveredT6,T1,T18
01CoveredT6,T7,T8
10CoveredT6,T7,T8

 LINE       306
 EXPRESSION (cg_en_o.main_otbn == MuBi4True)
            ----------------1---------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       679
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       690
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       701
 EXPRESSION (clk_usb_en ? MuBi4False : MuBi4True)
             -----1----
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       712
 EXPRESSION (clk_io_en ? MuBi4False : MuBi4True)
             ----1----
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       723
 EXPRESSION (clk_io_div2_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       734
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       745
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       756
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       794
 EXPRESSION (clk_io_div4_peri_sw_en & clk_io_div4_en)
             -----------1----------   -------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT43,T44,T45
11CoveredT6,T7,T8

 LINE       807
 EXPRESSION (clk_io_div4_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       836
 EXPRESSION (clk_io_div2_peri_sw_en & clk_io_div2_en)
             -----------1----------   -------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT43,T44,T45
11CoveredT6,T7,T8

 LINE       849
 EXPRESSION (clk_io_div2_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       878
 EXPRESSION (clk_io_peri_sw_en & clk_io_en)
             --------1--------   ----2----
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT43,T44,T45
11CoveredT6,T7,T8

 LINE       891
 EXPRESSION (clk_io_peri_combined_en ? MuBi4False : MuBi4True)
             -----------1-----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       920
 EXPRESSION (clk_usb_peri_sw_en & clk_usb_en)
             ---------1--------   -----2----
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT43,T44,T45
11CoveredT6,T7,T8

 LINE       933
 EXPRESSION (clk_usb_peri_combined_en ? MuBi4False : MuBi4True)
             ------------1-----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 106 106 100.00
Total Bits 660 660 100.00
Total Bits 0->1 330 330 100.00
Total Bits 1->0 330 330 100.00

Ports 106 106 100.00
Port Bits 660 660 100.00
Port Bits 0->1 330 330 100.00
Port Bits 1->0 330 330 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
rst_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_shadowed_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
clk_main_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
rst_main_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
clk_io_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
rst_io_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
clk_usb_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
rst_usb_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
clk_aon_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
rst_aon_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_io_div2_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_io_div4_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_root_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_root_main_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_root_io_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_root_io_div2_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_root_io_div4_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
rst_root_usb_ni Yes Yes T6,T30,T33 Yes T6,T7,T8 INPUT
tl_i.d_ready Yes Yes T6,T7,T30 Yes T6,T7,T8 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T8,T30,T31 Yes T8,T30,T31 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_mask[3:0] Yes Yes T6,T8,T30 Yes T6,T8,T30 INPUT
tl_i.a_address[31:0] Yes Yes T6,T8,T30 Yes T6,T8,T30 INPUT
tl_i.a_source[7:0] Yes Yes T6,T8,T30 Yes T6,T8,T30 INPUT
tl_i.a_size[1:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_i.a_valid Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
tl_o.a_ready Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
tl_o.d_error Yes Yes T34,T46,T47 Yes T34,T48,T46 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T6,T8,T30 Yes T6,T8,T30 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T6,*T7,*T8 Yes T6,T7,T8 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T6,T8,T30 Yes T6,T7,T8 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T6,T8,T30 Yes T6,T8,T30 OUTPUT
tl_o.d_size[1:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T6,*T8,*T30 Yes T6,T8,T30 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
alert_rx_i[0].ack_n Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
alert_rx_i[0].ack_p Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
alert_rx_i[1].ack_p Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
alert_tx_o[0].alert_p Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
alert_tx_o[1].alert_n Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
alert_tx_o[1].alert_p Yes Yes T30,T31,T32 Yes T30,T31,T32 OUTPUT
pwr_i.usb_ip_clk_en Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
pwr_i.io_ip_clk_en Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
pwr_i.main_ip_clk_en Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
pwr_o.usb_status Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
pwr_o.io_status Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
pwr_o.main_status Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
scanmode_i[3:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 INPUT
lc_clk_byp_req_i[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 INPUT
lc_clk_byp_ack_o[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 OUTPUT
io_clk_byp_req_o[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 OUTPUT
io_clk_byp_ack_i[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 INPUT
all_clk_byp_req_o[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 OUTPUT
all_clk_byp_ack_i[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 INPUT
hi_speed_sel_o[3:0] Yes Yes T6,T8,T30 Yes T6,T7,T8 OUTPUT
calib_rdy_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jitter_en_o[3:0] Yes Yes T49,T50,T51 Yes T50,T52,T53 OUTPUT
div_step_down_req_i[3:0] Yes Yes T6,T8,T1 Yes T6,T8,T1 INPUT
cg_en_o.usb_peri[3:0] Yes Yes T6,T7,T30 Yes T6,T7,T8 OUTPUT
cg_en_o.io_peri[3:0] Yes Yes T6,T7,T30 Yes T6,T7,T8 OUTPUT
cg_en_o.io_div2_peri[3:0] Yes Yes T6,T7,T30 Yes T6,T7,T8 OUTPUT
cg_en_o.io_div4_peri[3:0] Yes Yes T6,T7,T30 Yes T6,T7,T8 OUTPUT
cg_en_o.io_div4_timers[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.main_secure[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.io_div4_secure[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.io_div2_infra[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.io_infra[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.usb_infra[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.main_infra[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.io_div4_infra[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.main_otbn[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.main_kmac[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.main_hmac[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.main_aes[3:0] Yes Yes T6,T30,T33 Yes T6,T7,T8 OUTPUT
cg_en_o.aon_timers[3:0] Excluded Excluded Excluded OUTPUT [UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.aon_peri[3:0] Excluded Excluded Excluded OUTPUT [UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.aon_secure[3:0] Excluded Excluded Excluded OUTPUT [UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.io_div2_powerup[3:0] Excluded Excluded Excluded OUTPUT [UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.usb_powerup[3:0] Excluded Excluded Excluded OUTPUT [UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.io_powerup[3:0] Excluded Excluded Excluded OUTPUT [UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.main_powerup[3:0] Excluded Excluded Excluded OUTPUT [UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.aon_powerup[3:0] Excluded Excluded Excluded OUTPUT [UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.io_div4_powerup[3:0] Excluded Excluded Excluded OUTPUT [UNR] This is driven by a constant, and unr doesn't detect it.
clocks_o.clk_usb_peri Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_peri Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div2_peri Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div4_peri Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div4_timers Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_secure Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div4_secure Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div2_infra Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_infra Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_usb_infra Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_infra Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div4_infra Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_otbn Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_kmac Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_hmac Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_aes Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_aon_timers Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_aon_peri Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_aon_secure Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div2_powerup Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_usb_powerup Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_powerup Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_main_powerup Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_aon_powerup Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
clocks_o.clk_io_div4_powerup Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
Branches 26 26 100.00
TERNARY 679 2 2 100.00
TERNARY 690 2 2 100.00
TERNARY 701 2 2 100.00
TERNARY 712 2 2 100.00
TERNARY 723 2 2 100.00
TERNARY 734 2 2 100.00
TERNARY 745 2 2 100.00
TERNARY 756 2 2 100.00
TERNARY 807 2 2 100.00
TERNARY 849 2 2 100.00
TERNARY 891 2 2 100.00
TERNARY 933 2 2 100.00
IF 530 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr.sv' or '../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 679 (clk_io_div4_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 690 (clk_main_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 701 (clk_usb_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 712 (clk_io_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 723 (clk_io_div2_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 734 (clk_io_div4_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 745 (clk_main_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 756 (clk_io_div4_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 807 (clk_io_div4_peri_combined_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 849 (clk_io_div2_peri_combined_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 891 (clk_io_peri_combined_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 933 (clk_usb_peri_combined_en) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 530 if (prim_mubi_pkg::mubi4_test_false_strict(calib_rdy[BaseIdx]))

Branches:
-1-StatusTests
1 Covered T6,T1,T18
0 Covered T6,T7,T8


Assert Coverage for Instance : tb.dut
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnownO_A 144890486 142484600 0 0
AllClkBypReqKnownO_A 144890486 142484600 0 0
CgEnKnownO_A 144890486 142484600 0 0
ClocksKownO_A 144890486 142484600 0 0
FpvSecCmClkMainAesCountCheck_A 144890486 15 0 0
FpvSecCmClkMainHmacCountCheck_A 144890486 20 0 0
FpvSecCmClkMainKmacCountCheck_A 144890486 16 0 0
FpvSecCmClkMainOtbnCountCheck_A 144890486 17 0 0
FpvSecCmRegWeOnehotCheck_A 144890486 80 0 0
IoClkBypReqKnownO_A 144890486 142484600 0 0
JitterEnableKnownO_A 144890486 142484600 0 0
LcCtrlClkBypAckKnownO_A 144890486 142484600 0 0
PwrMgrKnownO_A 144890486 142484600 0 0
TlAReadyKnownO_A 144890486 142484600 0 0
TlDValidKnownO_A 144890486 142484600 0 0


AlertsKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

AllClkBypReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

CgEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

ClocksKownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

FpvSecCmClkMainAesCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 15 0 0
T54 14252 5 0 0
T55 0 10 0 0
T56 1027 0 0 0
T57 2529 0 0 0
T58 2194 0 0 0
T59 1204 0 0 0
T60 98149 0 0 0
T61 1036 0 0 0
T62 1554 0 0 0
T63 2269 0 0 0
T64 151435 0 0 0

FpvSecCmClkMainHmacCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 20 0 0
T54 14252 10 0 0
T55 0 10 0 0
T56 1027 0 0 0
T57 2529 0 0 0
T58 2194 0 0 0
T59 1204 0 0 0
T60 98149 0 0 0
T61 1036 0 0 0
T62 1554 0 0 0
T63 2269 0 0 0
T64 151435 0 0 0

FpvSecCmClkMainKmacCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 16 0 0
T54 14252 5 0 0
T55 0 10 0 0
T56 1027 0 0 0
T57 2529 0 0 0
T58 2194 0 0 0
T59 1204 0 0 0
T60 98149 0 0 0
T61 1036 0 0 0
T62 1554 0 0 0
T63 2269 0 0 0
T64 151435 0 0 0
T65 0 1 0 0

FpvSecCmClkMainOtbnCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 17 0 0
T54 14252 7 0 0
T55 0 10 0 0
T56 1027 0 0 0
T57 2529 0 0 0
T58 2194 0 0 0
T59 1204 0 0 0
T60 98149 0 0 0
T61 1036 0 0 0
T62 1554 0 0 0
T63 2269 0 0 0
T64 151435 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 80 0 0
T54 14252 20 0 0
T55 0 10 0 0
T56 1027 0 0 0
T57 2529 0 0 0
T58 2194 0 0 0
T59 1204 0 0 0
T60 98149 0 0 0
T61 1036 0 0 0
T62 1554 0 0 0
T63 2269 0 0 0
T64 151435 0 0 0
T65 0 10 0 0
T66 0 20 0 0
T67 0 20 0 0

IoClkBypReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

JitterEnableKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

LcCtrlClkBypAckKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

PwrMgrKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 142484600 0 0
T1 240054 236915 0 0
T4 23264 4873 0 0
T6 5223 5056 0 0
T7 1059 1030 0 0
T8 2282 2203 0 0
T17 1037 924 0 0
T18 4663 4482 0 0
T19 928 897 0 0
T20 964 930 0 0
T21 1137 1082 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%