Module Definition
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Module : clkmgr_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.58 100.00 98.31 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.64 98.39 95.43 100.00 97.91 96.48


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test_fatal_fault 100.00 100.00
u_alert_test_recov_fault 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_clk_enables_clk_io_div2_peri_en 100.00 100.00 100.00 100.00
u_clk_enables_clk_io_div4_peri_en 100.00 100.00 100.00 100.00
u_clk_enables_clk_io_peri_en 100.00 100.00 100.00 100.00
u_clk_enables_clk_usb_peri_en 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_aes_hint 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_hmac_hint 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_kmac_hint 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_otbn_hint 100.00 100.00 100.00 100.00
u_clk_hints_status_clk_main_aes_val 92.59 77.78 100.00 100.00
u_clk_hints_status_clk_main_hmac_val 92.59 77.78 100.00 100.00
u_clk_hints_status_clk_main_kmac_val 92.59 77.78 100.00 100.00
u_clk_hints_status_clk_main_otbn_val 92.59 77.78 100.00 100.00
u_extclk_ctrl_hi_speed_sel 100.00 100.00 100.00 100.00
u_extclk_ctrl_regwen 100.00 100.00 100.00 100.00
u_extclk_ctrl_sel 100.00 100.00 100.00 100.00
u_extclk_status 100.00 100.00
u_fatal_err_code_idle_cnt 96.30 88.89 100.00 100.00
u_fatal_err_code_reg_intg 96.30 88.89 100.00 100.00
u_fatal_err_code_shadow_storage_err 96.30 88.89 100.00 100.00
u_io_div2_meas_ctrl_en 100.00 100.00 100.00 100.00
u_io_div2_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_io_div2_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_io_div2_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_io_div2_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_div2_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_io_div2_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_div4_meas_ctrl_en 100.00 100.00 100.00 100.00
u_io_div4_meas_ctrl_en_cdc 92.36 97.74 86.76 94.92 90.00
u_io_div4_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_io_div4_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_io_div4_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_div4_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_io_div4_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_meas_ctrl_en 100.00 100.00 100.00 100.00
u_io_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_io_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_io_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_io_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_io_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_io_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_io_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_jitter_enable 100.00 100.00 100.00 100.00
u_jitter_regwen 100.00 100.00 100.00 100.00
u_main_meas_ctrl_en 100.00 100.00 100.00 100.00
u_main_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_main_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_main_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_main_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_main_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_measure_ctrl_regwen 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_recov_err_code_io_div2_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_div2_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_div4_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_div4_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_main_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_main_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_shadow_update_err 97.22 100.00 91.67 100.00
u_recov_err_code_usb_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_usb_timeout_err 100.00 100.00 100.00 100.00
u_reg_if 98.98 97.14 98.80 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_usb_meas_ctrl_en 100.00 100.00 100.00 100.00
u_usb_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_usb_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_usb_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_usb_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_usb_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_usb_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_usb_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_usb_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : clkmgr_reg_top
Line No.TotalCoveredPercent
TOTAL244244100.00
ALWAYS8544100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
ALWAYS28044100.00
CONT_ASSIGN31011100.00
ALWAYS32333100.00
CONT_ASSIGN35211100.00
ALWAYS36644100.00
CONT_ASSIGN39611100.00
ALWAYS40933100.00
CONT_ASSIGN43811100.00
ALWAYS45244100.00
CONT_ASSIGN48211100.00
ALWAYS49533100.00
CONT_ASSIGN52411100.00
ALWAYS53844100.00
CONT_ASSIGN56811100.00
ALWAYS58133100.00
CONT_ASSIGN61011100.00
ALWAYS62444100.00
CONT_ASSIGN65411100.00
ALWAYS66733100.00
CONT_ASSIGN69611100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN71811100.00
CONT_ASSIGN73411100.00
CONT_ASSIGN76811100.00
CONT_ASSIGN125611100.00
CONT_ASSIGN125911100.00
CONT_ASSIGN129011100.00
CONT_ASSIGN141311100.00
CONT_ASSIGN141611100.00
CONT_ASSIGN144811100.00
CONT_ASSIGN157111100.00
CONT_ASSIGN157411100.00
CONT_ASSIGN160611100.00
CONT_ASSIGN172911100.00
CONT_ASSIGN173211100.00
CONT_ASSIGN176411100.00
CONT_ASSIGN188711100.00
CONT_ASSIGN189011100.00
CONT_ASSIGN192111100.00
ALWAYS24272323100.00
CONT_ASSIGN245211100.00
ALWAYS245611100.00
CONT_ASSIGN248211100.00
CONT_ASSIGN248411100.00
CONT_ASSIGN248611100.00
CONT_ASSIGN248711100.00
CONT_ASSIGN248911100.00
CONT_ASSIGN249011100.00
CONT_ASSIGN249211100.00
CONT_ASSIGN249411100.00
CONT_ASSIGN249511100.00
CONT_ASSIGN249611100.00
CONT_ASSIGN249811100.00
CONT_ASSIGN249911100.00
CONT_ASSIGN250111100.00
CONT_ASSIGN250211100.00
CONT_ASSIGN250411100.00
CONT_ASSIGN250611100.00
CONT_ASSIGN250811100.00
CONT_ASSIGN251011100.00
CONT_ASSIGN251111100.00
CONT_ASSIGN251311100.00
CONT_ASSIGN251511100.00
CONT_ASSIGN251711100.00
CONT_ASSIGN251911100.00
CONT_ASSIGN252011100.00
CONT_ASSIGN252211100.00
CONT_ASSIGN252311100.00
CONT_ASSIGN252511100.00
CONT_ASSIGN252611100.00
CONT_ASSIGN252911100.00
CONT_ASSIGN253111100.00
CONT_ASSIGN253211100.00
CONT_ASSIGN253511100.00
CONT_ASSIGN253711100.00
CONT_ASSIGN253811100.00
CONT_ASSIGN254111100.00
CONT_ASSIGN254311100.00
CONT_ASSIGN254411100.00
CONT_ASSIGN254711100.00
CONT_ASSIGN254911100.00
CONT_ASSIGN255011100.00
CONT_ASSIGN255311100.00
CONT_ASSIGN255511100.00
CONT_ASSIGN255711100.00
CONT_ASSIGN255911100.00
CONT_ASSIGN256111100.00
CONT_ASSIGN256311100.00
CONT_ASSIGN256511100.00
CONT_ASSIGN256711100.00
CONT_ASSIGN256911100.00
CONT_ASSIGN257111100.00
CONT_ASSIGN257311100.00
CONT_ASSIGN257511100.00
ALWAYS25792323100.00
ALWAYS26064747100.00
ALWAYS272033100.00
ALWAYS272833100.00
CONT_ASSIGN273611100.00
CONT_ASSIGN273911100.00
CONT_ASSIGN275111100.00
CONT_ASSIGN276611100.00
ALWAYS27681212100.00
CONT_ASSIGN281311100.00
CONT_ASSIGN281411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv' or '../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 1 1
86 1 1
87 1 1
88 1 1
MISSING_ELSE
94 1 1
106 1 1
107 1 1
135 1 1
136 1 1
280 1 1
281 1 1
282 1 1
283 1 1
310 1 1
323 1 1
324 1 1
325 1 1
352 1 1
366 1 1
367 1 1
368 1 1
369 1 1
396 1 1
409 1 1
410 1 1
411 1 1
438 1 1
452 1 1
453 1 1
454 1 1
455 1 1
482 1 1
495 1 1
496 1 1
497 1 1
524 1 1
538 1 1
539 1 1
540 1 1
541 1 1
568 1 1
581 1 1
582 1 1
583 1 1
610 1 1
624 1 1
625 1 1
626 1 1
627 1 1
654 1 1
667 1 1
668 1 1
669 1 1
696 1 1
703 1 1
718 1 1
734 1 1
768 1 1
1256 1 1
1259 1 1
1290 1 1
1413 1 1
1416 1 1
1448 1 1
1571 1 1
1574 1 1
1606 1 1
1729 1 1
1732 1 1
1764 1 1
1887 1 1
1890 1 1
1921 1 1
2427 1 1
2428 1 1
2429 1 1
2430 1 1
2431 1 1
2432 1 1
2433 1 1
2434 1 1
2435 1 1
2436 1 1
2437 1 1
2438 1 1
2439 1 1
2440 1 1
2441 1 1
2442 1 1
2443 1 1
2444 1 1
2445 1 1
2446 1 1
2447 1 1
2448 1 1
2449 1 1
2452 1 1
2456 1 1
2482 1 1
2484 1 1
2486 1 1
2487 1 1
2489 1 1
2490 1 1
2492 1 1
2494 1 1
2495 1 1
2496 1 1
2498 1 1
2499 1 1
2501 1 1
2502 1 1
2504 1 1
2506 1 1
2508 1 1
2510 1 1
2511 1 1
2513 1 1
2515 1 1
2517 1 1
2519 1 1
2520 1 1
2522 1 1
2523 1 1
2525 1 1
2526 1 1
2529 1 1
2531 1 1
2532 1 1
2535 1 1
2537 1 1
2538 1 1
2541 1 1
2543 1 1
2544 1 1
2547 1 1
2549 1 1
2550 1 1
2553 1 1
2555 1 1
2557 1 1
2559 1 1
2561 1 1
2563 1 1
2565 1 1
2567 1 1
2569 1 1
2571 1 1
2573 1 1
2575 1 1
2579 1 1
2580 1 1
2581 1 1
2582 1 1
2583 1 1
2584 1 1
2585 1 1
2586 1 1
2587 1 1
2588 1 1
2589 1 1
2590 1 1
2591 1 1
2592 1 1
2593 1 1
2594 1 1
2595 1 1
2596 1 1
2597 1 1
2598 1 1
2599 1 1
2600 1 1
2601 1 1
2606 1 1
2607 1 1
2609 1 1
2610 1 1
2614 1 1
2618 1 1
2619 1 1
2623 1 1
2627 1 1
2631 1 1
2635 1 1
2636 1 1
2637 1 1
2638 1 1
2642 1 1
2643 1 1
2644 1 1
2645 1 1
2649 1 1
2650 1 1
2651 1 1
2652 1 1
2656 1 1
2660 1 1
2663 1 1
2666 1 1
2669 1 1
2672 1 1
2675 1 1
2678 1 1
2681 1 1
2684 1 1
2687 1 1
2690 1 1
2691 1 1
2692 1 1
2693 1 1
2694 1 1
2695 1 1
2696 1 1
2697 1 1
2698 1 1
2699 1 1
2700 1 1
2704 1 1
2705 1 1
2706 1 1
2720 1 1
2721 1 1
2723 1 1
2728 1 1
2729 1 1
2731 1 1
2736 1 1
2739 1 1
2751 1 1
2766 1 1
2768 1 1
2769 1 1
2771 1 1
2774 1 1
2777 1 1
2780 1 1
2783 1 1
2786 1 1
2789 1 1
2792 1 1
2795 1 1
2798 1 1
2813 1 1
2814 1 1


Cond Coverage for Module : clkmgr_reg_top
TotalCoveredPercent
Conditions29629198.31
Logical29629198.31
Non-Logical00
Event00

 LINE       75
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT34,T48,T69
11CoveredT6,T7,T8

 LINE       87
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT54,T66,T67
10CoveredT34,T69,T78

 LINE       94
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT6,T7,T8
001CoveredT54,T66,T67
010CoveredT34,T69,T78
100CoveredT34,T69,T78

 LINE       136
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT6,T7,T8
001CoveredT34,T69,T78
010CoveredT48,T70,T77
100CoveredT48,T70,T77

 LINE       136
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---
-1--2-StatusTests
01Unreachable
10CoveredT6,T7,T8
11CoveredT34,T48,T69

 LINE       768
 EXPRESSION (extclk_ctrl_we & extclk_ctrl_regwen_qs)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T5,T28
11CoveredT6,T8,T1

 LINE       1259
 EXPRESSION (io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen)
             ----------1----------   ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T28
11CoveredT1,T4,T5

 LINE       1290
 EXPRESSION (io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen)
             -------------1-------------   ---------------2---------------
-1--2-StatusTests
01CoveredT30,T33,T34
10CoveredT31,T32,T33
11CoveredT30,T33,T34

 LINE       1416
 EXPRESSION (io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T28
11CoveredT1,T4,T5

 LINE       1448
 EXPRESSION (io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT33,T34,T49
11CoveredT30,T31,T32

 LINE       1574
 EXPRESSION (io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T28
11CoveredT1,T4,T5

 LINE       1606
 EXPRESSION (io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT34,T49,T73
11CoveredT31,T32,T34

 LINE       1732
 EXPRESSION (main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen)
             ------------1------------   --------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T28
11CoveredT1,T4,T5

 LINE       1764
 EXPRESSION (main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01CoveredT30,T31,T33
10CoveredT32,T33,T34
11CoveredT30,T31,T33

 LINE       1890
 EXPRESSION (usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen)
             -----------1-----------   -------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T28
11CoveredT1,T4,T5

 LINE       1921
 EXPRESSION (usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen)
             --------------1--------------   ----------------2----------------
-1--2-StatusTests
01CoveredT30,T31,T33
10CoveredT32,T33,T34
11CoveredT30,T31,T33

 LINE       2428
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2429
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T8,T30

 LINE       2430
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T8,T30

 LINE       2431
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_STATUS_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2432
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_REGWEN_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2433
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_ENABLE_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT30,T31,T32

 LINE       2434
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_ENABLES_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT7,T8,T30

 LINE       2435
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T8,T30

 LINE       2436
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_STATUS_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T8,T30

 LINE       2437
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MEASURE_CTRL_REGWEN_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2438
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_EN_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2439
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2440
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2441
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2442
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2443
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2444
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2445
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2446
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_EN_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2447
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT30,T31,T32

 LINE       2448
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_RECOV_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT30,T31,T32

 LINE       2449
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_FATAL_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2452
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       2452
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT6,T7,T8
10CoveredT6,T8,T30

 LINE       2456
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT6,T7,T8
11CoveredT34,T48,T69

 LINE       2456
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT6,T7,T8
22 (addr_hit[21] & ((|(4'...CoveredT30,T31,T32
21 (addr_hit[20] & ((|(4'...CoveredT30,T31,T32
20 (addr_hit[19] & ((|(4'...CoveredT30,T31,T32
19 (addr_hit[18] & ((|(4'...CoveredT8,T30,T31
18 (addr_hit[17] & ((|(4'...CoveredT8,T30,T31
17 (addr_hit[16] & ((|(4'...CoveredT8,T30,T31
16 (addr_hit[15] & ((|(4'...CoveredT8,T30,T31
15 (addr_hit[14] & ((|(4'...CoveredT30,T31,T32
14 (addr_hit[13] & ((|(4'...CoveredT8,T30,T31
13 (addr_hit[12] & ((|(4'...CoveredT8,T30,T31
12 (addr_hit[11] & ((|(4'...CoveredT8,T30,T31
11 (addr_hit[10] & ((|(4'...CoveredT8,T30,T31
10 (addr_hit[9] & ((|(4'b...CoveredT8,T30,T31
9 (addr_hit[8] & ((|(4'b...CoveredT6,T30,T31
8 (addr_hit[7] & ((|(4'b...CoveredT8,T30,T31
7 (addr_hit[6] & ((|(4'b...CoveredT8,T30,T31
6 (addr_hit[5] & ((|(4'b...CoveredT30,T31,T32
5 (addr_hit[4] & ((|(4'b...CoveredT8,T30,T31
4 (addr_hit[3] & ((|(4'b...CoveredT8,T30,T31
3 (addr_hit[2] & ((|(4'b...CoveredT6,T8,T30
2 (addr_hit[1] & ((|(4'b...CoveredT8,T30,T31
1 (addr_hit[0] & ((|(4'b...CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT8,T30,T31
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT6,T8,T30
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT6,T8,T30
11CoveredT6,T8,T30

 LINE       2456
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT7,T8,T30
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT6,T30,T31
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT6,T8,T30
11CoveredT6,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT8,T30,T31
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT8,T30,T31
11CoveredT30,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT8,T30,T31
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT8,T30,T31
11CoveredT30,T31,T32

 LINE       2482
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T70,T77
111CoveredT31,T32,T34

 LINE       2487
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT6,T8,T30
110CoveredT34,T48,T77
111CoveredT6,T8,T31

 LINE       2490
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT6,T8,T30
110CoveredT48,T77,T78
111CoveredT6,T8,T1

 LINE       2495
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT8,T30,T31
110CoveredT99,T100,T101
111CoveredT30,T31,T32

 LINE       2496
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT70,T81,T82
111CoveredT31,T32,T33

 LINE       2499
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT30,T31,T32
110CoveredT48,T77,T79
111CoveredT31,T32,T33

 LINE       2502
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT7,T8,T30
110CoveredT34,T48,T70
111CoveredT7,T31,T32

 LINE       2511
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT6,T8,T30
110CoveredT48,T77,T79
111CoveredT6,T31,T32

 LINE       2520
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT34,T48,T77
111CoveredT31,T32,T33

 LINE       2523
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT34,T48,T70
111CoveredT1,T4,T5

 LINE       2525
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT8,T30,T31
110CoveredT102,T103,T104
111CoveredT30,T31,T32

 LINE       2526
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT34,T48,T70
111CoveredT30,T31,T32

 LINE       2529
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T77,T79
111CoveredT1,T4,T5

 LINE       2531
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT8,T30,T31
110CoveredT105
111CoveredT30,T31,T32

 LINE       2532
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T69,T70
111CoveredT30,T31,T32

 LINE       2535
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T77,T79
111CoveredT1,T4,T5

 LINE       2537
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT8,T30,T31
110CoveredT69,T78,T106
111CoveredT30,T31,T32

 LINE       2538
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T70,T79
111CoveredT31,T32,T34

 LINE       2541
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T77,T79
111CoveredT1,T4,T5

 LINE       2543
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT8,T30,T31
110CoveredT103,T107,T101
111CoveredT30,T31,T32

 LINE       2544
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T70,T77
111CoveredT30,T31,T32

 LINE       2547
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T77,T79
111CoveredT1,T4,T5

 LINE       2549
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT30,T31,T32
110CoveredT108,T104,T109
111CoveredT30,T31,T32

 LINE       2550
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT30,T31,T32
110CoveredT48,T79,T80
111CoveredT30,T31,T32

 LINE       2553
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT30,T31,T32
110CoveredT48,T69,T79
111CoveredT31,T32,T34

 LINE       2736
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------
-1--2-StatusTests
01CoveredT30,T33,T36
10CoveredT30,T33,T36
11CoveredT6,T7,T8

 LINE       2766
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT8,T30,T31
10CoveredT30,T31,T32

Branch Coverage for Module : clkmgr_reg_top
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 2452 2 2 100.00
IF 85 3 3 100.00
CASE 2607 23 23 100.00
IF 2720 2 2 100.00
IF 2728 2 2 100.00
CASE 2769 11 11 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv' or '../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 2452 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 85 if ((!rst_ni)) -2-: 87 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T6,T7,T8
0 1 Covered T34,T69,T78
0 0 Covered T6,T7,T8


LineNo. Expression -1-: 2607 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T6,T7,T8
addr_hit[1] Covered T6,T7,T8
addr_hit[2] Covered T6,T7,T8
addr_hit[3] Covered T6,T7,T8
addr_hit[4] Covered T6,T7,T8
addr_hit[5] Covered T6,T7,T30
addr_hit[6] Covered T6,T7,T8
addr_hit[7] Covered T6,T7,T8
addr_hit[8] Covered T6,T7,T8
addr_hit[9] Covered T6,T7,T8
addr_hit[10] Covered T6,T7,T8
addr_hit[11] Covered T6,T7,T8
addr_hit[12] Covered T6,T7,T8
addr_hit[13] Covered T6,T7,T8
addr_hit[14] Covered T6,T7,T8
addr_hit[15] Covered T6,T7,T8
addr_hit[16] Covered T6,T7,T8
addr_hit[17] Covered T6,T7,T8
addr_hit[18] Covered T6,T7,T8
addr_hit[19] Covered T6,T7,T30
addr_hit[20] Covered T6,T7,T30
addr_hit[21] Covered T6,T7,T8
default Covered T6,T7,T8


LineNo. Expression -1-: 2720 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 2728 if ((!rst_shadowed_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 2769 case (1'b1)

Branches:
-1-StatusTests
addr_hit[10] Covered T6,T7,T8
addr_hit[11] Covered T6,T7,T8
addr_hit[12] Covered T6,T7,T8
addr_hit[13] Covered T6,T7,T8
addr_hit[14] Covered T6,T7,T8
addr_hit[15] Covered T6,T7,T8
addr_hit[16] Covered T6,T7,T8
addr_hit[17] Covered T6,T7,T8
addr_hit[18] Covered T6,T7,T8
addr_hit[19] Covered T6,T7,T30
default Covered T6,T7,T8


Assert Coverage for Module : clkmgr_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 145816970 741777 0 0
reAfterRv 145816970 741773 0 0
rePulse 145816970 177456 0 0
wePulse 145816970 564317 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 145816970 741777 0 0
T6 5223 145 0 0
T7 1059 35 0 0
T8 2282 61 0 0
T30 9626 533 0 0
T31 13173 2224 0 0
T32 21788 2224 0 0
T33 5607 574 0 0
T34 5273 982 0 0
T35 1337 43 0 0
T36 5718 291 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 145816970 741773 0 0
T6 5223 145 0 0
T7 1059 35 0 0
T8 2282 61 0 0
T30 9626 533 0 0
T31 13173 2224 0 0
T32 21788 2224 0 0
T33 5607 574 0 0
T34 5273 982 0 0
T35 1337 43 0 0
T36 5718 291 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 145816970 177456 0 0
T6 5223 78 0 0
T7 1059 0 0 0
T8 2282 20 0 0
T30 9626 458 0 0
T31 13173 952 0 0
T32 21788 952 0 0
T33 5607 383 0 0
T34 5273 555 0 0
T35 1337 22 0 0
T36 5718 252 0 0
T49 0 214 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 145816970 564317 0 0
T6 5223 67 0 0
T7 1059 35 0 0
T8 2282 41 0 0
T30 9626 75 0 0
T31 13173 1272 0 0
T32 21788 1272 0 0
T33 5607 191 0 0
T34 5273 427 0 0
T35 1337 21 0 0
T36 5718 39 0 0

Line Coverage for Instance : tb.dut.u_reg
Line No.TotalCoveredPercent
TOTAL244244100.00
ALWAYS8544100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
ALWAYS28044100.00
CONT_ASSIGN31011100.00
ALWAYS32333100.00
CONT_ASSIGN35211100.00
ALWAYS36644100.00
CONT_ASSIGN39611100.00
ALWAYS40933100.00
CONT_ASSIGN43811100.00
ALWAYS45244100.00
CONT_ASSIGN48211100.00
ALWAYS49533100.00
CONT_ASSIGN52411100.00
ALWAYS53844100.00
CONT_ASSIGN56811100.00
ALWAYS58133100.00
CONT_ASSIGN61011100.00
ALWAYS62444100.00
CONT_ASSIGN65411100.00
ALWAYS66733100.00
CONT_ASSIGN69611100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN71811100.00
CONT_ASSIGN73411100.00
CONT_ASSIGN76811100.00
CONT_ASSIGN125611100.00
CONT_ASSIGN125911100.00
CONT_ASSIGN129011100.00
CONT_ASSIGN141311100.00
CONT_ASSIGN141611100.00
CONT_ASSIGN144811100.00
CONT_ASSIGN157111100.00
CONT_ASSIGN157411100.00
CONT_ASSIGN160611100.00
CONT_ASSIGN172911100.00
CONT_ASSIGN173211100.00
CONT_ASSIGN176411100.00
CONT_ASSIGN188711100.00
CONT_ASSIGN189011100.00
CONT_ASSIGN192111100.00
ALWAYS24272323100.00
CONT_ASSIGN245211100.00
ALWAYS245611100.00
CONT_ASSIGN248211100.00
CONT_ASSIGN248411100.00
CONT_ASSIGN248611100.00
CONT_ASSIGN248711100.00
CONT_ASSIGN248911100.00
CONT_ASSIGN249011100.00
CONT_ASSIGN249211100.00
CONT_ASSIGN249411100.00
CONT_ASSIGN249511100.00
CONT_ASSIGN249611100.00
CONT_ASSIGN249811100.00
CONT_ASSIGN249911100.00
CONT_ASSIGN250111100.00
CONT_ASSIGN250211100.00
CONT_ASSIGN250411100.00
CONT_ASSIGN250611100.00
CONT_ASSIGN250811100.00
CONT_ASSIGN251011100.00
CONT_ASSIGN251111100.00
CONT_ASSIGN251311100.00
CONT_ASSIGN251511100.00
CONT_ASSIGN251711100.00
CONT_ASSIGN251911100.00
CONT_ASSIGN252011100.00
CONT_ASSIGN252211100.00
CONT_ASSIGN252311100.00
CONT_ASSIGN252511100.00
CONT_ASSIGN252611100.00
CONT_ASSIGN252911100.00
CONT_ASSIGN253111100.00
CONT_ASSIGN253211100.00
CONT_ASSIGN253511100.00
CONT_ASSIGN253711100.00
CONT_ASSIGN253811100.00
CONT_ASSIGN254111100.00
CONT_ASSIGN254311100.00
CONT_ASSIGN254411100.00
CONT_ASSIGN254711100.00
CONT_ASSIGN254911100.00
CONT_ASSIGN255011100.00
CONT_ASSIGN255311100.00
CONT_ASSIGN255511100.00
CONT_ASSIGN255711100.00
CONT_ASSIGN255911100.00
CONT_ASSIGN256111100.00
CONT_ASSIGN256311100.00
CONT_ASSIGN256511100.00
CONT_ASSIGN256711100.00
CONT_ASSIGN256911100.00
CONT_ASSIGN257111100.00
CONT_ASSIGN257311100.00
CONT_ASSIGN257511100.00
ALWAYS25792323100.00
ALWAYS26064747100.00
ALWAYS272033100.00
ALWAYS272833100.00
CONT_ASSIGN273611100.00
CONT_ASSIGN273911100.00
CONT_ASSIGN275111100.00
CONT_ASSIGN276611100.00
ALWAYS27681212100.00
CONT_ASSIGN281311100.00
CONT_ASSIGN281411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv' or '../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 1 1
86 1 1
87 1 1
88 1 1
MISSING_ELSE
94 1 1
106 1 1
107 1 1
135 1 1
136 1 1
280 1 1
281 1 1
282 1 1
283 1 1
310 1 1
323 1 1
324 1 1
325 1 1
352 1 1
366 1 1
367 1 1
368 1 1
369 1 1
396 1 1
409 1 1
410 1 1
411 1 1
438 1 1
452 1 1
453 1 1
454 1 1
455 1 1
482 1 1
495 1 1
496 1 1
497 1 1
524 1 1
538 1 1
539 1 1
540 1 1
541 1 1
568 1 1
581 1 1
582 1 1
583 1 1
610 1 1
624 1 1
625 1 1
626 1 1
627 1 1
654 1 1
667 1 1
668 1 1
669 1 1
696 1 1
703 1 1
718 1 1
734 1 1
768 1 1
1256 1 1
1259 1 1
1290 1 1
1413 1 1
1416 1 1
1448 1 1
1571 1 1
1574 1 1
1606 1 1
1729 1 1
1732 1 1
1764 1 1
1887 1 1
1890 1 1
1921 1 1
2427 1 1
2428 1 1
2429 1 1
2430 1 1
2431 1 1
2432 1 1
2433 1 1
2434 1 1
2435 1 1
2436 1 1
2437 1 1
2438 1 1
2439 1 1
2440 1 1
2441 1 1
2442 1 1
2443 1 1
2444 1 1
2445 1 1
2446 1 1
2447 1 1
2448 1 1
2449 1 1
2452 1 1
2456 1 1
2482 1 1
2484 1 1
2486 1 1
2487 1 1
2489 1 1
2490 1 1
2492 1 1
2494 1 1
2495 1 1
2496 1 1
2498 1 1
2499 1 1
2501 1 1
2502 1 1
2504 1 1
2506 1 1
2508 1 1
2510 1 1
2511 1 1
2513 1 1
2515 1 1
2517 1 1
2519 1 1
2520 1 1
2522 1 1
2523 1 1
2525 1 1
2526 1 1
2529 1 1
2531 1 1
2532 1 1
2535 1 1
2537 1 1
2538 1 1
2541 1 1
2543 1 1
2544 1 1
2547 1 1
2549 1 1
2550 1 1
2553 1 1
2555 1 1
2557 1 1
2559 1 1
2561 1 1
2563 1 1
2565 1 1
2567 1 1
2569 1 1
2571 1 1
2573 1 1
2575 1 1
2579 1 1
2580 1 1
2581 1 1
2582 1 1
2583 1 1
2584 1 1
2585 1 1
2586 1 1
2587 1 1
2588 1 1
2589 1 1
2590 1 1
2591 1 1
2592 1 1
2593 1 1
2594 1 1
2595 1 1
2596 1 1
2597 1 1
2598 1 1
2599 1 1
2600 1 1
2601 1 1
2606 1 1
2607 1 1
2609 1 1
2610 1 1
2614 1 1
2618 1 1
2619 1 1
2623 1 1
2627 1 1
2631 1 1
2635 1 1
2636 1 1
2637 1 1
2638 1 1
2642 1 1
2643 1 1
2644 1 1
2645 1 1
2649 1 1
2650 1 1
2651 1 1
2652 1 1
2656 1 1
2660 1 1
2663 1 1
2666 1 1
2669 1 1
2672 1 1
2675 1 1
2678 1 1
2681 1 1
2684 1 1
2687 1 1
2690 1 1
2691 1 1
2692 1 1
2693 1 1
2694 1 1
2695 1 1
2696 1 1
2697 1 1
2698 1 1
2699 1 1
2700 1 1
2704 1 1
2705 1 1
2706 1 1
2720 1 1
2721 1 1
2723 1 1
2728 1 1
2729 1 1
2731 1 1
2736 1 1
2739 1 1
2751 1 1
2766 1 1
2768 1 1
2769 1 1
2771 1 1
2774 1 1
2777 1 1
2780 1 1
2783 1 1
2786 1 1
2789 1 1
2792 1 1
2795 1 1
2798 1 1
2813 1 1
2814 1 1


Cond Coverage for Instance : tb.dut.u_reg
TotalCoveredPercent
Conditions291291100.00
Logical291291100.00
Non-Logical00
Event00

 LINE       75
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT34,T48,T69
11CoveredT6,T7,T8

 LINE       87
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT54,T66,T67
10CoveredT34,T69,T78

 LINE       94
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT6,T7,T8
001CoveredT54,T66,T67
010CoveredT34,T69,T78
100CoveredT34,T69,T78

 LINE       136
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT6,T7,T8
001CoveredT34,T69,T78
010CoveredT48,T70,T77
100CoveredT48,T70,T77

 LINE       136
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---
-1--2-StatusTests
01Unreachable
10CoveredT6,T7,T8
11CoveredT34,T48,T69

 LINE       768
 EXPRESSION (extclk_ctrl_we & extclk_ctrl_regwen_qs)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T5,T28
11CoveredT6,T8,T1

 LINE       1259
 EXPRESSION (io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen)
             ----------1----------   ------------2------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T5,T28
11CoveredT1,T4,T5

 LINE       1290
 EXPRESSION (io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen)
             -------------1-------------   ---------------2---------------
-1--2-StatusTests
01CoveredT30,T33,T34
10CoveredT31,T32,T33
11CoveredT30,T33,T34

 LINE       1416
 EXPRESSION (io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T5,T28
11CoveredT1,T4,T5

 LINE       1448
 EXPRESSION (io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT33,T34,T49
11CoveredT30,T31,T32

 LINE       1574
 EXPRESSION (io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T5,T28
11CoveredT1,T4,T5

 LINE       1606
 EXPRESSION (io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT34,T49,T73
11CoveredT31,T32,T34

 LINE       1732
 EXPRESSION (main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen)
             ------------1------------   --------------2--------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T5,T28
11CoveredT1,T4,T5

 LINE       1764
 EXPRESSION (main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01CoveredT30,T31,T33
10CoveredT32,T33,T34
11CoveredT30,T31,T33

 LINE       1890
 EXPRESSION (usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen)
             -----------1-----------   -------------2-------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T5,T28
11CoveredT1,T4,T5

 LINE       1921
 EXPRESSION (usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen)
             --------------1--------------   ----------------2----------------
-1--2-StatusTests
01CoveredT30,T31,T33
10CoveredT32,T33,T34
11CoveredT30,T31,T33

 LINE       2428
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2429
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T8,T30

 LINE       2430
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T8,T30

 LINE       2431
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_STATUS_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2432
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_REGWEN_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2433
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_ENABLE_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT30,T31,T32

 LINE       2434
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_ENABLES_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT7,T8,T30

 LINE       2435
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T8,T30

 LINE       2436
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_STATUS_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T8,T30

 LINE       2437
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MEASURE_CTRL_REGWEN_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2438
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_EN_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2439
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2440
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2441
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2442
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2443
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2444
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2445
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2446
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_EN_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2447
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT30,T31,T32

 LINE       2448
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_RECOV_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT30,T31,T32

 LINE       2449
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_FATAL_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T30,T31

 LINE       2452
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       2452
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT6,T7,T8
10CoveredT6,T8,T30

 LINE       2456
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT6,T7,T8
11CoveredT34,T48,T69

 LINE       2456
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT6,T7,T8
22 (addr_hit[21] & ((|(4'...CoveredT30,T31,T32
21 (addr_hit[20] & ((|(4'...CoveredT30,T31,T32
20 (addr_hit[19] & ((|(4'...CoveredT30,T31,T32
19 (addr_hit[18] & ((|(4'...CoveredT8,T30,T31
18 (addr_hit[17] & ((|(4'...CoveredT8,T30,T31
17 (addr_hit[16] & ((|(4'...CoveredT8,T30,T31
16 (addr_hit[15] & ((|(4'...CoveredT8,T30,T31
15 (addr_hit[14] & ((|(4'...CoveredT30,T31,T32
14 (addr_hit[13] & ((|(4'...CoveredT8,T30,T31
13 (addr_hit[12] & ((|(4'...CoveredT8,T30,T31
12 (addr_hit[11] & ((|(4'...CoveredT8,T30,T31
11 (addr_hit[10] & ((|(4'...CoveredT8,T30,T31
10 (addr_hit[9] & ((|(4'b...CoveredT8,T30,T31
9 (addr_hit[8] & ((|(4'b...CoveredT6,T30,T31
8 (addr_hit[7] & ((|(4'b...CoveredT8,T30,T31
7 (addr_hit[6] & ((|(4'b...CoveredT8,T30,T31
6 (addr_hit[5] & ((|(4'b...CoveredT30,T31,T32
5 (addr_hit[4] & ((|(4'b...CoveredT8,T30,T31
4 (addr_hit[3] & ((|(4'b...CoveredT8,T30,T31
3 (addr_hit[2] & ((|(4'b...CoveredT6,T8,T30
2 (addr_hit[1] & ((|(4'b...CoveredT8,T30,T31
1 (addr_hit[0] & ((|(4'b...CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT8,T30,T31
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT6,T8,T30
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT6,T8,T30
11CoveredT6,T8,T30

 LINE       2456
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT7,T8,T30
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT6,T30,T31
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT6,T8,T30
11CoveredT6,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT8,T30,T31
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT8,T30,T31
11CoveredT30,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT8,T30,T31
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT30,T31,T32
11CoveredT8,T30,T31

 LINE       2456
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       2456
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T8,T30
10CoveredT8,T30,T31
11CoveredT30,T31,T32

 LINE       2482
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T70,T77
111CoveredT31,T32,T34

 LINE       2487
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT6,T8,T30
110CoveredT34,T48,T77
111CoveredT6,T8,T31

 LINE       2490
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT6,T8,T30
110CoveredT48,T77,T78
111CoveredT6,T8,T1

 LINE       2495
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT8,T30,T31
110CoveredT99,T100,T101
111CoveredT30,T31,T32

 LINE       2496
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT70,T81,T82
111CoveredT31,T32,T33

 LINE       2499
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT30,T31,T32
110CoveredT48,T77,T79
111CoveredT31,T32,T33

 LINE       2502
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT7,T8,T30
110CoveredT34,T48,T70
111CoveredT7,T31,T32

 LINE       2511
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT6,T8,T30
110CoveredT48,T77,T79
111CoveredT6,T31,T32

 LINE       2520
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT34,T48,T77
111CoveredT31,T32,T33

 LINE       2523
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT34,T48,T70
111CoveredT1,T4,T5

 LINE       2525
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT8,T30,T31
110CoveredT102,T103,T104
111CoveredT30,T31,T32

 LINE       2526
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT34,T48,T70
111CoveredT30,T31,T32

 LINE       2529
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T77,T79
111CoveredT1,T4,T5

 LINE       2531
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT8,T30,T31
110CoveredT105
111CoveredT30,T31,T32

 LINE       2532
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T69,T70
111CoveredT30,T31,T32

 LINE       2535
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T77,T79
111CoveredT1,T4,T5

 LINE       2537
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT8,T30,T31
110CoveredT69,T78,T106
111CoveredT30,T31,T32

 LINE       2538
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T70,T79
111CoveredT31,T32,T34

 LINE       2541
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T77,T79
111CoveredT1,T4,T5

 LINE       2543
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT8,T30,T31
110CoveredT103,T107,T101
111CoveredT30,T31,T32

 LINE       2544
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T70,T77
111CoveredT30,T31,T32

 LINE       2547
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T30,T31
110CoveredT48,T77,T79
111CoveredT1,T4,T5

 LINE       2549
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T8,T30
101CoveredT30,T31,T32
110CoveredT108,T104,T109
111CoveredT30,T31,T32

 LINE       2550
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT30,T31,T32
110CoveredT48,T79,T80
111CoveredT30,T31,T32

 LINE       2553
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT30,T31,T32
110CoveredT48,T69,T79
111CoveredT31,T32,T34

 LINE       2736
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------
-1--2-StatusTests
01CoveredT30,T33,T36
10CoveredT30,T33,T36
11CoveredT6,T7,T8

 LINE       2766
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT8,T30,T31
10CoveredT30,T31,T32

Branch Coverage for Instance : tb.dut.u_reg
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 2452 2 2 100.00
IF 85 3 3 100.00
CASE 2607 23 23 100.00
IF 2720 2 2 100.00
IF 2728 2 2 100.00
CASE 2769 11 11 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv' or '../src/lowrisc_systems_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 2452 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 85 if ((!rst_ni)) -2-: 87 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T6,T7,T8
0 1 Covered T34,T69,T78
0 0 Covered T6,T7,T8


LineNo. Expression -1-: 2607 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T6,T7,T8
addr_hit[1] Covered T6,T7,T8
addr_hit[2] Covered T6,T7,T8
addr_hit[3] Covered T6,T7,T8
addr_hit[4] Covered T6,T7,T8
addr_hit[5] Covered T6,T7,T30
addr_hit[6] Covered T6,T7,T8
addr_hit[7] Covered T6,T7,T8
addr_hit[8] Covered T6,T7,T8
addr_hit[9] Covered T6,T7,T8
addr_hit[10] Covered T6,T7,T8
addr_hit[11] Covered T6,T7,T8
addr_hit[12] Covered T6,T7,T8
addr_hit[13] Covered T6,T7,T8
addr_hit[14] Covered T6,T7,T8
addr_hit[15] Covered T6,T7,T8
addr_hit[16] Covered T6,T7,T8
addr_hit[17] Covered T6,T7,T8
addr_hit[18] Covered T6,T7,T8
addr_hit[19] Covered T6,T7,T30
addr_hit[20] Covered T6,T7,T30
addr_hit[21] Covered T6,T7,T8
default Covered T6,T7,T8


LineNo. Expression -1-: 2720 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 2728 if ((!rst_shadowed_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 2769 case (1'b1)

Branches:
-1-StatusTests
addr_hit[10] Covered T6,T7,T8
addr_hit[11] Covered T6,T7,T8
addr_hit[12] Covered T6,T7,T8
addr_hit[13] Covered T6,T7,T8
addr_hit[14] Covered T6,T7,T8
addr_hit[15] Covered T6,T7,T8
addr_hit[16] Covered T6,T7,T8
addr_hit[17] Covered T6,T7,T8
addr_hit[18] Covered T6,T7,T8
addr_hit[19] Covered T6,T7,T30
default Covered T6,T7,T8


Assert Coverage for Instance : tb.dut.u_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 145816970 741777 0 0
reAfterRv 145816970 741773 0 0
rePulse 145816970 177456 0 0
wePulse 145816970 564317 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 145816970 741777 0 0
T6 5223 145 0 0
T7 1059 35 0 0
T8 2282 61 0 0
T30 9626 533 0 0
T31 13173 2224 0 0
T32 21788 2224 0 0
T33 5607 574 0 0
T34 5273 982 0 0
T35 1337 43 0 0
T36 5718 291 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 145816970 741773 0 0
T6 5223 145 0 0
T7 1059 35 0 0
T8 2282 61 0 0
T30 9626 533 0 0
T31 13173 2224 0 0
T32 21788 2224 0 0
T33 5607 574 0 0
T34 5273 982 0 0
T35 1337 43 0 0
T36 5718 291 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 145816970 177456 0 0
T6 5223 78 0 0
T7 1059 0 0 0
T8 2282 20 0 0
T30 9626 458 0 0
T31 13173 952 0 0
T32 21788 952 0 0
T33 5607 383 0 0
T34 5273 555 0 0
T35 1337 22 0 0
T36 5718 252 0 0
T49 0 214 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 145816970 564317 0 0
T6 5223 67 0 0
T7 1059 35 0 0
T8 2282 41 0 0
T30 9626 75 0 0
T31 13173 1272 0 0
T32 21788 1272 0 0
T33 5607 191 0 0
T34 5273 427 0 0
T35 1337 21 0 0
T36 5718 39 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%