Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T6,T1,T18

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	144890486	142352016	0	0
AllClkBypReqTrue_A	144890486	130204	0	0
IoClkBypReqFalse_A	144890486	142276926	0	2409
IoClkBypReqTrue_A	144890486	200534	0	0
LcClkBypAckFalse_A	144890486	142364524	0	0
LcClkBypAckTrue_A	144890486	117696	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144890486	142352016	0	0
T1	240054	236817	0	0
T4	23264	4860	0	0
T6	5223	4979	0	0
T7	1059	1029	0	0
T8	2282	1801	0	0
T17	1037	923	0	0
T18	4663	4480	0	0
T19	928	896	0	0
T20	964	929	0	0
T21	1137	1081	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144890486	130204	0	0
T1	240054	967	0	0
T3	0	313	0	0
T4	23264	0	0	0
T6	5223	75	0	0
T7	1059	0	0	0
T8	2282	401	0	0
T10	0	377	0	0
T17	1037	0	0	0
T18	4663	0	0	0
T19	928	0	0	0
T20	964	0	0	0
T21	1137	0	0	0
T22	0	359	0	0
T110	0	77	0	0
T111	0	47	0	0
T112	0	141	0	0
T113	0	257	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144890486	142276926	0	2409
T1	240054	236794	0	3
T4	23264	4834	0	3
T6	5223	4979	0	3
T7	1059	1027	0	3
T8	2282	1806	0	3
T17	1037	921	0	3
T18	4663	4476	0	3
T19	928	894	0	3
T20	964	927	0	3
T21	1137	1079	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144890486	200534	0	0
T1	240054	1169	0	0
T3	0	678	0	0
T4	23264	0	0	0
T6	5223	71	0	0
T7	1059	0	0	0
T8	2282	394	0	0
T10	0	490	0	0
T17	1037	0	0	0
T18	4663	0	0	0
T19	928	0	0	0
T20	964	0	0	0
T21	1137	0	0	0
T22	0	611	0	0
T110	0	31	0	0
T111	0	155	0	0
T112	0	243	0	0
T113	0	369	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144890486	142364524	0	0
T1	240054	236831	0	0
T4	23264	4860	0	0
T6	5223	5022	0	0
T7	1059	1029	0	0
T8	2282	1985	0	0
T17	1037	923	0	0
T18	4663	4480	0	0
T19	928	896	0	0
T20	964	929	0	0
T21	1137	1081	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144890486	117696	0	0
T1	240054	826	0	0
T3	0	364	0	0
T4	23264	0	0	0
T6	5223	32	0	0
T7	1059	0	0	0
T8	2282	217	0	0
T10	0	330	0	0
T17	1037	0	0	0
T18	4663	0	0	0
T19	928	0	0	0
T20	964	0	0	0
T21	1137	0	0	0
T22	0	465	0	0
T111	0	93	0	0
T112	0	169	0	0
T113	0	183	0	0
T114	0	289	0	0