Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1679648668	14680	0	0
TransStop_A	1679648668	7435	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679648668	14680	0	0
T1	988256	188	0	0
T3	0	78	0	0
T4	372232	0	0	0
T6	42636	37	0	0
T7	17672	0	0	0
T8	19436	0	0	0
T17	6188	0	0	0
T18	38060	30	0	0
T19	24780	2	0	0
T20	16080	4	0	0
T21	9280	0	0	0
T115	0	5	0	0
T116	0	4	0	0
T117	0	36	0	0
T118	0	4	0	0
T119	0	13	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679648668	7435	0	0
T1	988256	107	0	0
T3	0	45	0	0
T4	372232	0	0	0
T6	42636	18	0	0
T7	17672	0	0	0
T8	19436	0	0	0
T17	6188	0	0	0
T18	38060	13	0	0
T19	24780	2	0	0
T20	16080	4	0	0
T21	9280	0	0	0
T115	0	2	0	0
T116	0	4	0	0
T117	0	17	0	0
T118	0	4	0	0
T119	0	5	0	0
T120	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	419912167	3693	0	0
TransStop_A	419912167	1872	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419912167	3693	0	0
T1	247064	45	0	0
T3	0	19	0	0
T4	93058	0	0	0
T6	10659	12	0	0
T7	4418	0	0	0
T8	4859	0	0	0
T17	1547	0	0	0
T18	9515	6	0	0
T19	6195	0	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	11	0	0
T118	0	2	0	0
T119	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419912167	1872	0	0
T1	247064	25	0	0
T3	0	11	0	0
T4	93058	0	0	0
T6	10659	6	0	0
T7	4418	0	0	0
T8	4859	0	0	0
T17	1547	0	0	0
T18	9515	2	0	0
T19	6195	0	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T116	0	1	0	0
T117	0	4	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	419912167	3653	0	0
TransStop_A	419912167	1839	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419912167	3653	0	0
T1	247064	50	0	0
T3	0	19	0	0
T4	93058	0	0	0
T6	10659	9	0	0
T7	4418	0	0	0
T8	4859	0	0	0
T17	1547	0	0	0
T18	9515	8	0	0
T19	6195	1	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T115	0	2	0	0
T116	0	1	0	0
T117	0	7	0	0
T119	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419912167	1839	0	0
T1	247064	29	0	0
T3	0	11	0	0
T4	93058	0	0	0
T6	10659	2	0	0
T7	4418	0	0	0
T8	4859	0	0	0
T17	1547	0	0	0
T18	9515	4	0	0
T19	6195	1	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	4	0	0
T119	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	419912167	3627	0	0
TransStop_A	419912167	1838	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419912167	3627	0	0
T1	247064	47	0	0
T3	0	22	0	0
T4	93058	0	0	0
T6	10659	8	0	0
T7	4418	0	0	0
T8	4859	0	0	0
T17	1547	0	0	0
T18	9515	10	0	0
T19	6195	1	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	9	0	0
T118	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419912167	1838	0	0
T1	247064	26	0	0
T3	0	13	0	0
T4	93058	0	0	0
T6	10659	5	0	0
T7	4418	0	0	0
T8	4859	0	0	0
T17	1547	0	0	0
T18	9515	4	0	0
T19	6195	1	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T116	0	1	0	0
T117	0	5	0	0
T118	0	1	0	0
T119	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	419912167	3707	0	0
TransStop_A	419912167	1886	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419912167	3707	0	0
T1	247064	46	0	0
T3	0	18	0	0
T4	93058	0	0	0
T6	10659	8	0	0
T7	4418	0	0	0
T8	4859	0	0	0
T17	1547	0	0	0
T18	9515	6	0	0
T19	6195	0	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	9	0	0
T118	0	1	0	0
T119	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419912167	1886	0	0
T1	247064	27	0	0
T3	0	10	0	0
T4	93058	0	0	0
T6	10659	5	0	0
T7	4418	0	0	0
T8	4859	0	0	0
T17	1547	0	0	0
T18	9515	3	0	0
T19	6195	0	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	4	0	0
T118	0	1	0	0
T119	0	1	0	0