Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : clkmgr_lost_calib_regwen_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if 100.00 100.00



Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
RegwenOff_A 144890486 16773053 0 61


RegwenOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144890486 16773053 0 61
T1 240054 120805 0 0
T2 23579 3951 0 1
T3 0 28905 0 0
T4 23264 0 0 0
T5 17049 0 0 0
T10 0 22112 0 0
T11 0 32217 0 1
T12 0 13586 0 1
T13 0 12299 0 0
T14 0 1454 0 1
T15 0 249945 0 0
T17 1037 0 0 0
T18 4663 0 0 0
T19 928 0 0 0
T20 964 0 0 0
T21 1137 0 0 0
T22 2282 0 0 0
T23 0 1229 0 1
T24 0 0 0 1
T121 0 0 0 1
T122 0 0 0 1
T123 0 0 0 1
T124 0 0 0 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%