Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	145816970	4353540	0	0
clk_enables_rd_A	145816970	60280	0	0
clk_hints_rd_A	145816970	55432	0	0
extclk_ctrl_rd_A	145816970	66540	0	0
extclk_ctrl_regwen_rd_A	145816970	51840	0	0
jitter_enable_rd_A	145816970	74766	0	0
jitter_regwen_rd_A	145816970	59239	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145816970	4353540	0	0
T34	5273	9	0	0
T46	2156	27	0	0
T47	2924	78	0	0
T48	11942	431	0	0
T69	5139	10	0	0
T70	0	523	0	0
T71	5734	0	0	0
T76	8480	0	0	0
T77	0	633	0	0
T78	0	12	0	0
T88	2644	0	0	0
T89	2203	44	0	0
T90	21301	0	0	0
T137	0	52	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145816970	60280	0	0
T32	21788	111	0	0
T35	1337	2	0	0
T47	2924	0	0	0
T48	11942	50	0	0
T49	4870	60	0	0
T51	0	31	0	0
T69	5139	0	0	0
T76	0	47	0	0
T85	0	11	0	0
T89	0	5	0	0
T90	0	141	0	0
T95	2491	2	0	0
T96	1006	0	0	0
T97	1215	0	0	0
T98	1366	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145816970	55432	0	0
T32	21788	189	0	0
T35	1337	4	0	0
T47	2924	0	0	0
T48	11942	14	0	0
T49	4870	64	0	0
T51	0	44	0	0
T69	5139	0	0	0
T76	0	47	0	0
T85	0	21	0	0
T89	0	11	0	0
T90	0	154	0	0
T95	2491	7	0	0
T96	1006	0	0	0
T97	1215	0	0	0
T98	1366	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145816970	66540	0	0
T35	1337	7	0	0
T47	2924	0	0	0
T48	11942	18	0	0
T49	4870	12	0	0
T51	0	6	0	0
T69	5139	0	0	0
T72	0	67	0	0
T76	0	61	0	0
T88	2644	0	0	0
T89	0	7	0	0
T95	2491	7	0	0
T96	1006	0	0	0
T97	1215	0	0	0
T98	1366	0	0	0
T133	0	9	0	0
T137	0	13	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145816970	51840	0	0
T32	21788	177	0	0
T35	1337	5	0	0
T47	2924	0	0	0
T48	11942	1	0	0
T49	4870	35	0	0
T51	0	39	0	0
T69	5139	0	0	0
T76	0	47	0	0
T85	0	11	0	0
T89	0	7	0	0
T90	0	125	0	0
T95	2491	5	0	0
T96	1006	0	0	0
T97	1215	0	0	0
T98	1366	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145816970	74766	0	0
T32	21788	133	0	0
T35	1337	3	0	0
T47	2924	0	0	0
T48	11942	29	0	0
T49	4870	26	0	0
T51	0	14	0	0
T69	5139	0	0	0
T76	0	57	0	0
T85	0	4	0	0
T89	0	17	0	0
T90	0	136	0	0
T95	2491	5	0	0
T96	1006	0	0	0
T97	1215	0	0	0
T98	1366	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145816970	59239	0	0
T32	21788	128	0	0
T35	1337	2	0	0
T48	11942	25	0	0
T49	4870	82	0	0
T51	0	36	0	0
T70	7087	0	0	0
T71	5734	0	0	0
T76	8480	51	0	0
T85	0	7	0	0
T89	2203	8	0	0
T90	21301	125	0	0
T91	6149	0	0	0
T137	0	6	0	0