Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT6,T8,T1
11CoveredT6,T8,T1

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 392840573 4039 0 0
g_div2.Div2Whole_A 392840573 4719 0 0
g_div4.Div4Stepped_A 195591789 3962 0 0
g_div4.Div4Whole_A 195591789 4482 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 392840573 4039 0 0
T1 228534 22 0 0
T3 0 16 0 0
T4 89334 0 0 0
T6 10232 3 0 0
T7 4241 0 0 0
T8 4664 12 0 0
T10 0 15 0 0
T17 1485 0 0 0
T18 9135 0 0 0
T19 5947 0 0 0
T20 3858 0 0 0
T21 2228 0 0 0
T22 0 15 0 0
T110 0 3 0 0
T111 0 3 0 0
T112 0 11 0 0
T113 0 8 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 392840573 4719 0 0
T1 228534 23 0 0
T3 0 18 0 0
T4 89334 0 0 0
T6 10232 3 0 0
T7 4241 0 0 0
T8 4664 12 0 0
T10 0 15 0 0
T17 1485 0 0 0
T18 9135 0 0 0
T19 5947 0 0 0
T20 3858 0 0 0
T21 2228 0 0 0
T22 0 16 0 0
T110 0 3 0 0
T111 0 5 0 0
T112 0 11 0 0
T113 0 10 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195591789 3962 0 0
T1 113540 22 0 0
T3 0 16 0 0
T4 23037 0 0 0
T6 5130 3 0 0
T7 2081 0 0 0
T8 2695 12 0 0
T10 0 15 0 0
T17 731 0 0 0
T18 4515 0 0 0
T19 2920 0 0 0
T20 1911 0 0 0
T21 1081 0 0 0
T22 0 15 0 0
T110 0 3 0 0
T111 0 3 0 0
T112 0 11 0 0
T113 0 8 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195591789 4482 0 0
T1 113540 22 0 0
T3 0 18 0 0
T4 23037 0 0 0
T6 5130 3 0 0
T7 2081 0 0 0
T8 2695 12 0 0
T10 0 15 0 0
T17 731 0 0 0
T18 4515 0 0 0
T19 2920 0 0 0
T20 1911 0 0 0
T21 1081 0 0 0
T22 0 16 0 0
T110 0 3 0 0
T111 0 3 0 0
T112 0 11 0 0
T113 0 10 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT6,T8,T1
11CoveredT6,T8,T1

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 392840573 4039 0 0
g_div2.Div2Whole_A 392840573 4719 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 392840573 4039 0 0
T1 228534 22 0 0
T3 0 16 0 0
T4 89334 0 0 0
T6 10232 3 0 0
T7 4241 0 0 0
T8 4664 12 0 0
T10 0 15 0 0
T17 1485 0 0 0
T18 9135 0 0 0
T19 5947 0 0 0
T20 3858 0 0 0
T21 2228 0 0 0
T22 0 15 0 0
T110 0 3 0 0
T111 0 3 0 0
T112 0 11 0 0
T113 0 8 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 392840573 4719 0 0
T1 228534 23 0 0
T3 0 18 0 0
T4 89334 0 0 0
T6 10232 3 0 0
T7 4241 0 0 0
T8 4664 12 0 0
T10 0 15 0 0
T17 1485 0 0 0
T18 9135 0 0 0
T19 5947 0 0 0
T20 3858 0 0 0
T21 2228 0 0 0
T22 0 16 0 0
T110 0 3 0 0
T111 0 5 0 0
T112 0 11 0 0
T113 0 10 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT6,T8,T1
11CoveredT6,T8,T1

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 195591789 3962 0 0
g_div4.Div4Whole_A 195591789 4482 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195591789 3962 0 0
T1 113540 22 0 0
T3 0 16 0 0
T4 23037 0 0 0
T6 5130 3 0 0
T7 2081 0 0 0
T8 2695 12 0 0
T10 0 15 0 0
T17 731 0 0 0
T18 4515 0 0 0
T19 2920 0 0 0
T20 1911 0 0 0
T21 1081 0 0 0
T22 0 15 0 0
T110 0 3 0 0
T111 0 3 0 0
T112 0 11 0 0
T113 0 8 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195591789 4482 0 0
T1 113540 22 0 0
T3 0 18 0 0
T4 23037 0 0 0
T6 5130 3 0 0
T7 2081 0 0 0
T8 2695 12 0 0
T10 0 15 0 0
T17 731 0 0 0
T18 4515 0 0 0
T19 2920 0 0 0
T20 1911 0 0 0
T21 1081 0 0 0
T22 0 16 0 0
T110 0 3 0 0
T111 0 3 0 0
T112 0 11 0 0
T113 0 10 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%