Assert Coverage for Module :
clkmgr_pwrmgr_sva_if
Assertion Details
IoStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
144890486 |
142 |
0 |
0 |
T3 |
133182 |
0 |
0 |
0 |
T27 |
42175 |
0 |
0 |
0 |
T28 |
27111 |
0 |
0 |
0 |
T37 |
858 |
0 |
0 |
0 |
T43 |
1594 |
5 |
0 |
0 |
T44 |
1165 |
2 |
0 |
0 |
T45 |
0 |
3 |
0 |
0 |
T111 |
1680 |
0 |
0 |
0 |
T112 |
1483 |
0 |
0 |
0 |
T115 |
1391 |
0 |
0 |
0 |
T116 |
1732 |
0 |
0 |
0 |
T138 |
0 |
5 |
0 |
0 |
T139 |
0 |
1 |
0 |
0 |
T140 |
0 |
1 |
0 |
0 |
T141 |
0 |
4 |
0 |
0 |
T142 |
0 |
6 |
0 |
0 |
T143 |
0 |
4 |
0 |
0 |
T144 |
0 |
3 |
0 |
0 |
IoStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
144890486 |
142 |
0 |
0 |
T3 |
133182 |
0 |
0 |
0 |
T27 |
42175 |
0 |
0 |
0 |
T28 |
27111 |
0 |
0 |
0 |
T37 |
858 |
0 |
0 |
0 |
T43 |
1594 |
5 |
0 |
0 |
T44 |
1165 |
2 |
0 |
0 |
T45 |
0 |
3 |
0 |
0 |
T111 |
1680 |
0 |
0 |
0 |
T112 |
1483 |
0 |
0 |
0 |
T115 |
1391 |
0 |
0 |
0 |
T116 |
1732 |
0 |
0 |
0 |
T138 |
0 |
5 |
0 |
0 |
T139 |
0 |
1 |
0 |
0 |
T140 |
0 |
1 |
0 |
0 |
T141 |
0 |
4 |
0 |
0 |
T142 |
0 |
6 |
0 |
0 |
T143 |
0 |
4 |
0 |
0 |
T144 |
0 |
3 |
0 |
0 |
MainStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
144890486 |
146 |
0 |
0 |
T3 |
133182 |
0 |
0 |
0 |
T27 |
42175 |
0 |
0 |
0 |
T28 |
27111 |
0 |
0 |
0 |
T37 |
858 |
0 |
0 |
0 |
T43 |
1594 |
3 |
0 |
0 |
T44 |
1165 |
1 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T111 |
1680 |
0 |
0 |
0 |
T112 |
1483 |
0 |
0 |
0 |
T115 |
1391 |
0 |
0 |
0 |
T116 |
1732 |
0 |
0 |
0 |
T138 |
0 |
5 |
0 |
0 |
T139 |
0 |
3 |
0 |
0 |
T140 |
0 |
1 |
0 |
0 |
T141 |
0 |
2 |
0 |
0 |
T142 |
0 |
4 |
0 |
0 |
T143 |
0 |
4 |
0 |
0 |
T144 |
0 |
3 |
0 |
0 |
MainStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
144890486 |
146 |
0 |
0 |
T3 |
133182 |
0 |
0 |
0 |
T27 |
42175 |
0 |
0 |
0 |
T28 |
27111 |
0 |
0 |
0 |
T37 |
858 |
0 |
0 |
0 |
T43 |
1594 |
3 |
0 |
0 |
T44 |
1165 |
1 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T111 |
1680 |
0 |
0 |
0 |
T112 |
1483 |
0 |
0 |
0 |
T115 |
1391 |
0 |
0 |
0 |
T116 |
1732 |
0 |
0 |
0 |
T138 |
0 |
5 |
0 |
0 |
T139 |
0 |
3 |
0 |
0 |
T140 |
0 |
1 |
0 |
0 |
T141 |
0 |
2 |
0 |
0 |
T142 |
0 |
4 |
0 |
0 |
T143 |
0 |
4 |
0 |
0 |
T144 |
0 |
3 |
0 |
0 |
UsbStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
144890486 |
145 |
0 |
0 |
T3 |
133182 |
0 |
0 |
0 |
T27 |
42175 |
0 |
0 |
0 |
T28 |
27111 |
0 |
0 |
0 |
T37 |
858 |
0 |
0 |
0 |
T43 |
1594 |
5 |
0 |
0 |
T44 |
1165 |
1 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T111 |
1680 |
0 |
0 |
0 |
T112 |
1483 |
0 |
0 |
0 |
T115 |
1391 |
0 |
0 |
0 |
T116 |
1732 |
0 |
0 |
0 |
T138 |
0 |
5 |
0 |
0 |
T139 |
0 |
2 |
0 |
0 |
T140 |
0 |
1 |
0 |
0 |
T141 |
0 |
3 |
0 |
0 |
T142 |
0 |
4 |
0 |
0 |
T143 |
0 |
6 |
0 |
0 |
T144 |
0 |
3 |
0 |
0 |
UsbStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
144890486 |
145 |
0 |
0 |
T3 |
133182 |
0 |
0 |
0 |
T27 |
42175 |
0 |
0 |
0 |
T28 |
27111 |
0 |
0 |
0 |
T37 |
858 |
0 |
0 |
0 |
T43 |
1594 |
5 |
0 |
0 |
T44 |
1165 |
1 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T111 |
1680 |
0 |
0 |
0 |
T112 |
1483 |
0 |
0 |
0 |
T115 |
1391 |
0 |
0 |
0 |
T116 |
1732 |
0 |
0 |
0 |
T138 |
0 |
5 |
0 |
0 |
T139 |
0 |
2 |
0 |
0 |
T140 |
0 |
1 |
0 |
0 |
T141 |
0 |
3 |
0 |
0 |
T142 |
0 |
4 |
0 |
0 |
T143 |
0 |
6 |
0 |
0 |
T144 |
0 |
3 |
0 |
0 |