Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	44929	0	0
CgEnOn_A	2147483647	35415	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44929	0	0
T1	1403900	389	0	0
T3	1684095	0	0	0
T4	310003	39	0	0
T6	39242	18	0	0
T7	16198	44	0	0
T8	18422	3	0	0
T15	1656366	5	0	0
T17	5672	6	0	0
T18	34936	42	0	0
T19	22714	3	0	0
T20	14763	7	0	0
T21	8487	16	0	0
T27	220020	0	0	0
T28	242934	0	0	0
T37	12884	0	0	0
T43	4306	28	0	0
T44	2495	10	0	0
T45	0	15	0	0
T111	5665	0	0	0
T112	19106	0	0	0
T115	9406	1	0	0
T116	5575	0	0	0
T138	0	25	0	0
T139	0	5	0	0
T140	0	5	0	0
T141	0	20	0	0
T142	0	30	0	0
T145	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35415	0	0
T1	681238	207	0	0
T3	1151364	45	0	0
T4	34554	0	0	0
T7	3121	27	0	0
T8	4042	0	0	0
T10	0	25	0	0
T15	920600	4	0	0
T17	1095	2	0	0
T18	6771	20	0	0
T19	4380	0	0	0
T20	2865	2	0	0
T21	1620	10	0	0
T22	6441	0	0	0
T27	133950	0	0	0
T28	152566	0	0	0
T37	8797	0	0	0
T43	2930	35	0	0
T44	2302	10	0	0
T45	0	15	0	0
T111	3897	0	0	0
T112	13399	0	0	0
T115	6382	0	0	0
T116	3790	0	0	0
T138	0	25	0	0
T139	0	5	0	0
T140	0	5	0	0
T141	0	20	0	0
T142	0	30	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	4	0	0
T146	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	195591369	153	0	0
CgEnOn_A	195591369	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195591369	153	0	0
T3	255986	0	0	0
T15	368240	1	0	0
T27	29746	0	0	0
T28	26326	0	0	0
T37	1949	0	0	0
T43	627	5	0	0
T44	0	2	0	0
T45	0	3	0	0
T111	880	0	0	0
T112	3171	0	0	0
T115	1391	0	0	0
T116	831	0	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	6	0	0
T145	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195591369	153	0	0
T3	255986	0	0	0
T15	368240	1	0	0
T27	29746	0	0	0
T28	26326	0	0	0
T37	1949	0	0	0
T43	627	5	0	0
T44	0	2	0	0
T45	0	3	0	0
T111	880	0	0	0
T112	3171	0	0	0
T115	1391	0	0	0
T116	831	0	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	6	0	0
T145	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97795133	153	0	0
CgEnOn_A	97795133	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97795133	153	0	0
T3	127991	0	0	0
T15	184120	1	0	0
T27	14873	0	0	0
T28	13163	0	0	0
T37	975	0	0	0
T43	314	5	0	0
T44	0	2	0	0
T45	0	3	0	0
T111	440	0	0	0
T112	1583	0	0	0
T115	696	0	0	0
T116	415	0	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	6	0	0
T145	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97795133	153	0	0
T3	127991	0	0	0
T15	184120	1	0	0
T27	14873	0	0	0
T28	13163	0	0	0
T37	975	0	0	0
T43	314	5	0	0
T44	0	2	0	0
T45	0	3	0	0
T111	440	0	0	0
T112	1583	0	0	0
T115	696	0	0	0
T116	415	0	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	6	0	0
T145	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	392840153	153	0	0
CgEnOn_A	392840153	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392840153	153	0	0
T3	511405	0	0	0
T15	735766	1	0	0
T27	59585	0	0	0
T28	86751	0	0	0
T37	3923	0	0	0
T43	1361	5	0	0
T44	0	2	0	0
T45	0	3	0	0
T111	1697	0	0	0
T112	5479	0	0	0
T115	2903	0	0	0
T116	1714	0	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	6	0	0
T145	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392840153	142	0	0
T3	511405	0	0	0
T27	59585	0	0	0
T28	86751	0	0	0
T37	3923	0	0	0
T43	1361	5	0	0
T44	2302	2	0	0
T45	0	3	0	0
T111	1697	0	0	0
T112	5479	0	0	0
T115	2903	0	0	0
T116	1714	0	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	6	0	0
T143	0	4	0	0
T144	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419911733	148	0	0
CgEnOn_A	419911733	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419911733	148	0	0
T3	532731	0	0	0
T27	86070	0	0	0
T28	90368	0	0	0
T37	4087	0	0	0
T43	1376	3	0	0
T44	2495	1	0	0
T45	0	2	0	0
T111	1768	0	0	0
T112	5707	0	0	0
T115	3024	0	0	0
T116	1785	0	0	0
T138	0	5	0	0
T139	0	3	0	0
T140	0	1	0	0
T141	0	2	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419911733	146	0	0
T3	532731	0	0	0
T27	86070	0	0	0
T28	90368	0	0	0
T37	4087	0	0	0
T43	1376	3	0	0
T44	2495	1	0	0
T45	0	2	0	0
T111	1768	0	0	0
T112	5707	0	0	0
T115	3024	0	0	0
T116	1785	0	0	0
T138	0	5	0	0
T139	0	3	0	0
T140	0	1	0	0
T141	0	2	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97795133	153	0	0
CgEnOn_A	97795133	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97795133	153	0	0
T3	127991	0	0	0
T15	184120	1	0	0
T27	14873	0	0	0
T28	13163	0	0	0
T37	975	0	0	0
T43	314	5	0	0
T44	0	2	0	0
T45	0	3	0	0
T111	440	0	0	0
T112	1583	0	0	0
T115	696	0	0	0
T116	415	0	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	6	0	0
T145	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97795133	153	0	0
T3	127991	0	0	0
T15	184120	1	0	0
T27	14873	0	0	0
T28	13163	0	0	0
T37	975	0	0	0
T43	314	5	0	0
T44	0	2	0	0
T45	0	3	0	0
T111	440	0	0	0
T112	1583	0	0	0
T115	696	0	0	0
T116	415	0	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	6	0	0
T145	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419911733	148	0	0
CgEnOn_A	419911733	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419911733	148	0	0
T3	532731	0	0	0
T27	86070	0	0	0
T28	90368	0	0	0
T37	4087	0	0	0
T43	1376	3	0	0
T44	2495	1	0	0
T45	0	2	0	0
T111	1768	0	0	0
T112	5707	0	0	0
T115	3024	0	0	0
T116	1785	0	0	0
T138	0	5	0	0
T139	0	3	0	0
T140	0	1	0	0
T141	0	2	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419911733	146	0	0
T3	532731	0	0	0
T27	86070	0	0	0
T28	90368	0	0	0
T37	4087	0	0	0
T43	1376	3	0	0
T44	2495	1	0	0
T45	0	2	0	0
T111	1768	0	0	0
T112	5707	0	0	0
T115	3024	0	0	0
T116	1785	0	0	0
T138	0	5	0	0
T139	0	3	0	0
T140	0	1	0	0
T141	0	2	0	0
T142	0	4	0	0
T143	0	4	0	0
T144	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97795133	153	0	0
CgEnOn_A	97795133	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97795133	153	0	0
T3	127991	0	0	0
T15	184120	1	0	0
T27	14873	0	0	0
T28	13163	0	0	0
T37	975	0	0	0
T43	314	5	0	0
T44	0	2	0	0
T45	0	3	0	0
T111	440	0	0	0
T112	1583	0	0	0
T115	696	0	0	0
T116	415	0	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	6	0	0
T145	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97795133	153	0	0
T3	127991	0	0	0
T15	184120	1	0	0
T27	14873	0	0	0
T28	13163	0	0	0
T37	975	0	0	0
T43	314	5	0	0
T44	0	2	0	0
T45	0	3	0	0
T111	440	0	0	0
T112	1583	0	0	0
T115	696	0	0	0
T116	415	0	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	4	0	0
T142	0	6	0	0
T145	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T43,T44,T45
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	195591369	7138	0	0
CgEnOn_A	195591369	4769	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195591369	7138	0	0
T1	113540	113	0	0
T4	23036	13	0	0
T6	5130	2	0	0
T7	2081	14	0	0
T8	2695	1	0	0
T17	730	2	0	0
T18	4514	13	0	0
T19	2920	1	0	0
T20	1910	2	0	0
T21	1080	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195591369	4769	0	0
T1	113540	102	0	0
T3	0	22	0	0
T4	23036	0	0	0
T7	2081	13	0	0
T8	2695	0	0	0
T10	0	12	0	0
T17	730	1	0	0
T18	4514	11	0	0
T19	2920	0	0	0
T20	1910	1	0	0
T21	1080	5	0	0
T22	4295	0	0	0
T43	0	5	0	0
T146	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T43,T44,T45
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97795133	6988	0	0
CgEnOn_A	97795133	4619	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97795133	6988	0	0
T1	567698	116	0	0
T4	11518	13	0	0
T6	2565	2	0	0
T7	1040	15	0	0
T8	1347	1	0	0
T17	365	2	0	0
T18	2257	11	0	0
T19	1460	1	0	0
T20	955	2	0	0
T21	540	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97795133	4619	0	0
T1	567698	105	0	0
T3	0	23	0	0
T4	11518	0	0	0
T7	1040	14	0	0
T8	1347	0	0	0
T10	0	13	0	0
T17	365	1	0	0
T18	2257	9	0	0
T19	1460	0	0	0
T20	955	1	0	0
T21	540	5	0	0
T22	2146	0	0	0
T43	0	5	0	0
T146	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T43,T44,T45
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	392840153	7314	0	0
CgEnOn_A	392840153	4934	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392840153	7314	0	0
T1	228534	115	0	0
T4	89333	13	0	0
T6	10231	2	0	0
T7	4241	15	0	0
T8	4664	1	0	0
T17	1485	2	0	0
T18	9135	12	0	0
T19	5946	1	0	0
T20	3858	2	0	0
T21	2227	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392840153	4934	0	0
T1	228534	104	0	0
T3	0	25	0	0
T4	89333	0	0	0
T7	4241	14	0	0
T8	4664	0	0	0
T17	1485	1	0	0
T18	9135	10	0	0
T19	5946	0	0	0
T20	3858	1	0	0
T21	2227	3	0	0
T22	7067	0	0	0
T43	0	5	0	0
T116	0	1	0	0
T146	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T43,T44,T45
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	201586944	7156	0	0
CgEnOn_A	201586944	4776	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201586944	7156	0	0
T1	118592	113	0	0
T4	44669	13	0	0
T6	5115	2	0	0
T7	2120	14	0	0
T8	2332	1	0	0
T17	742	2	0	0
T18	4567	12	0	0
T19	2973	1	0	0
T20	1929	2	0	0
T21	1114	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201586944	4776	0	0
T1	118592	102	0	0
T3	0	25	0	0
T4	44669	0	0	0
T7	2120	13	0	0
T8	2332	0	0	0
T17	742	1	0	0
T18	4567	10	0	0
T19	2973	0	0	0
T20	1929	1	0	0
T21	1114	3	0	0
T22	3533	0	0	0
T43	0	5	0	0
T116	0	1	0	0
T146	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Covered	T6,T1,T18
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419911733	3841	0	0
CgEnOn_A	419911733	3840	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419911733	3841	0	0
T1	247064	45	0	0
T3	0	19	0	0
T4	93058	0	0	0
T6	10658	12	0	0
T7	4418	0	0	0
T8	4858	0	0	0
T17	1546	0	0	0
T18	9515	6	0	0
T19	6194	0	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T43	0	3	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	11	0	0
T118	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419911733	3840	0	0
T1	247064	45	0	0
T3	0	19	0	0
T4	93058	0	0	0
T6	10658	12	0	0
T7	4418	0	0	0
T8	4858	0	0	0
T17	1546	0	0	0
T18	9515	6	0	0
T19	6194	0	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T43	0	3	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	11	0	0
T118	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Covered	T6,T1,T18
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419911733	3801	0	0
CgEnOn_A	419911733	3803	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419911733	3801	0	0
T1	247064	50	0	0
T3	0	19	0	0
T4	93058	0	0	0
T6	10658	9	0	0
T7	4418	0	0	0
T8	4858	0	0	0
T17	1546	0	0	0
T18	9515	8	0	0
T19	6194	1	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T43	0	3	0	0
T115	0	2	0	0
T116	0	1	0	0
T117	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419911733	3803	0	0
T1	247064	50	0	0
T3	0	19	0	0
T4	93058	0	0	0
T6	10658	9	0	0
T7	4418	0	0	0
T8	4858	0	0	0
T17	1546	0	0	0
T18	9515	8	0	0
T19	6194	1	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T43	0	3	0	0
T115	0	2	0	0
T116	0	1	0	0
T117	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Covered	T6,T1,T18
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419911733	3775	0	0
CgEnOn_A	419911733	3774	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419911733	3775	0	0
T1	247064	47	0	0
T3	0	22	0	0
T4	93058	0	0	0
T6	10658	8	0	0
T7	4418	0	0	0
T8	4858	0	0	0
T17	1546	0	0	0
T18	9515	10	0	0
T19	6194	1	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T43	0	3	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419911733	3774	0	0
T1	247064	47	0	0
T3	0	22	0	0
T4	93058	0	0	0
T6	10658	8	0	0
T7	4418	0	0	0
T8	4858	0	0	0
T17	1546	0	0	0
T18	9515	10	0	0
T19	6194	1	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T43	0	3	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Covered	T6,T1,T18
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419911733	3855	0	0
CgEnOn_A	419911733	3854	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419911733	3855	0	0
T1	247064	46	0	0
T3	0	18	0	0
T4	93058	0	0	0
T6	10658	8	0	0
T7	4418	0	0	0
T8	4858	0	0	0
T17	1546	0	0	0
T18	9515	6	0	0
T19	6194	0	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T43	0	3	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	9	0	0
T118	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419911733	3854	0	0
T1	247064	46	0	0
T3	0	18	0	0
T4	93058	0	0	0
T6	10658	8	0	0
T7	4418	0	0	0
T8	4858	0	0	0
T17	1546	0	0	0
T18	9515	6	0	0
T19	6194	0	0	0
T20	4020	1	0	0
T21	2320	0	0	0
T43	0	3	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	9	0	0
T118	0	1	0	0