Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T17
0	1	Covered	T7,T1,T18
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T17
1	0	Covered	T43,T44,T45
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	887815296	12795	0	0
GateOpen_A	887815296	12795	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	887815296	12795	0	0
T1	1028364	295	0	0
T3	0	50	0	0
T4	168559	0	0	0
T7	9484	34	0	0
T8	11038	0	0	0
T17	3325	4	0	0
T18	20476	29	0	0
T19	13300	0	0	0
T20	8655	4	0	0
T21	4964	14	0	0
T22	17043	0	0	0
T43	0	20	0	0
T116	0	4	0	0
T146	0	18	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	887815296	12795	0	0
T1	1028364	295	0	0
T3	0	50	0	0
T4	168559	0	0	0
T7	9484	34	0	0
T8	11038	0	0	0
T17	3325	4	0	0
T18	20476	29	0	0
T19	13300	0	0	0
T20	8655	4	0	0
T21	4964	14	0	0
T22	17043	0	0	0
T43	0	20	0	0
T116	0	4	0	0
T146	0	18	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T17
0	1	Covered	T7,T1,T18
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T17
1	0	Covered	T43,T44,T45
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	97795551	3143	0	0
GateOpen_A	97795551	3143	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97795551	3143	0	0
T1	567698	71	0	0
T3	0	12	0	0
T4	11519	0	0	0
T7	1041	8	0	0
T8	1347	0	0	0
T17	366	1	0	0
T18	2258	6	0	0
T19	1460	0	0	0
T20	956	1	0	0
T21	541	4	0	0
T22	2147	0	0	0
T43	0	5	0	0
T116	0	1	0	0
T146	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97795551	3143	0	0
T1	567698	71	0	0
T3	0	12	0	0
T4	11519	0	0	0
T7	1041	8	0	0
T8	1347	0	0	0
T17	366	1	0	0
T18	2258	6	0	0
T19	1460	0	0	0
T20	956	1	0	0
T21	541	4	0	0
T22	2147	0	0	0
T43	0	5	0	0
T116	0	1	0	0
T146	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T17
0	1	Covered	T7,T1,T18
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T17
1	0	Covered	T43,T44,T45
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	195591789	3218	0	0
GateOpen_A	195591789	3218	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195591789	3218	0	0
T1	113540	74	0	0
T3	0	12	0	0
T4	23037	0	0	0
T7	2081	9	0	0
T8	2695	0	0	0
T17	731	1	0	0
T18	4515	8	0	0
T19	2920	0	0	0
T20	1911	1	0	0
T21	1081	4	0	0
T22	4295	0	0	0
T43	0	5	0	0
T116	0	1	0	0
T146	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195591789	3218	0	0
T1	113540	74	0	0
T3	0	12	0	0
T4	23037	0	0	0
T7	2081	9	0	0
T8	2695	0	0	0
T17	731	1	0	0
T18	4515	8	0	0
T19	2920	0	0	0
T20	1911	1	0	0
T21	1081	4	0	0
T22	4295	0	0	0
T43	0	5	0	0
T116	0	1	0	0
T146	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T17
0	1	Covered	T7,T1,T18
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T17
1	0	Covered	T43,T44,T45
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	392840573	3223	0	0
GateOpen_A	392840573	3223	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392840573	3223	0	0
T1	228534	74	0	0
T3	0	13	0	0
T4	89334	0	0	0
T7	4241	9	0	0
T8	4664	0	0	0
T17	1485	1	0	0
T18	9135	8	0	0
T19	5947	0	0	0
T20	3858	1	0	0
T21	2228	3	0	0
T22	7067	0	0	0
T43	0	5	0	0
T116	0	1	0	0
T146	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392840573	3223	0	0
T1	228534	74	0	0
T3	0	13	0	0
T4	89334	0	0	0
T7	4241	9	0	0
T8	4664	0	0	0
T17	1485	1	0	0
T18	9135	8	0	0
T19	5947	0	0	0
T20	3858	1	0	0
T21	2228	3	0	0
T22	7067	0	0	0
T43	0	5	0	0
T116	0	1	0	0
T146	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T17
0	1	Covered	T7,T1,T18
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T17
1	0	Covered	T43,T44,T45
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	201587383	3211	0	0
GateOpen_A	201587383	3211	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201587383	3211	0	0
T1	118592	76	0	0
T3	0	13	0	0
T4	44669	0	0	0
T7	2121	8	0	0
T8	2332	0	0	0
T17	743	1	0	0
T18	4568	7	0	0
T19	2973	0	0	0
T20	1930	1	0	0
T21	1114	3	0	0
T22	3534	0	0	0
T43	0	5	0	0
T116	0	1	0	0
T146	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201587383	3211	0	0
T1	118592	76	0	0
T3	0	13	0	0
T4	44669	0	0	0
T7	2121	8	0	0
T8	2332	0	0	0
T17	743	1	0	0
T18	4568	7	0	0
T19	2973	0	0	0
T20	1930	1	0	0
T21	1114	3	0	0
T22	3534	0	0	0
T43	0	5	0	0
T116	0	1	0	0
T146	0	5	0	0