Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	873045	0	0
SrcPulseCheck_M	2147483647	871989	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	873045
T1	329018	5067
T2	0	7763
T3	0	292
T4	48894	80
T5	64302	53
T6	211195	150
T7	148954	90
T9	3458	0
T12	0	15461
T13	0	268
T14	0	1208
T15	0	4041
T19	4475	0
T25	0	266
T28	3449	0
T29	6161	0
T30	4088	0
T31	4569	0
T32	4331	0
T34	12355	0
T35	0	419
T36	12431	0
T37	26654	0
T38	20420	0
T39	31117	0
T40	2916	0
T59	13156	3
T61	4787	1
T62	3729	1
T63	0	2
T65	0	1
T66	0	3
T119	0	1
T120	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	871989
T1	50118	4935
T2	0	7766
T3	0	292
T4	47526	80
T5	29014	53
T6	776	150
T7	80004	90
T9	3514	0
T12	0	15464
T13	0	268
T14	0	1208
T15	0	4042
T19	318	0
T25	0	266
T28	4453	0
T29	6127	0
T30	5224	0
T31	4721	0
T32	3312	0
T34	7221	0
T35	0	419
T36	1304	0
T37	2792	0
T38	2076	0
T39	3260	0
T40	208	0
T59	5444	3
T61	9460	1
T62	7018	1
T63	0	2
T65	0	1
T66	0	3
T119	0	1
T120	0	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	396426348	23040	0	0
SrcPulseCheck_M	150427568	23040	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	396426348	23040
T1	0	236
T2	0	421
T3	0	24
T4	54703	16
T5	44857	10
T6	0	30
T7	30867	6
T9	2330	0
T12	0	743
T25	0	18
T28	1764	0
T29	3900	0
T30	2076	0
T31	1669	0
T32	2000	0
T34	2532	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	150427568	23040
T1	0	236
T2	0	421
T3	0	24
T4	15386	16
T5	6075	10
T6	0	30
T7	32153	6
T9	1190	0
T12	0	743
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	396426348	29222	0	0
SrcPulseCheck_M	150427568	29239	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	396426348	29222
T1	0	241
T2	0	431
T3	0	24
T4	54703	32
T5	44857	20
T6	0	60
T7	30867	6
T9	2330	0
T12	0	753
T25	0	18
T28	1764	0
T29	3900	0
T30	2076	0
T31	1669	0
T32	2000	0
T34	2532	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	150427568	29239
T1	0	241
T2	0	431
T3	0	24
T4	15386	32
T5	6075	20
T6	0	60
T7	32153	6
T9	1190	0
T12	0	753
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	29207	0	0
SrcPulseCheck_M	396426348	29225	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	29207
T1	0	241
T2	0	431
T3	0	24
T4	15386	32
T5	6075	20
T6	0	60
T7	32153	6
T9	1190	0
T12	0	753
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	396426348	29225
T1	0	241
T2	0	431
T3	0	24
T4	54703	32
T5	44857	20
T6	0	60
T7	30867	6
T9	2330	0
T12	0	753
T25	0	18
T28	1764	0
T29	3900	0
T30	2076	0
T31	1669	0
T32	2000	0
T34	2532	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	197251858	23040	0	0
SrcPulseCheck_M	150427568	23040	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	197251858	23040
T1	0	236
T2	0	421
T3	0	24
T4	16754	16
T5	16636	10
T6	0	30
T7	15366	6
T9	1134	0
T12	0	743
T25	0	18
T28	815	0
T29	2065	0
T30	984	0
T31	781	0
T32	940	0
T34	1315	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	150427568	23040
T1	0	236
T2	0	421
T3	0	24
T4	15386	16
T5	6075	10
T6	0	30
T7	32153	6
T9	1190	0
T12	0	743
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	197251858	29236	0	0
SrcPulseCheck_M	150427568	29254	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	197251858	29236
T1	0	241
T2	0	431
T3	0	24
T4	16754	32
T5	16636	20
T6	0	60
T7	15366	6
T9	1134	0
T12	0	753
T25	0	18
T28	815	0
T29	2065	0
T30	984	0
T31	781	0
T32	940	0
T34	1315	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	150427568	29254
T1	0	241
T2	0	431
T3	0	24
T4	15386	32
T5	6075	20
T6	0	60
T7	32153	6
T9	1190	0
T12	0	753
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	29227	0	0
SrcPulseCheck_M	197251858	29239	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	29227
T1	0	241
T2	0	431
T3	0	24
T4	15386	32
T5	6075	20
T6	0	60
T7	32153	6
T9	1190	0
T12	0	753
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	197251858	29239
T1	0	241
T2	0	431
T3	0	24
T4	16754	32
T5	16636	20
T6	0	60
T7	15366	6
T9	1134	0
T12	0	753
T25	0	18
T28	815	0
T29	2065	0
T30	984	0
T31	781	0
T32	940	0
T34	1315	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	98625279	23040	0	0
SrcPulseCheck_M	150427568	23040	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	98625279	23040
T1	0	236
T2	0	421
T3	0	24
T4	8377	16
T5	8319	10
T6	0	30
T7	7683	6
T9	567	0
T12	0	743
T25	0	18
T28	407	0
T29	1032	0
T30	492	0
T31	391	0
T32	470	0
T34	656	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	150427568	23040
T1	0	236
T2	0	421
T3	0	24
T4	15386	16
T5	6075	10
T6	0	30
T7	32153	6
T9	1190	0
T12	0	743
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	98625279	29391	0	0
SrcPulseCheck_M	150427568	29435	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	98625279	29391
T1	0	241
T2	0	431
T3	0	24
T4	8377	32
T5	8319	20
T6	0	60
T7	7683	6
T9	567	0
T12	0	753
T25	0	18
T28	407	0
T29	1032	0
T30	492	0
T31	391	0
T32	470	0
T34	656	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	150427568	29435
T1	0	241
T2	0	431
T3	0	24
T4	15386	32
T5	6075	20
T6	0	60
T7	32153	6
T9	1190	0
T12	0	753
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	29392	0	0
SrcPulseCheck_M	98625279	29394	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	29392
T1	0	241
T2	0	431
T3	0	24
T4	15386	32
T5	6075	20
T6	0	60
T7	32153	6
T9	1190	0
T12	0	753
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	98625279	29394
T1	0	241
T2	0	431
T3	0	24
T4	8377	32
T5	8319	20
T6	0	60
T7	7683	6
T9	567	0
T12	0	753
T25	0	18
T28	407	0
T29	1032	0
T30	492	0
T31	391	0
T32	470	0
T34	656	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	422813339	23040	0	0
SrcPulseCheck_M	150427568	23040	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	422813339	23040
T1	0	236
T2	0	421
T3	0	24
T4	56984	16
T5	46727	10
T6	0	30
T7	32153	6
T9	2428	0
T12	0	743
T25	0	18
T28	1837	0
T29	4062	0
T30	2163	0
T31	1760	0
T32	2083	0
T34	2637	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	150427568	23040
T1	0	236
T2	0	421
T3	0	24
T4	15386	16
T5	6075	10
T6	0	30
T7	32153	6
T9	1190	0
T12	0	743
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	422813339	29229	0	0
SrcPulseCheck_M	150427568	29243	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	422813339	29229
T1	0	241
T2	0	431
T3	0	24
T4	56984	32
T5	46727	20
T6	0	60
T7	32153	6
T9	2428	0
T12	0	753
T25	0	18
T28	1837	0
T29	4062	0
T30	2163	0
T31	1760	0
T32	2083	0
T34	2637	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	150427568	29243
T1	0	241
T2	0	431
T3	0	24
T4	15386	32
T5	6075	20
T6	0	60
T7	32153	6
T9	1190	0
T12	0	753
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	29220	0	0
SrcPulseCheck_M	422813339	29230	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	29220
T1	0	241
T2	0	431
T3	0	24
T4	15386	32
T5	6075	20
T6	0	60
T7	32153	6
T9	1190	0
T12	0	753
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	422813339	29230
T1	0	241
T2	0	431
T3	0	24
T4	56984	32
T5	46727	20
T6	0	60
T7	32153	6
T9	2428	0
T12	0	753
T25	0	18
T28	1837	0
T29	4062	0
T30	2163	0
T31	1760	0
T32	2083	0
T34	2637	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	203100787	22594	0	0
SrcPulseCheck_M	150427568	23040	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	203100787	22594
T1	0	236
T2	0	421
T3	0	24
T4	27353	8
T5	22429	10
T6	0	15
T7	15433	6
T9	1165	0
T12	0	743
T25	0	18
T28	882	0
T29	1950	0
T30	1038	0
T31	877	0
T32	999	0
T34	1266	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	150427568	23040
T1	0	236
T2	0	421
T3	0	24
T4	15386	16
T5	6075	10
T6	0	30
T7	32153	6
T9	1190	0
T12	0	743
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	203100787	28989	0	0
SrcPulseCheck_M	150427568	29160	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	203100787	28989
T1	0	241
T2	0	431
T3	0	24
T4	27353	32
T5	22429	20
T6	0	45
T7	15433	6
T9	1165	0
T12	0	753
T25	0	18
T28	882	0
T29	1950	0
T30	1038	0
T31	877	0
T32	999	0
T34	1266	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	150427568	29160
T1	0	241
T2	0	431
T3	0	24
T4	15386	32
T5	6075	20
T6	0	60
T7	32153	6
T9	1190	0
T12	0	753
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	28858	0	0
SrcPulseCheck_M	203100787	29016	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	28858
T1	0	241
T2	0	431
T3	0	24
T4	15386	29
T5	6075	20
T6	0	45
T7	32153	6
T9	1190	0
T12	0	753
T25	0	18
T28	1819	0
T29	2031	0
T30	2120	0
T31	1835	0
T32	1041	0
T34	2585	0
T35	0	16

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	203100787	29016
T1	0	241
T2	0	431
T3	0	24
T4	27353	32
T5	22429	20
T6	0	45
T7	15433	6
T9	1165	0
T12	0	753
T25	0	18
T28	882	0
T29	1950	0
T30	1038	0
T31	877	0
T32	999	0
T34	1266	0
T35	0	16

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T60,T62,T63
1	0	Covered	T60,T62,T63
1	1	Covered	T63,T66,T121

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T60,T62,T63
1	0	Covered	T63,T66,T121
1	1	Covered	T60,T62,T63

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	35	0	0
SrcPulseCheck_M	396426348	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	35
T60	6170	1
T62	3729	1
T63	4229	2
T64	2751	1
T65	9256	1
T66	12956	4
T121	6817	3
T122	11595	2
T123	6451	1
T124	7424	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	396426348	35
T60	6170	1
T62	14915	1
T63	14001	2
T64	5502	1
T65	9353	1
T66	12956	4
T121	26179	3
T122	11130	2
T123	25804	1
T124	54821	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T60,T61,T62
1	0	Covered	T60,T61,T62
1	1	Covered	T63,T121,T125

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T60,T61,T62
1	0	Covered	T63,T121,T125
1	1	Covered	T60,T61,T62

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	31	0	0
SrcPulseCheck_M	396426348	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	31
T60	6170	1
T61	4787	1
T62	3729	1
T63	4229	2
T65	9256	2
T66	12956	2
T122	11595	2
T123	6451	1
T126	13729	1
T127	6570	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	396426348	31
T60	6170	1
T61	19982	1
T62	14915	1
T63	14001	2
T65	9353	2
T66	12956	2
T122	11130	2
T123	25804	1
T126	13312	1
T127	33197	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T59,T61,T62
1	0	Covered	T59,T61,T62
1	1	Covered	T66,T122,T127

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T59,T61,T62
1	0	Covered	T66,T122,T127
1	1	Covered	T59,T61,T62

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	35	0	0
SrcPulseCheck_M	197251858	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	35
T59	13156	3
T61	4787	1
T62	3729	1
T63	4229	2
T65	9256	1
T66	12956	3
T119	5385	1
T120	5215	1
T122	11595	2
T128	6671	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	197251858	35
T59	5444	3
T61	9460	1
T62	7018	1
T63	6456	2
T65	4017	1
T66	5528	3
T119	2465	1
T120	4628	1
T122	4611	2
T128	2771	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T59,T60,T61
1	0	Covered	T59,T60,T61
1	1	Covered	T119

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T59,T60,T61
1	0	Covered	T119
1	1	Covered	T59,T60,T61

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	34	0	0
SrcPulseCheck_M	197251858	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	34
T59	13156	2
T60	6170	1
T61	4787	2
T62	3729	2
T63	4229	2
T65	9256	1
T66	12956	3
T119	5385	2
T126	13729	1
T129	9843	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	197251858	34
T59	5444	2
T60	2740	1
T61	9460	2
T62	7018	2
T63	6456	2
T65	4017	1
T66	5528	3
T119	2465	2
T126	5962	1
T129	8646	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T58,T59,T61
1	0	Covered	T58,T59,T61
1	1	Covered	T59,T62,T122

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T58,T59,T61
1	0	Covered	T59,T62,T122
1	1	Covered	T58,T59,T61

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	46	0	0
SrcPulseCheck_M	98625279	46	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	46
T58	11555	2
T59	13156	3
T61	4787	1
T62	3729	4
T66	12956	2
T119	5385	1
T120	5215	2
T122	11595	3
T126	13729	2
T130	10200	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	98625279	46
T58	6164	2
T59	2725	3
T61	4730	1
T62	3508	4
T66	2767	2
T119	1232	1
T120	2315	2
T122	2303	3
T126	2983	2
T130	9009	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T58,T59,T62
1	0	Covered	T58,T59,T62
1	1	Covered	T59,T62,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T58,T59,T62
1	0	Covered	T59,T62,T64
1	1	Covered	T58,T59,T62

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	45	0	0
SrcPulseCheck_M	98625279	45	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	45
T58	11555	3
T59	13156	3
T62	3729	3
T64	2751	2
T66	12956	2
T119	5385	2
T120	5215	4
T122	11595	4
T126	13729	2
T130	10200	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	98625279	45
T58	6164	3
T59	2725	3
T62	3508	3
T64	1263	2
T66	2767	2
T119	1232	2
T120	2315	4
T122	2303	4
T126	2983	2
T130	9009	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T58,T59,T60
1	0	Covered	T58,T59,T60
1	1	Covered	T64,T119,T128

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T58,T59,T60
1	0	Covered	T64,T119,T128
1	1	Covered	T58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	45	0	0
SrcPulseCheck_M	422813339	45	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	45
T58	11555	1
T59	13156	2
T60	6170	1
T61	4787	1
T62	3729	2
T63	4229	1
T64	2751	3
T65	9256	1
T83	7339	1
T126	13729	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	422813339	45
T58	27515	1
T59	13289	2
T60	6428	1
T61	20815	1
T62	15538	2
T63	14585	1
T64	5732	3
T65	9744	1
T83	7724	1
T126	13867	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T58,T59,T60
1	0	Covered	T58,T59,T60
1	1	Covered	T64,T128,T127

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T58,T59,T60
1	0	Covered	T64,T128,T127
1	1	Covered	T58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	45	0	0
SrcPulseCheck_M	422813339	45	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	45
T58	11555	1
T59	13156	2
T60	6170	1
T61	4787	2
T62	3729	2
T63	4229	1
T64	2751	2
T119	5385	1
T126	13729	1
T130	10200	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	422813339	45
T58	27515	1
T59	13289	2
T60	6428	1
T61	20815	2
T62	15538	2
T63	14585	1
T64	5732	2
T119	5611	1
T126	13867	1
T130	39234	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T58,T65,T66
1	0	Covered	T58,T65,T66
1	1	Covered	T131,T132,T133

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T58,T65,T66
1	0	Covered	T131,T132,T133
1	1	Covered	T58,T65,T66

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	32	0	0
SrcPulseCheck_M	203100787	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	32
T58	11555	1
T65	9256	3
T66	12956	2
T120	5215	1
T123	6451	1
T124	7424	1
T127	6570	2
T131	3401	2
T132	8738	3
T134	7552	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	203100787	32
T58	13207	1
T65	4676	3
T66	6478	2
T120	5215	1
T123	12902	1
T124	27412	1
T127	16599	2
T131	32653	2
T132	27963	3
T134	7399	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T58,T59,T60
1	0	Covered	T58,T59,T60
1	1	Covered	T62,T132,T125

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T58,T59,T60
1	0	Covered	T62,T132,T125
1	1	Covered	T58,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	150427568	27	0	0
SrcPulseCheck_M	203100787	27	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	150427568	27
T58	11555	1
T59	13156	1
T60	6170	1
T62	3729	2
T65	9256	1
T123	6451	1
T127	6570	2
T130	10200	1
T132	8738	4
T135	3563	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	203100787	27
T58	13207	1
T59	6378	1
T60	3085	1
T62	7458	2
T65	4676	1
T123	12902	1
T127	16599	2
T130	18832	1
T132	27963	4
T135	6841	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T7,T1,T25
1	0	Covered	T7,T1,T25
1	1	Covered	T7,T1,T25

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T7,T1,T25
1	0	Covered	T7,T1,T25
1	1	Covered	T7,T1,T25

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	393101660	86971	0	0
SrcPulseCheck_M	16135358	86524	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	393101660	86971
T1	153077	1007
T2	0	1582
T3	0	55
T6	86775	0
T7	30867	18
T12	0	3149
T13	0	67
T14	0	272
T15	0	1842
T19	2192	0
T25	0	53
T34	2532	0
T35	0	84
T36	4478	0
T37	9583	0
T38	7123	0
T39	11182	0
T40	1428	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16135358	86524
T1	24052	963
T2	0	1583
T3	0	55
T6	194	0
T7	83	18
T12	0	3150
T13	0	67
T14	0	272
T15	0	1842
T19	159	0
T25	0	53
T34	184	0
T35	0	84
T36	326	0
T37	698	0
T38	519	0
T39	815	0
T40	104	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T5,T7,T1
1	0	Covered	T7,T1,T25
1	1	Covered	T5,T7,T1

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T5,T7,T1
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T7,T1

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	195636578	86303	0	0
SrcPulseCheck_M	16135358	85860	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	195636578	86303
T1	0	1007
T2	0	1582
T3	0	55
T5	16636	2
T6	22684	0
T7	15366	18
T12	0	3123
T13	0	67
T14	0	272
T25	0	53
T31	781	0
T32	940	0
T34	1315	0
T35	0	84
T36	2192	0
T37	4725	0
T38	3919	0
T39	5524	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16135358	85860
T1	0	963
T2	0	1583
T3	0	55
T5	114	2
T6	194	0
T7	83	18
T12	0	3124
T13	0	67
T14	0	272
T25	0	53
T31	135	0
T32	145	0
T34	184	0
T35	0	84
T36	326	0
T37	698	0
T38	519	0
T39	815	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T5,T7,T1
1	0	Covered	T7,T1,T25
1	1	Covered	T7,T1,T25

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T5,T7,T1
1	0	Covered	T7,T1,T25
1	1	Covered	T5,T7,T1

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	97817651	85421	0	0
SrcPulseCheck_M	16135358	84987	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	97817651	85421
T1	0	1006
T2	0	1582
T3	0	55
T5	8319	1
T6	11343	0
T7	7683	18
T12	0	3098
T13	0	67
T14	0	272
T25	0	53
T31	391	0
T32	470	0
T34	656	0
T35	0	84
T36	1096	0
T37	2362	0
T38	1959	0
T39	2762	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16135358	84987
T1	0	962
T2	0	1583
T3	0	55
T5	114	1
T6	194	0
T7	83	18
T12	0	3099
T13	0	67
T14	0	272
T25	0	53
T31	135	0
T32	145	0
T34	184	0
T35	0	84
T36	326	0
T37	698	0
T38	519	0
T39	815	0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T7,T1,T25
1	0	Covered	T7,T1,T25
1	1	Covered	T7,T1,T25

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T7,T1,T25
1	0	Covered	T7,T1,T25
1	1	Covered	T7,T1,T25

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	419349993	103944	0	0
SrcPulseCheck_M	16058547	103356	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	419349993	103944
T1	175941	1329
T2	0	1734
T3	0	55
T6	90393	0
T7	32153	18
T12	0	3842
T13	0	67
T14	0	392
T15	0	2199
T19	2283	0
T25	0	53
T34	2637	0
T35	0	119
T36	4665	0
T37	9984	0
T38	7419	0
T39	11649	0
T40	1488	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16058547	103356
T1	26066	1329
T2	0	1734
T3	0	55
T6	194	0
T7	83	18
T12	0	3842
T13	0	67
T14	0	392
T15	0	2200
T19	159	0
T25	0	53
T34	184	0
T35	0	119
T36	326	0
T37	698	0
T38	519	0
T39	815	0
T40	104	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T7,T1,T25
1	0	Covered	T7,T1,T25
1	1	Covered	T7,T1,T25

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T7,T1,T25
1	0	Covered	T7,T1,T25
1	1	Covered	T7,T1,T25

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T8,T4,T9

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	201438402	103306	0	0
SrcPulseCheck_M	16225421	103252	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	201438402	103306
T1	850294	1349
T2	0	1782
T3	0	55
T6	43390	0
T7	15433	18
T12	0	3691
T13	0	67
T14	0	356
T15	0	2318
T19	1096	0
T25	0	53
T34	1266	0
T35	0	101
T36	2239	0
T37	4792	0
T38	3561	0
T39	5591	0
T40	714	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16225421	103252
T1	26090	1349
T2	0	1782
T3	0	55
T6	194	0
T7	83	18
T12	0	3691
T13	0	67
T14	0	356
T15	0	2318
T19	159	0
T25	0	53
T34	184	0
T35	0	101
T36	326	0
T37	698	0
T38	519	0
T39	815	0
T40	104	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb