Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1504275680	1362614	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1504275680	260636	0	0
SrcBusyKnown_A	1504275680	1476285220	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1504275680	1362614	0	0
T1	0	19032	0	0
T2	0	35983	0	0
T3	0	1907	0	0
T4	153860	819	0	0
T5	60750	384	0	0
T6	0	3682	0	0
T7	321530	479	0	0
T9	11900	0	0	0
T12	0	38842	0	0
T25	0	1457	0	0
T28	18190	0	0	0
T29	20310	0	0	0
T30	21200	0	0	0
T31	18350	0	0	0
T32	10410	0	0	0
T34	25850	0	0	0
T35	0	541	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	328342	84428	0	0
T5	277936	148614	0	0
T7	203004	201688	0	0
T8	12848	12268	0	0
T9	15248	13822	0	0
T28	11410	10184	0	0
T29	26018	25092	0	0
T30	13506	12148	0	0
T31	10956	9782	0	0
T32	12984	11738	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1504275680	260636	0	0
T1	0	2385	0	0
T2	0	4260	0	0
T3	0	240	0	0
T4	153860	230	0	0
T5	60750	150	0	0
T6	0	420	0	0
T7	321530	60	0	0
T9	11900	0	0	0
T12	0	7480	0	0
T25	0	180	0	0
T28	18190	0	0	0
T29	20310	0	0	0
T30	21200	0	0	0
T31	18350	0	0	0
T32	10410	0	0	0
T34	25850	0	0	0
T35	0	160	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1504275680	1476285220	0	0
T4	153860	36070	0	0
T5	60750	30570	0	0
T7	321530	319130	0	0
T8	19570	18630	0	0
T9	11900	10650	0	0
T28	18190	15950	0	0
T29	20310	19460	0	0
T30	21200	18840	0	0
T31	18350	16340	0	0
T32	10410	9280	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	150427568	84087	0	0
DstReqKnown_A	396426348	391605739	0	0
SrcAckBusyChk_A	150427568	23040	0	0
SrcBusyKnown_A	150427568	147628522	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	84087	0	0
T1	0	1176	0	0
T2	0	2165	0	0
T3	0	121	0	0
T4	15386	40	0	0
T5	6075	22	0	0
T6	0	159	0	0
T7	32153	29	0	0
T9	1190	0	0	0
T12	0	2599	0	0
T25	0	91	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	39	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396426348	391605739	0	0
T4	54703	12823	0	0
T5	44857	22574	0	0
T7	30867	30636	0	0
T8	1957	1863	0	0
T9	2330	2086	0	0
T28	1764	1547	0	0
T29	3900	3738	0	0
T30	2076	1845	0	0
T31	1669	1466	0	0
T32	2000	1783	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	23040	0	0
T1	0	236	0	0
T2	0	421	0	0
T3	0	24	0	0
T4	15386	16	0	0
T5	6075	10	0	0
T6	0	30	0	0
T7	32153	6	0	0
T9	1190	0	0	0
T12	0	743	0	0
T25	0	18	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	147628522	0	0
T4	15386	3607	0	0
T5	6075	3057	0	0
T7	32153	31913	0	0
T8	1957	1863	0	0
T9	1190	1065	0	0
T28	1819	1595	0	0
T29	2031	1946	0	0
T30	2120	1884	0	0
T31	1835	1634	0	0
T32	1041	928	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	150427568	120356	0	0
DstReqKnown_A	197251858	196065950	0	0
SrcAckBusyChk_A	150427568	23040	0	0
SrcBusyKnown_A	150427568	147628522	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	120356	0	0
T1	0	1879	0	0
T2	0	3449	0	0
T3	0	196	0	0
T4	15386	57	0	0
T5	6075	22	0	0
T6	0	255	0	0
T7	32153	48	0	0
T9	1190	0	0	0
T12	0	3714	0	0
T25	0	148	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	57	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197251858	196065950	0	0
T4	16754	6413	0	0
T5	16636	11287	0	0
T7	15366	15318	0	0
T8	966	931	0	0
T9	1134	1072	0	0
T28	815	774	0	0
T29	2065	2031	0	0
T30	984	922	0	0
T31	781	733	0	0
T32	940	892	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	23040	0	0
T1	0	236	0	0
T2	0	421	0	0
T3	0	24	0	0
T4	15386	16	0	0
T5	6075	10	0	0
T6	0	30	0	0
T7	32153	6	0	0
T9	1190	0	0	0
T12	0	743	0	0
T25	0	18	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	147628522	0	0
T4	15386	3607	0	0
T5	6075	3057	0	0
T7	32153	31913	0	0
T8	1957	1863	0	0
T9	1190	1065	0	0
T28	1819	1595	0	0
T29	2031	1946	0	0
T30	2120	1884	0	0
T31	1835	1634	0	0
T32	1041	928	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	150427568	193061	0	0
DstReqKnown_A	98625279	98032433	0	0
SrcAckBusyChk_A	150427568	23040	0	0
SrcBusyKnown_A	150427568	147628522	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	193061	0	0
T1	0	3307	0	0
T2	0	6158	0	0
T3	0	326	0	0
T4	15386	80	0	0
T5	6075	32	0	0
T6	0	449	0	0
T7	32153	85	0	0
T9	1190	0	0	0
T12	0	5950	0	0
T25	0	257	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	80	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98625279	98032433	0	0
T4	8377	3207	0	0
T5	8319	5644	0	0
T7	7683	7659	0	0
T8	483	466	0	0
T9	567	536	0	0
T28	407	386	0	0
T29	1032	1015	0	0
T30	492	461	0	0
T31	391	367	0	0
T32	470	446	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	23040	0	0
T1	0	236	0	0
T2	0	421	0	0
T3	0	24	0	0
T4	15386	16	0	0
T5	6075	10	0	0
T6	0	30	0	0
T7	32153	6	0	0
T9	1190	0	0	0
T12	0	743	0	0
T25	0	18	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	147628522	0	0
T4	15386	3607	0	0
T5	6075	3057	0	0
T7	32153	31913	0	0
T8	1957	1863	0	0
T9	1190	1065	0	0
T28	1819	1595	0	0
T29	2031	1946	0	0
T30	2120	1884	0	0
T31	1835	1634	0	0
T32	1041	928	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	150427568	82999	0	0
DstReqKnown_A	422813339	417748847	0	0
SrcAckBusyChk_A	150427568	23040	0	0
SrcBusyKnown_A	150427568	147628522	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	82999	0	0
T1	0	1149	0	0
T2	0	2528	0	0
T3	0	118	0	0
T4	15386	39	0	0
T5	6075	22	0	0
T6	0	184	0	0
T7	32153	34	0	0
T9	1190	0	0	0
T12	0	2565	0	0
T25	0	90	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	39	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422813339	417748847	0	0
T4	56984	13358	0	0
T5	46727	23515	0	0
T7	32153	31913	0	0
T8	2039	1942	0	0
T9	2428	2174	0	0
T28	1837	1611	0	0
T29	4062	3893	0	0
T30	2163	1923	0	0
T31	1760	1549	0	0
T32	2083	1857	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	23040	0	0
T1	0	236	0	0
T2	0	421	0	0
T3	0	24	0	0
T4	15386	16	0	0
T5	6075	10	0	0
T6	0	30	0	0
T7	32153	6	0	0
T9	1190	0	0	0
T12	0	743	0	0
T25	0	18	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	147628522	0	0
T4	15386	3607	0	0
T5	6075	3057	0	0
T7	32153	31913	0	0
T8	1957	1863	0	0
T9	1190	1065	0	0
T28	1819	1595	0	0
T29	2031	1946	0	0
T30	2120	1884	0	0
T31	1835	1634	0	0
T32	1041	928	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	150427568	119318	0	0
DstReqKnown_A	203100787	200672878	0	0
SrcAckBusyChk_A	150427568	22528	0	0
SrcBusyKnown_A	150427568	147628522	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	119318	0	0
T1	0	1902	0	0
T2	0	3462	0	0
T3	0	191	0	0
T4	15386	37	0	0
T5	6075	23	0	0
T6	0	143	0	0
T7	32153	46	0	0
T9	1190	0	0	0
T12	0	4457	0	0
T25	0	144	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	55	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	203100787	200672878	0	0
T4	27353	6413	0	0
T5	22429	11287	0	0
T7	15433	15318	0	0
T8	979	932	0	0
T9	1165	1043	0	0
T28	882	774	0	0
T29	1950	1869	0	0
T30	1038	923	0	0
T31	877	776	0	0
T32	999	891	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	22528	0	0
T1	0	236	0	0
T2	0	421	0	0
T3	0	24	0	0
T4	15386	8	0	0
T5	6075	10	0	0
T6	0	15	0	0
T7	32153	6	0	0
T9	1190	0	0	0
T12	0	743	0	0
T25	0	18	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	147628522	0	0
T4	15386	3607	0	0
T5	6075	3057	0	0
T7	32153	31913	0	0
T8	1957	1863	0	0
T9	1190	1065	0	0
T28	1819	1595	0	0
T29	2031	1946	0	0
T30	2120	1884	0	0
T31	1835	1634	0	0
T32	1041	928	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	150427568	106364	0	0
DstReqKnown_A	396426348	391605739	0	0
SrcAckBusyChk_A	150427568	29208	0	0
SrcBusyKnown_A	150427568	147628522	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	106364	0	0
T1	0	1209	0	0
T2	0	2215	0	0
T3	0	119	0	0
T4	15386	81	0	0
T5	6075	47	0	0
T6	0	311	0	0
T7	32153	29	0	0
T9	1190	0	0	0
T12	0	2637	0	0
T25	0	93	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	41	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396426348	391605739	0	0
T4	54703	12823	0	0
T5	44857	22574	0	0
T7	30867	30636	0	0
T8	1957	1863	0	0
T9	2330	2086	0	0
T28	1764	1547	0	0
T29	3900	3738	0	0
T30	2076	1845	0	0
T31	1669	1466	0	0
T32	2000	1783	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	29208	0	0
T1	0	241	0	0
T2	0	431	0	0
T3	0	24	0	0
T4	15386	32	0	0
T5	6075	20	0	0
T6	0	60	0	0
T7	32153	6	0	0
T9	1190	0	0	0
T12	0	753	0	0
T25	0	18	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	147628522	0	0
T4	15386	3607	0	0
T5	6075	3057	0	0
T7	32153	31913	0	0
T8	1957	1863	0	0
T9	1190	1065	0	0
T28	1819	1595	0	0
T29	2031	1946	0	0
T30	2120	1884	0	0
T31	1835	1634	0	0
T32	1041	928	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	150427568	152556	0	0
DstReqKnown_A	197251858	196065950	0	0
SrcAckBusyChk_A	150427568	29229	0	0
SrcBusyKnown_A	150427568	147628522	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	152556	0	0
T1	0	1933	0	0
T2	0	3568	0	0
T3	0	196	0	0
T4	15386	118	0	0
T5	6075	50	0	0
T6	0	505	0	0
T7	32153	46	0	0
T9	1190	0	0	0
T12	0	3766	0	0
T25	0	148	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	55	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197251858	196065950	0	0
T4	16754	6413	0	0
T5	16636	11287	0	0
T7	15366	15318	0	0
T8	966	931	0	0
T9	1134	1072	0	0
T28	815	774	0	0
T29	2065	2031	0	0
T30	984	922	0	0
T31	781	733	0	0
T32	940	892	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	29229	0	0
T1	0	241	0	0
T2	0	431	0	0
T3	0	24	0	0
T4	15386	32	0	0
T5	6075	20	0	0
T6	0	60	0	0
T7	32153	6	0	0
T9	1190	0	0	0
T12	0	753	0	0
T25	0	18	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	147628522	0	0
T4	15386	3607	0	0
T5	6075	3057	0	0
T7	32153	31913	0	0
T8	1957	1863	0	0
T9	1190	1065	0	0
T28	1819	1595	0	0
T29	2031	1946	0	0
T30	2120	1884	0	0
T31	1835	1634	0	0
T32	1041	928	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	150427568	246280	0	0
DstReqKnown_A	98625279	98032433	0	0
SrcAckBusyChk_A	150427568	29392	0	0
SrcBusyKnown_A	150427568	147628522	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	246280	0	0
T1	0	3372	0	0
T2	0	6267	0	0
T3	0	336	0	0
T4	15386	170	0	0
T5	6075	71	0	0
T6	0	888	0	0
T7	32153	83	0	0
T9	1190	0	0	0
T12	0	6033	0	0
T25	0	251	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	81	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98625279	98032433	0	0
T4	8377	3207	0	0
T5	8319	5644	0	0
T7	7683	7659	0	0
T8	483	466	0	0
T9	567	536	0	0
T28	407	386	0	0
T29	1032	1015	0	0
T30	492	461	0	0
T31	391	367	0	0
T32	470	446	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	29392	0	0
T1	0	241	0	0
T2	0	431	0	0
T3	0	24	0	0
T4	15386	32	0	0
T5	6075	20	0	0
T6	0	60	0	0
T7	32153	6	0	0
T9	1190	0	0	0
T12	0	753	0	0
T25	0	18	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	147628522	0	0
T4	15386	3607	0	0
T5	6075	3057	0	0
T7	32153	31913	0	0
T8	1957	1863	0	0
T9	1190	1065	0	0
T28	1819	1595	0	0
T29	2031	1946	0	0
T30	2120	1884	0	0
T31	1835	1634	0	0
T32	1041	928	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	150427568	105131	0	0
DstReqKnown_A	422813339	417748847	0	0
SrcAckBusyChk_A	150427568	29223	0	0
SrcBusyKnown_A	150427568	147628522	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	105131	0	0
T1	0	1172	0	0
T2	0	2591	0	0
T3	0	119	0	0
T4	15386	81	0	0
T5	6075	47	0	0
T6	0	366	0	0
T7	32153	34	0	0
T9	1190	0	0	0
T12	0	2602	0	0
T25	0	89	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	39	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422813339	417748847	0	0
T4	56984	13358	0	0
T5	46727	23515	0	0
T7	32153	31913	0	0
T8	2039	1942	0	0
T9	2428	2174	0	0
T28	1837	1611	0	0
T29	4062	3893	0	0
T30	2163	1923	0	0
T31	1760	1549	0	0
T32	2083	1857	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	29223	0	0
T1	0	241	0	0
T2	0	431	0	0
T3	0	24	0	0
T4	15386	32	0	0
T5	6075	20	0	0
T6	0	60	0	0
T7	32153	6	0	0
T9	1190	0	0	0
T12	0	753	0	0
T25	0	18	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	147628522	0	0
T4	15386	3607	0	0
T5	6075	3057	0	0
T7	32153	31913	0	0
T8	1957	1863	0	0
T9	1190	1065	0	0
T28	1819	1595	0	0
T29	2031	1946	0	0
T30	2120	1884	0	0
T31	1835	1634	0	0
T32	1041	928	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T4,T9
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	150427568	152462	0	0
DstReqKnown_A	203100787	200672878	0	0
SrcAckBusyChk_A	150427568	28896	0	0
SrcBusyKnown_A	150427568	147628522	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	152462	0	0
T1	0	1933	0	0
T2	0	3580	0	0
T3	0	185	0	0
T4	15386	116	0	0
T5	6075	48	0	0
T6	0	422	0	0
T7	32153	45	0	0
T9	1190	0	0	0
T12	0	4519	0	0
T25	0	146	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	55	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	203100787	200672878	0	0
T4	27353	6413	0	0
T5	22429	11287	0	0
T7	15433	15318	0	0
T8	979	932	0	0
T9	1165	1043	0	0
T28	882	774	0	0
T29	1950	1869	0	0
T30	1038	923	0	0
T31	877	776	0	0
T32	999	891	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	28896	0	0
T1	0	241	0	0
T2	0	431	0	0
T3	0	24	0	0
T4	15386	30	0	0
T5	6075	20	0	0
T6	0	45	0	0
T7	32153	6	0	0
T9	1190	0	0	0
T12	0	753	0	0
T25	0	18	0	0
T28	1819	0	0	0
T29	2031	0	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T35	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	147628522	0	0
T4	15386	3607	0	0
T5	6075	3057	0	0
T7	32153	31913	0	0
T8	1957	1863	0	0
T9	1190	1065	0	0
T28	1819	1595	0	0
T29	2031	1946	0	0
T30	2120	1884	0	0
T31	1835	1634	0	0
T32	1041	928	0	0