Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	967391	0	0
SrcPulseCheck_M	2147483647	962339	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	967391
T1	3719115	9877
T2	0	1684
T3	0	156
T4	228352	154
T5	382350	484
T6	18478	30
T7	40449	0
T10	0	72
T11	0	1391
T12	0	2706
T13	0	4366
T17	15074	0
T18	10411	0
T19	41977	0
T20	12657	0
T21	13910	0
T22	40895	0
T26	0	794
T52	12373	1
T53	9787	2
T57	11406	1
T59	4969	1
T74	6352	4
T104	9778	1
T105	8662	3
T106	10408	1
T107	2989	4
T108	12613	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	962339
T1	2576511	9878
T2	0	1684
T3	0	156
T4	57027	154
T5	106595	484
T6	17381	30
T7	10232	0
T10	0	72
T11	0	1391
T12	0	2706
T13	0	4366
T17	6119	0
T18	6168	0
T19	13479	0
T20	5274	0
T21	4506	0
T22	4280	0
T26	0	794
T52	11082	1
T53	3958	2
T57	4620	1
T59	4648	1
T74	11480	4
T104	4139	1
T105	7527	3
T106	4398	1
T107	5571	4
T108	12216	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	598771328	25295	0	0
SrcPulseCheck_M	158547154	25295	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	598771328	25295
T1	909800	433
T2	0	80
T3	0	12
T4	56546	10
T5	91382	20
T6	20848	6
T7	9763	0
T10	0	6
T11	0	88
T12	0	138
T17	3314	0
T18	2137	0
T19	9622	0
T20	2936	0
T21	3473	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	158547154	25295
T1	230953	433
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	6
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	598771328	31134	0	0
SrcPulseCheck_M	158547154	31154	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	598771328	31134
T1	909800	439
T2	0	80
T3	0	12
T4	56546	10
T5	91382	20
T6	20848	12
T7	9763	0
T10	0	6
T11	0	88
T12	0	138
T17	3314	0
T18	2137	0
T19	9622	0
T20	2936	0
T21	3473	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	158547154	31154
T1	230953	439
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	12
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	31123	0	0
SrcPulseCheck_M	598771328	31136	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	31123
T1	230953	439
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	12
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	598771328	31136
T1	909800	439
T2	0	80
T3	0	12
T4	56546	10
T5	91382	20
T6	20848	12
T7	9763	0
T10	0	6
T11	0	88
T12	0	138
T17	3314	0
T18	2137	0
T19	9622	0
T20	2936	0
T21	3473	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	298641222	25295	0	0
SrcPulseCheck_M	158547154	25295	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	298641222	25295
T1	454921	433
T2	0	80
T3	0	12
T4	28219	10
T5	45637	20
T6	6525	6
T7	4848	0
T10	0	6
T11	0	88
T12	0	138
T17	1911	0
T18	1092	0
T19	5665	0
T20	1484	0
T21	1690	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	158547154	25295
T1	230953	433
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	6
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	298641222	31313	0	0
SrcPulseCheck_M	158547154	31347	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	298641222	31313
T1	454921	439
T2	0	80
T3	0	12
T4	28219	10
T5	45637	20
T6	6525	12
T7	4848	0
T10	0	6
T11	0	88
T12	0	138
T17	1911	0
T18	1092	0
T19	5665	0
T20	1484	0
T21	1690	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	158547154	31347
T1	230953	439
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	12
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	31309	0	0
SrcPulseCheck_M	298641222	31318	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	31309
T1	230953	439
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	12
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	298641222	31318
T1	454921	439
T2	0	80
T3	0	12
T4	28219	10
T5	45637	20
T6	6525	12
T7	4848	0
T10	0	6
T11	0	88
T12	0	138
T17	1911	0
T18	1092	0
T19	5665	0
T20	1484	0
T21	1690	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	149319939	25295	0	0
SrcPulseCheck_M	158547154	25295	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	149319939	25295
T1	227460	433
T2	0	80
T3	0	12
T4	14110	10
T5	22819	20
T6	3262	6
T7	2424	0
T10	0	6
T11	0	88
T12	0	138
T17	953	0
T18	546	0
T19	2831	0
T20	741	0
T21	845	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	158547154	25295
T1	230953	433
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	6
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	149319939	31253	0	0
SrcPulseCheck_M	158547154	31282	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	149319939	31253
T1	227460	439
T2	0	80
T3	0	12
T4	14110	10
T5	22819	20
T6	3262	12
T7	2424	0
T10	0	6
T11	0	88
T12	0	138
T17	953	0
T18	546	0
T19	2831	0
T20	741	0
T21	845	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	158547154	31282
T1	230953	439
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	12
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	31251	0	0
SrcPulseCheck_M	149319939	31255	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	31251
T1	230953	439
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	12
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	149319939	31255
T1	227460	439
T2	0	80
T3	0	12
T4	14110	10
T5	22819	20
T6	3262	12
T7	2424	0
T10	0	6
T11	0	88
T12	0	138
T17	953	0
T18	546	0
T19	2831	0
T20	741	0
T21	845	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	634474150	25295	0	0
SrcPulseCheck_M	158547154	25295	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	634474150	25295
T1	986139	433
T2	0	80
T3	0	12
T4	58903	10
T5	101193	20
T6	21717	6
T7	13010	0
T10	0	6
T11	0	88
T12	0	138
T17	3452	0
T18	2226	0
T19	10024	0
T20	3059	0
T21	3618	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	158547154	25295
T1	230953	433
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	6
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	634474150	31186	0	0
SrcPulseCheck_M	158547154	31211	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	634474150	31186
T1	986139	439
T2	0	80
T3	0	12
T4	58903	10
T5	101193	20
T6	21717	12
T7	13010	0
T10	0	6
T11	0	88
T12	0	138
T17	3452	0
T18	2226	0
T19	10024	0
T20	3059	0
T21	3618	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	158547154	31211
T1	230953	439
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	12
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	31178	0	0
SrcPulseCheck_M	634474150	31194	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	31178
T1	230953	439
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	12
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	634474150	31194
T1	986139	439
T2	0	80
T3	0	12
T4	58903	10
T5	101193	20
T6	21717	12
T7	13010	0
T10	0	6
T11	0	88
T12	0	138
T17	3452	0
T18	2226	0
T19	10024	0
T20	3059	0
T21	3618	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	304562291	24841	0	0
SrcPulseCheck_M	158547154	25295	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	304562291	24841
T1	473642	433
T2	0	80
T3	0	12
T4	28274	10
T5	57213	20
T6	10424	6
T7	5966	0
T10	0	6
T11	0	88
T12	0	138
T17	1657	0
T18	1069	0
T19	4812	0
T20	1469	0
T21	1737	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	158547154	25295
T1	230953	433
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	6
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	304562291	30987	0	0
SrcPulseCheck_M	158547154	31177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	304562291	30987
T1	473642	439
T2	0	80
T3	0	12
T4	28274	10
T5	57213	20
T6	10424	12
T7	5966	0
T10	0	6
T11	0	88
T12	0	138
T17	1657	0
T18	1069	0
T19	4812	0
T20	1469	0
T21	1737	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	158547154	31177
T1	230953	439
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	12
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T4
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	30832	0	0
SrcPulseCheck_M	304562291	31032	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	30832
T1	230953	439
T2	0	80
T3	0	12
T4	14136	10
T5	30045	20
T6	5428	12
T7	708	0
T10	0	6
T11	0	88
T12	0	138
T17	1622	0
T18	2226	0
T19	2505	0
T20	1469	0
T21	904	0
T26	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	304562291	31032
T1	473642	439
T2	0	80
T3	0	12
T4	28274	10
T5	57213	20
T6	10424	12
T7	5966	0
T10	0	6
T11	0	88
T12	0	138
T17	1657	0
T18	1069	0
T19	4812	0
T20	1469	0
T21	1737	0
T26	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T54,T55
1	0	Covered	T52,T54,T55
1	1	Covered	T59,T109

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T54,T55
1	0	Covered	T59,T109
1	1	Covered	T52,T54,T55

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	29	0	0
SrcPulseCheck_M	598771328	29	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	29
T52	12373	2
T54	4804	1
T55	3213	1
T57	11406	1
T59	4969	2
T104	9778	2
T107	2989	1
T108	12613	1
T110	11307	2
T111	5266	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	598771328	29
T52	23754	2
T54	19214	1
T55	12340	1
T57	11172	1
T59	10151	2
T104	9676	2
T107	11954	1
T108	25763	1
T110	11307	2
T111	21064	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T54,T55
1	0	Covered	T52,T54,T55
1	1	Covered	T54,T109

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T54,T55
1	0	Covered	T54,T109
1	1	Covered	T52,T54,T55

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	29	0	0
SrcPulseCheck_M	598771328	29	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	29
T52	12373	2
T54	4804	2
T55	3213	1
T59	4969	1
T74	6352	2
T104	9778	1
T107	2989	1
T108	12613	1
T110	11307	1
T111	5266	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	598771328	29
T52	23754	2
T54	19214	2
T55	12340	1
T59	10151	1
T74	24391	2
T104	9676	1
T107	11954	1
T108	25763	1
T110	11307	1
T111	21064	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T53,T59
1	0	Covered	T52,T53,T59
1	1	Covered	T74,T105,T107

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T53,T59
1	0	Covered	T74,T105,T107
1	1	Covered	T52,T53,T59

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	35	0	0
SrcPulseCheck_M	298641222	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	35
T52	12373	1
T53	9787	2
T57	11406	1
T59	4969	1
T74	6352	4
T104	9778	1
T105	8662	3
T106	10408	1
T107	2989	4
T108	12613	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	298641222	35
T52	11082	1
T53	3958	2
T57	4620	1
T59	4648	1
T74	11480	4
T104	4139	1
T105	7527	3
T106	4398	1
T107	5571	4
T108	12216	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T53,T58
1	0	Covered	T52,T53,T58
1	1	Covered	T112,T113,T114

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T53,T58
1	0	Covered	T112,T113,T114
1	1	Covered	T52,T53,T58

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	32	0	0
SrcPulseCheck_M	298641222	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	32
T52	12373	1
T53	9787	1
T57	11406	1
T58	9925	1
T59	4969	1
T74	6352	2
T104	9778	1
T106	10408	1
T108	12613	1
T111	5266	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	298641222	32
T52	11082	1
T53	3958	1
T57	4620	1
T58	3952	1
T59	4648	1
T74	11480	2
T104	4139	1
T106	4398	1
T108	12216	1
T111	10179	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T53,T54
1	0	Covered	T52,T53,T54
1	1	Covered	T105

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T53,T54
1	0	Covered	T105
1	1	Covered	T52,T53,T54

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	32	0	0
SrcPulseCheck_M	149319939	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	32
T52	12373	2
T53	9787	1
T54	4804	2
T74	6352	1
T104	9778	1
T105	8662	2
T106	10408	1
T108	12613	1
T110	11307	2
T111	5266	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	149319939	32
T52	5541	2
T53	1979	1
T54	4573	2
T74	5740	1
T104	2070	1
T105	3763	2
T106	2200	1
T108	6107	1
T110	2397	2
T111	5089	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T53,T54
1	0	Covered	T52,T53,T54
1	1	Covered	T109,T112,T115

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T53,T54
1	0	Covered	T109,T112,T115
1	1	Covered	T52,T53,T54

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	37	0	0
SrcPulseCheck_M	149319939	37	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	37
T52	12373	1
T53	9787	1
T54	4804	2
T56	18634	1
T74	6352	1
T105	8662	1
T107	2989	1
T110	11307	2
T111	5266	1
T116	10273	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	149319939	37
T52	5541	1
T53	1979	1
T54	4573	2
T56	4169	1
T74	5740	1
T105	3763	1
T107	2785	1
T110	2397	2
T111	5089	1
T116	2111	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T53,T58
1	0	Covered	T52,T53,T58
1	1	Covered	T53,T117,T113

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T53,T58
1	0	Covered	T53,T117,T113
1	1	Covered	T52,T53,T58

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	32	0	0
SrcPulseCheck_M	634474150	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	32
T52	12373	1
T53	9787	2
T55	3213	1
T56	18634	2
T57	11406	1
T58	9925	1
T104	9778	1
T107	2989	1
T110	11307	1
T118	10158	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	634474150	32
T52	24745	1
T53	10302	2
T55	12855	1
T56	19411	2
T57	11638	1
T58	9925	1
T104	10080	1
T107	12453	1
T110	11779	1
T118	40635	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T53,T58
1	0	Covered	T52,T53,T58
1	1	Covered	T53,T58,T119

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T52,T53,T58
1	0	Covered	T53,T58,T119
1	1	Covered	T52,T53,T58

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	40	0	0
SrcPulseCheck_M	634474150	40	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	40
T52	12373	1
T53	9787	2
T55	3213	2
T56	18634	1
T57	11406	2
T58	9925	2
T59	4969	1
T74	6352	1
T105	8662	1
T110	11307	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	634474150	40
T52	24745	1
T53	10302	2
T55	12855	2
T56	19411	1
T57	11638	2
T58	9925	2
T59	10574	1
T74	25409	1
T105	17324	1
T110	11779	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T53,T56,T59
1	0	Covered	T53,T56,T59
1	1	Covered	T105,T120

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T53,T56,T59
1	0	Covered	T105,T120
1	1	Covered	T53,T56,T59

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	34	0	0
SrcPulseCheck_M	304562291	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	34
T53	9787	1
T56	18634	2
T59	4969	1
T74	6352	1
T104	9778	1
T105	8662	3
T106	10408	2
T110	11307	1
T118	10158	2
T121	15353	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	304562291	34
T53	4945	1
T56	9317	2
T59	5075	1
T74	12196	1
T104	4838	1
T105	8316	3
T106	5204	2
T110	5654	1
T118	19504	2
T121	7444	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T53,T58,T56
1	0	Covered	T53,T58,T56
1	1	Covered	T59,T105,T112

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T53,T58,T56
1	0	Covered	T59,T105,T112
1	1	Covered	T53,T58,T56

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	158547154	36	0	0
SrcPulseCheck_M	304562291	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	158547154	36
T53	9787	2
T56	18634	1
T58	9925	1
T59	4969	2
T104	9778	1
T105	8662	3
T106	10408	2
T110	11307	1
T116	10273	2
T118	10158	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	304562291	36
T53	4945	2
T56	9317	1
T58	4764	1
T59	5075	2
T104	4838	1
T105	8316	3
T106	5204	2
T110	5654	1
T116	5083	2
T118	19504	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	595862208	101107	0	0
SrcPulseCheck_M	19533033	99724	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	595862208	101107
T1	909800	1950
T2	0	369
T3	0	30
T4	56546	31
T5	91382	103
T7	9763	0
T10	0	14
T11	0	273
T12	0	537
T13	0	1228
T17	3314	0
T18	2137	0
T19	9622	0
T20	2936	0
T21	3473	0
T22	14677	0
T26	0	185

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	19533033	99724
T1	414729	1950
T2	0	369
T3	0	30
T4	134	31
T5	214	103
T7	992	0
T10	0	14
T11	0	273
T12	0	537
T13	0	1228
T17	241	0
T18	156	0
T19	701	0
T20	213	0
T21	252	0
T22	1070	0
T26	0	185

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	297233686	99549	0	0
SrcPulseCheck_M	19533033	98189	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	297233686	99549
T1	454921	1950
T2	0	350
T3	0	30
T4	28219	31
T5	45637	103
T7	4848	0
T10	0	14
T11	0	273
T12	0	537
T13	0	1131
T17	1911	0
T18	1092	0
T19	5665	0
T20	1484	0
T21	1690	0
T22	7285	0
T26	0	185

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	19533033	98189
T1	414729	1950
T2	0	350
T3	0	30
T4	134	31
T5	214	103
T7	992	0
T10	0	14
T11	0	273
T12	0	537
T13	0	1131
T17	241	0
T18	156	0
T19	701	0
T20	213	0
T21	252	0
T22	1070	0
T26	0	185

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	148616179	97511	0	0
SrcPulseCheck_M	19533033	96181	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	148616179	97511
T1	227460	1949
T2	0	329
T3	0	30
T4	14110	31
T5	22819	103
T7	2424	0
T10	0	14
T11	0	270
T12	0	537
T13	0	1032
T17	953	0
T18	546	0
T19	2831	0
T20	741	0
T21	845	0
T22	3643	0
T26	0	185

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	19533033	96181
T1	414729	1949
T2	0	329
T3	0	30
T4	134	31
T5	214	103
T7	992	0
T10	0	14
T11	0	270
T12	0	537
T13	0	1032
T17	241	0
T18	156	0
T19	701	0
T20	213	0
T21	252	0
T22	1070	0
T26	0	185

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	631443680	116778	0	0
SrcPulseCheck_M	19910688	116345	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	631443680	116778
T1	986139	2717
T2	0	396
T3	0	30
T4	58903	31
T5	101193	115
T7	13010	0
T10	0	12
T11	0	311
T12	0	681
T13	0	975
T17	3452	0
T18	2226	0
T19	10024	0
T20	3059	0
T21	3618	0
T22	15290	0
T26	0	161

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	19910688	116345
T1	415497	2718
T2	0	396
T3	0	30
T4	134	31
T5	226	115
T7	992	0
T10	0	12
T11	0	311
T12	0	681
T13	0	975
T17	241	0
T18	156	0
T19	701	0
T20	213	0
T21	252	0
T22	1070	0
T26	0	161

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T7
0	Covered	T6,T1,T7

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	303107690	114523	0	0
SrcPulseCheck_M	19849572	112983	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	303107690	114523
T1	473642	2725
T2	0	389
T3	0	30
T4	28274	29
T5	57213	148
T7	5966	0
T10	0	12
T11	0	295
T12	0	657
T13	0	906
T17	1657	0
T18	1069	0
T19	4812	0
T20	1469	0
T21	1737	0
T22	7339	0
T26	0	149

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	19849572	112983
T1	415509	2725
T2	0	389
T3	0	30
T4	134	29
T5	262	148
T7	992	0
T10	0	12
T11	0	295
T12	0	657
T13	0	907
T17	241	0
T18	156	0
T19	701	0
T20	213	0
T21	252	0
T22	1070	0
T26	0	149

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb