Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T13
1	0	Covered	T6,T1,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1585471540	1340454	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1585471540	281699	0	0
SrcBusyKnown_A	1585471540	1560432360	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585471540	1340454	0	0
T1	2309530	14658	0	0
T2	0	2077	0	0
T3	0	549	0	0
T4	141360	340	0	0
T5	300450	704	0	0
T6	54280	321	0	0
T7	7080	0	0	0
T10	0	197	0	0
T11	0	2916	0	0
T12	0	8127	0	0
T17	16220	0	0	0
T18	22260	0	0	0
T19	25050	0	0	0
T20	14690	0	0	0
T21	9040	0	0	0
T26	0	1280	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6103924	6099242	0	0
T4	372104	371198	0	0
T5	636488	635130	0	0
T6	125552	59800	0	0
T7	72022	71414	0	0
T17	22574	21688	0	0
T18	14140	12920	0	0
T19	65908	65320	0	0
T20	19378	17996	0	0
T21	22726	21524	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585471540	281699	0	0
T1	2309530	4360	0	0
T2	0	800	0	0
T3	0	120	0	0
T4	141360	100	0	0
T5	300450	200	0	0
T6	54280	90	0	0
T7	7080	0	0	0
T10	0	60	0	0
T11	0	880	0	0
T12	0	1380	0	0
T17	16220	0	0	0
T18	22260	0	0	0
T19	25050	0	0	0
T20	14690	0	0	0
T21	9040	0	0	0
T26	0	260	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585471540	1560432360	0	0
T1	2309530	2307560	0	0
T4	141360	140960	0	0
T5	300450	299880	0	0
T6	54280	23680	0	0
T7	7080	7020	0	0
T17	16220	15430	0	0
T18	22260	20140	0	0
T19	25050	24780	0	0
T20	14690	13530	0	0
T21	9040	8510	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158547154	84018	0	0
DstReqKnown_A	598771328	594078918	0	0
SrcAckBusyChk_A	158547154	25295	0	0
SrcBusyKnown_A	158547154	156043236	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	84018	0	0
T1	230953	1084	0	0
T2	0	203	0	0
T3	0	39	0	0
T4	14136	25	0	0
T5	30045	52	0	0
T6	5428	16	0	0
T7	708	0	0	0
T10	0	16	0	0
T11	0	220	0	0
T12	0	543	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	91	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598771328	594078918	0	0
T1	909800	908978	0	0
T4	56546	56384	0	0
T5	91382	91151	0	0
T6	20848	9083	0	0
T7	9763	9655	0	0
T17	3314	3152	0	0
T18	2137	1934	0	0
T19	9622	9515	0	0
T20	2936	2705	0	0
T21	3473	3269	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	25295	0	0
T1	230953	433	0	0
T2	0	80	0	0
T3	0	12	0	0
T4	14136	10	0	0
T5	30045	20	0	0
T6	5428	6	0	0
T7	708	0	0	0
T10	0	6	0	0
T11	0	88	0	0
T12	0	138	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	156043236	0	0
T1	230953	230756	0	0
T4	14136	14096	0	0
T5	30045	29988	0	0
T6	5428	2368	0	0
T7	708	702	0	0
T17	1622	1543	0	0
T18	2226	2014	0	0
T19	2505	2478	0	0
T20	1469	1353	0	0
T21	904	851	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158547154	119001	0	0
DstReqKnown_A	298641222	297462432	0	0
SrcAckBusyChk_A	158547154	25295	0	0
SrcBusyKnown_A	158547154	156043236	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	119001	0	0
T1	230953	1498	0	0
T2	0	203	0	0
T3	0	54	0	0
T4	14136	35	0	0
T5	30045	72	0	0
T6	5428	23	0	0
T7	708	0	0	0
T10	0	21	0	0
T11	0	306	0	0
T12	0	817	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	127	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298641222	297462432	0	0
T1	454921	454716	0	0
T4	28219	28192	0	0
T5	45637	45575	0	0
T6	6525	4543	0	0
T7	4848	4827	0	0
T17	1911	1890	0	0
T18	1092	1030	0	0
T19	5665	5651	0	0
T20	1484	1415	0	0
T21	1690	1635	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	25295	0	0
T1	230953	433	0	0
T2	0	80	0	0
T3	0	12	0	0
T4	14136	10	0	0
T5	30045	20	0	0
T6	5428	6	0	0
T7	708	0	0	0
T10	0	6	0	0
T11	0	88	0	0
T12	0	138	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	156043236	0	0
T1	230953	230756	0	0
T4	14136	14096	0	0
T5	30045	29988	0	0
T6	5428	2368	0	0
T7	708	702	0	0
T17	1622	1543	0	0
T18	2226	2014	0	0
T19	2505	2478	0	0
T20	1469	1353	0	0
T21	904	851	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158547154	185418	0	0
DstReqKnown_A	149319939	148730663	0	0
SrcAckBusyChk_A	158547154	25295	0	0
SrcBusyKnown_A	158547154	156043236	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	185418	0	0
T1	230953	2117	0	0
T2	0	226	0	0
T3	0	89	0	0
T4	14136	50	0	0
T5	30045	104	0	0
T6	5428	36	0	0
T7	708	0	0	0
T10	0	27	0	0
T11	0	418	0	0
T12	0	1356	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	206	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149319939	148730663	0	0
T1	227460	227357	0	0
T4	14110	14096	0	0
T5	22819	22788	0	0
T6	3262	2271	0	0
T7	2424	2414	0	0
T17	953	943	0	0
T18	546	515	0	0
T19	2831	2824	0	0
T20	741	706	0	0
T21	845	817	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	25295	0	0
T1	230953	433	0	0
T2	0	80	0	0
T3	0	12	0	0
T4	14136	10	0	0
T5	30045	20	0	0
T6	5428	6	0	0
T7	708	0	0	0
T10	0	6	0	0
T11	0	88	0	0
T12	0	138	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	156043236	0	0
T1	230953	230756	0	0
T4	14136	14096	0	0
T5	30045	29988	0	0
T6	5428	2368	0	0
T7	708	702	0	0
T17	1622	1543	0	0
T18	2226	2014	0	0
T19	2505	2478	0	0
T20	1469	1353	0	0
T21	904	851	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158547154	82880	0	0
DstReqKnown_A	634474150	629534386	0	0
SrcAckBusyChk_A	158547154	25295	0	0
SrcBusyKnown_A	158547154	156043236	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	82880	0	0
T1	230953	1084	0	0
T2	0	203	0	0
T3	0	39	0	0
T4	14136	25	0	0
T5	30045	52	0	0
T6	5428	16	0	0
T7	708	0	0	0
T10	0	16	0	0
T11	0	220	0	0
T12	0	530	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	89	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634474150	629534386	0	0
T1	986139	985339	0	0
T4	58903	58734	0	0
T5	101193	100953	0	0
T6	21717	9462	0	0
T7	13010	12898	0	0
T17	3452	3283	0	0
T18	2226	2014	0	0
T19	10024	9912	0	0
T20	3059	2819	0	0
T21	3618	3406	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	25295	0	0
T1	230953	433	0	0
T2	0	80	0	0
T3	0	12	0	0
T4	14136	10	0	0
T5	30045	20	0	0
T6	5428	6	0	0
T7	708	0	0	0
T10	0	6	0	0
T11	0	88	0	0
T12	0	138	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	156043236	0	0
T1	230953	230756	0	0
T4	14136	14096	0	0
T5	30045	29988	0	0
T6	5428	2368	0	0
T7	708	702	0	0
T17	1622	1543	0	0
T18	2226	2014	0	0
T19	2505	2478	0	0
T20	1469	1353	0	0
T21	904	851	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158547154	117464	0	0
DstReqKnown_A	304562291	302200349	0	0
SrcAckBusyChk_A	158547154	24790	0	0
SrcBusyKnown_A	158547154	156043236	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	117464	0	0
T1	230953	1495	0	0
T2	0	203	0	0
T3	0	55	0	0
T4	14136	35	0	0
T5	30045	72	0	0
T6	5428	23	0	0
T7	708	0	0	0
T10	0	20	0	0
T11	0	300	0	0
T12	0	805	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	129	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304562291	302200349	0	0
T1	473642	473231	0	0
T4	28274	28193	0	0
T5	57213	57098	0	0
T6	10424	4541	0	0
T7	5966	5913	0	0
T17	1657	1576	0	0
T18	1069	967	0	0
T19	4812	4758	0	0
T20	1469	1353	0	0
T21	1737	1635	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	24790	0	0
T1	230953	433	0	0
T2	0	80	0	0
T3	0	12	0	0
T4	14136	10	0	0
T5	30045	20	0	0
T6	5428	6	0	0
T7	708	0	0	0
T10	0	6	0	0
T11	0	88	0	0
T12	0	138	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	156043236	0	0
T1	230953	230756	0	0
T4	14136	14096	0	0
T5	30045	29988	0	0
T6	5428	2368	0	0
T7	708	702	0	0
T17	1622	1543	0	0
T18	2226	2014	0	0
T19	2505	2478	0	0
T20	1469	1353	0	0
T21	904	851	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T13
1	0	Covered	T6,T1,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158547154	106119	0	0
DstReqKnown_A	598771328	594078918	0	0
SrcAckBusyChk_A	158547154	31125	0	0
SrcBusyKnown_A	158547154	156043236	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	106119	0	0
T1	230953	1098	0	0
T2	0	203	0	0
T3	0	40	0	0
T4	14136	25	0	0
T5	30045	52	0	0
T6	5428	30	0	0
T7	708	0	0	0
T10	0	15	0	0
T11	0	218	0	0
T12	0	540	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	89	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598771328	594078918	0	0
T1	909800	908978	0	0
T4	56546	56384	0	0
T5	91382	91151	0	0
T6	20848	9083	0	0
T7	9763	9655	0	0
T17	3314	3152	0	0
T18	2137	1934	0	0
T19	9622	9515	0	0
T20	2936	2705	0	0
T21	3473	3269	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	31125	0	0
T1	230953	439	0	0
T2	0	80	0	0
T3	0	12	0	0
T4	14136	10	0	0
T5	30045	20	0	0
T6	5428	12	0	0
T7	708	0	0	0
T10	0	6	0	0
T11	0	88	0	0
T12	0	138	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	156043236	0	0
T1	230953	230756	0	0
T4	14136	14096	0	0
T5	30045	29988	0	0
T6	5428	2368	0	0
T7	708	702	0	0
T17	1622	1543	0	0
T18	2226	2014	0	0
T19	2505	2478	0	0
T20	1469	1353	0	0
T21	904	851	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T13
1	0	Covered	T6,T1,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158547154	151375	0	0
DstReqKnown_A	298641222	297462432	0	0
SrcAckBusyChk_A	158547154	31310	0	0
SrcBusyKnown_A	158547154	156043236	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	151375	0	0
T1	230953	1518	0	0
T2	0	203	0	0
T3	0	54	0	0
T4	14136	35	0	0
T5	30045	72	0	0
T6	5428	43	0	0
T7	708	0	0	0
T10	0	19	0	0
T11	0	298	0	0
T12	0	825	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	128	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298641222	297462432	0	0
T1	454921	454716	0	0
T4	28219	28192	0	0
T5	45637	45575	0	0
T6	6525	4543	0	0
T7	4848	4827	0	0
T17	1911	1890	0	0
T18	1092	1030	0	0
T19	5665	5651	0	0
T20	1484	1415	0	0
T21	1690	1635	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	31310	0	0
T1	230953	439	0	0
T2	0	80	0	0
T3	0	12	0	0
T4	14136	10	0	0
T5	30045	20	0	0
T6	5428	12	0	0
T7	708	0	0	0
T10	0	6	0	0
T11	0	88	0	0
T12	0	138	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	156043236	0	0
T1	230953	230756	0	0
T4	14136	14096	0	0
T5	30045	29988	0	0
T6	5428	2368	0	0
T7	708	702	0	0
T17	1622	1543	0	0
T18	2226	2014	0	0
T19	2505	2478	0	0
T20	1469	1353	0	0
T21	904	851	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T13
1	0	Covered	T6,T1,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158547154	238706	0	0
DstReqKnown_A	149319939	148730663	0	0
SrcAckBusyChk_A	158547154	31251	0	0
SrcBusyKnown_A	158547154	156043236	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	238706	0	0
T1	230953	2143	0	0
T2	0	227	0	0
T3	0	85	0	0
T4	14136	50	0	0
T5	30045	104	0	0
T6	5428	62	0	0
T7	708	0	0	0
T10	0	29	0	0
T11	0	423	0	0
T12	0	1363	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	205	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149319939	148730663	0	0
T1	227460	227357	0	0
T4	14110	14096	0	0
T5	22819	22788	0	0
T6	3262	2271	0	0
T7	2424	2414	0	0
T17	953	943	0	0
T18	546	515	0	0
T19	2831	2824	0	0
T20	741	706	0	0
T21	845	817	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	31251	0	0
T1	230953	439	0	0
T2	0	80	0	0
T3	0	12	0	0
T4	14136	10	0	0
T5	30045	20	0	0
T6	5428	12	0	0
T7	708	0	0	0
T10	0	6	0	0
T11	0	88	0	0
T12	0	138	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	156043236	0	0
T1	230953	230756	0	0
T4	14136	14096	0	0
T5	30045	29988	0	0
T6	5428	2368	0	0
T7	708	702	0	0
T17	1622	1543	0	0
T18	2226	2014	0	0
T19	2505	2478	0	0
T20	1469	1353	0	0
T21	904	851	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T13
1	0	Covered	T6,T1,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158547154	104648	0	0
DstReqKnown_A	634474150	629534386	0	0
SrcAckBusyChk_A	158547154	31181	0	0
SrcBusyKnown_A	158547154	156043236	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	104648	0	0
T1	230953	1098	0	0
T2	0	203	0	0
T3	0	39	0	0
T4	14136	25	0	0
T5	30045	52	0	0
T6	5428	30	0	0
T7	708	0	0	0
T10	0	15	0	0
T11	0	218	0	0
T12	0	534	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	89	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634474150	629534386	0	0
T1	986139	985339	0	0
T4	58903	58734	0	0
T5	101193	100953	0	0
T6	21717	9462	0	0
T7	13010	12898	0	0
T17	3452	3283	0	0
T18	2226	2014	0	0
T19	10024	9912	0	0
T20	3059	2819	0	0
T21	3618	3406	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	31181	0	0
T1	230953	439	0	0
T2	0	80	0	0
T3	0	12	0	0
T4	14136	10	0	0
T5	30045	20	0	0
T6	5428	12	0	0
T7	708	0	0	0
T10	0	6	0	0
T11	0	88	0	0
T12	0	138	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	156043236	0	0
T1	230953	230756	0	0
T4	14136	14096	0	0
T5	30045	29988	0	0
T6	5428	2368	0	0
T7	708	702	0	0
T17	1622	1543	0	0
T18	2226	2014	0	0
T19	2505	2478	0	0
T20	1469	1353	0	0
T21	904	851	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T6,T1,T13
1	0	Covered	T6,T1,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T4
1	1	Covered	T6,T1,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T4
0	0	1	Covered	T6,T1,T4
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158547154	150825	0	0
DstReqKnown_A	304562291	302200349	0	0
SrcAckBusyChk_A	158547154	30862	0	0
SrcBusyKnown_A	158547154	156043236	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	150825	0	0
T1	230953	1523	0	0
T2	0	203	0	0
T3	0	55	0	0
T4	14136	35	0	0
T5	30045	72	0	0
T6	5428	42	0	0
T7	708	0	0	0
T10	0	19	0	0
T11	0	295	0	0
T12	0	814	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	127	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304562291	302200349	0	0
T1	473642	473231	0	0
T4	28274	28193	0	0
T5	57213	57098	0	0
T6	10424	4541	0	0
T7	5966	5913	0	0
T17	1657	1576	0	0
T18	1069	967	0	0
T19	4812	4758	0	0
T20	1469	1353	0	0
T21	1737	1635	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	30862	0	0
T1	230953	439	0	0
T2	0	80	0	0
T3	0	12	0	0
T4	14136	10	0	0
T5	30045	20	0	0
T6	5428	12	0	0
T7	708	0	0	0
T10	0	6	0	0
T11	0	88	0	0
T12	0	138	0	0
T17	1622	0	0	0
T18	2226	0	0	0
T19	2505	0	0	0
T20	1469	0	0	0
T21	904	0	0	0
T26	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158547154	156043236	0	0
T1	230953	230756	0	0
T4	14136	14096	0	0
T5	30045	29988	0	0
T6	5428	2368	0	0
T7	708	702	0	0
T17	1622	1543	0	0
T18	2226	2014	0	0
T19	2505	2478	0	0
T20	1469	1353	0	0
T21	904	851	0	0