Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
957295 |
0 |
0 |
T1 |
425826 |
196 |
0 |
0 |
T2 |
191050 |
66 |
0 |
0 |
T3 |
308157 |
144 |
0 |
0 |
T4 |
151914 |
60 |
0 |
0 |
T8 |
0 |
130 |
0 |
0 |
T11 |
0 |
5107 |
0 |
0 |
T12 |
0 |
1362 |
0 |
0 |
T13 |
0 |
7444 |
0 |
0 |
T18 |
7485 |
0 |
0 |
0 |
T19 |
882717 |
950 |
0 |
0 |
T20 |
17752 |
0 |
0 |
0 |
T21 |
6960 |
0 |
0 |
0 |
T22 |
15941 |
0 |
0 |
0 |
T23 |
6926 |
0 |
0 |
0 |
T32 |
0 |
194 |
0 |
0 |
T33 |
0 |
80 |
0 |
0 |
T50 |
27578 |
2 |
0 |
0 |
T53 |
23098 |
2 |
0 |
0 |
T55 |
7803 |
1 |
0 |
0 |
T56 |
2493 |
0 |
0 |
0 |
T57 |
13048 |
1 |
0 |
0 |
T62 |
0 |
676 |
0 |
0 |
T63 |
0 |
888 |
0 |
0 |
T104 |
10546 |
1 |
0 |
0 |
T105 |
7751 |
1 |
0 |
0 |
T106 |
11850 |
1 |
0 |
0 |
T107 |
19908 |
2 |
0 |
0 |
T108 |
9226 |
0 |
0 |
0 |
T109 |
26604 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
952248 |
0 |
0 |
T1 |
225665 |
196 |
0 |
0 |
T2 |
64551 |
66 |
0 |
0 |
T3 |
156379 |
144 |
0 |
0 |
T4 |
37994 |
60 |
0 |
0 |
T8 |
0 |
130 |
0 |
0 |
T11 |
0 |
4704 |
0 |
0 |
T12 |
0 |
1362 |
0 |
0 |
T13 |
0 |
7444 |
0 |
0 |
T18 |
4398 |
0 |
0 |
0 |
T19 |
532003 |
950 |
0 |
0 |
T20 |
5669 |
0 |
0 |
0 |
T21 |
4331 |
0 |
0 |
0 |
T22 |
6743 |
0 |
0 |
0 |
T23 |
4147 |
0 |
0 |
0 |
T32 |
0 |
194 |
0 |
0 |
T33 |
0 |
80 |
0 |
0 |
T50 |
12164 |
2 |
0 |
0 |
T53 |
18494 |
2 |
0 |
0 |
T55 |
14694 |
1 |
0 |
0 |
T56 |
4088 |
0 |
0 |
0 |
T57 |
24940 |
1 |
0 |
0 |
T62 |
0 |
676 |
0 |
0 |
T63 |
0 |
888 |
0 |
0 |
T104 |
19198 |
1 |
0 |
0 |
T105 |
14542 |
1 |
0 |
0 |
T106 |
5320 |
1 |
0 |
0 |
T107 |
38170 |
2 |
0 |
0 |
T108 |
18850 |
0 |
0 |
0 |
T109 |
12056 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468127480 |
24937 |
0 |
0 |
T1 |
88491 |
16 |
0 |
0 |
T2 |
44819 |
6 |
0 |
0 |
T3 |
65026 |
12 |
0 |
0 |
T4 |
42728 |
12 |
0 |
0 |
T8 |
0 |
26 |
0 |
0 |
T11 |
0 |
255 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1569 |
0 |
0 |
0 |
T19 |
164283 |
38 |
0 |
0 |
T20 |
4403 |
0 |
0 |
0 |
T21 |
1465 |
0 |
0 |
0 |
T22 |
3754 |
0 |
0 |
0 |
T23 |
1451 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
16 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
24937 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
12 |
0 |
0 |
T8 |
0 |
26 |
0 |
0 |
T11 |
0 |
255 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468127480 |
30966 |
0 |
0 |
T1 |
88491 |
16 |
0 |
0 |
T2 |
44819 |
6 |
0 |
0 |
T3 |
65026 |
12 |
0 |
0 |
T4 |
42728 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1569 |
0 |
0 |
0 |
T19 |
164283 |
38 |
0 |
0 |
T20 |
4403 |
0 |
0 |
0 |
T21 |
1465 |
0 |
0 |
0 |
T22 |
3754 |
0 |
0 |
0 |
T23 |
1451 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
30980 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
30951 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468127480 |
30968 |
0 |
0 |
T1 |
88491 |
16 |
0 |
0 |
T2 |
44819 |
6 |
0 |
0 |
T3 |
65026 |
12 |
0 |
0 |
T4 |
42728 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1569 |
0 |
0 |
0 |
T19 |
164283 |
38 |
0 |
0 |
T20 |
4403 |
0 |
0 |
0 |
T21 |
1465 |
0 |
0 |
0 |
T22 |
3754 |
0 |
0 |
0 |
T23 |
1451 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233316797 |
24937 |
0 |
0 |
T1 |
44233 |
16 |
0 |
0 |
T2 |
23105 |
6 |
0 |
0 |
T3 |
32501 |
12 |
0 |
0 |
T4 |
15300 |
12 |
0 |
0 |
T8 |
0 |
26 |
0 |
0 |
T11 |
0 |
255 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
770 |
0 |
0 |
0 |
T19 |
82027 |
38 |
0 |
0 |
T20 |
2189 |
0 |
0 |
0 |
T21 |
693 |
0 |
0 |
0 |
T22 |
1817 |
0 |
0 |
0 |
T23 |
701 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
16 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
24937 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
12 |
0 |
0 |
T8 |
0 |
26 |
0 |
0 |
T11 |
0 |
255 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233316797 |
30651 |
0 |
0 |
T1 |
44233 |
16 |
0 |
0 |
T2 |
23105 |
6 |
0 |
0 |
T3 |
32501 |
12 |
0 |
0 |
T4 |
15300 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
770 |
0 |
0 |
0 |
T19 |
82027 |
38 |
0 |
0 |
T20 |
2189 |
0 |
0 |
0 |
T21 |
693 |
0 |
0 |
0 |
T22 |
1817 |
0 |
0 |
0 |
T23 |
701 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
30672 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
30639 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233316797 |
30656 |
0 |
0 |
T1 |
44233 |
16 |
0 |
0 |
T2 |
23105 |
6 |
0 |
0 |
T3 |
32501 |
12 |
0 |
0 |
T4 |
15300 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
770 |
0 |
0 |
0 |
T19 |
82027 |
38 |
0 |
0 |
T20 |
2189 |
0 |
0 |
0 |
T21 |
693 |
0 |
0 |
0 |
T22 |
1817 |
0 |
0 |
0 |
T23 |
701 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116657803 |
24937 |
0 |
0 |
T1 |
22117 |
16 |
0 |
0 |
T2 |
11552 |
6 |
0 |
0 |
T3 |
16250 |
12 |
0 |
0 |
T4 |
7649 |
12 |
0 |
0 |
T8 |
0 |
26 |
0 |
0 |
T11 |
0 |
255 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
385 |
0 |
0 |
0 |
T19 |
41014 |
38 |
0 |
0 |
T20 |
1095 |
0 |
0 |
0 |
T21 |
346 |
0 |
0 |
0 |
T22 |
908 |
0 |
0 |
0 |
T23 |
350 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
16 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
24937 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
12 |
0 |
0 |
T8 |
0 |
26 |
0 |
0 |
T11 |
0 |
255 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116657803 |
30571 |
0 |
0 |
T1 |
22117 |
16 |
0 |
0 |
T2 |
11552 |
6 |
0 |
0 |
T3 |
16250 |
12 |
0 |
0 |
T4 |
7649 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
385 |
0 |
0 |
0 |
T19 |
41014 |
38 |
0 |
0 |
T20 |
1095 |
0 |
0 |
0 |
T21 |
346 |
0 |
0 |
0 |
T22 |
908 |
0 |
0 |
0 |
T23 |
350 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
30601 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
30569 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116657803 |
30576 |
0 |
0 |
T1 |
22117 |
16 |
0 |
0 |
T2 |
11552 |
6 |
0 |
0 |
T3 |
16250 |
12 |
0 |
0 |
T4 |
7649 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
385 |
0 |
0 |
0 |
T19 |
41014 |
38 |
0 |
0 |
T20 |
1095 |
0 |
0 |
0 |
T21 |
346 |
0 |
0 |
0 |
T22 |
908 |
0 |
0 |
0 |
T23 |
350 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
498849462 |
24937 |
0 |
0 |
T1 |
92181 |
16 |
0 |
0 |
T2 |
46689 |
6 |
0 |
0 |
T3 |
67737 |
12 |
0 |
0 |
T4 |
44510 |
12 |
0 |
0 |
T8 |
0 |
26 |
0 |
0 |
T11 |
0 |
255 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1635 |
0 |
0 |
0 |
T19 |
207133 |
38 |
0 |
0 |
T20 |
4587 |
0 |
0 |
0 |
T21 |
1491 |
0 |
0 |
0 |
T22 |
3911 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
16 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
24937 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
12 |
0 |
0 |
T8 |
0 |
26 |
0 |
0 |
T11 |
0 |
255 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
498849462 |
30932 |
0 |
0 |
T1 |
92181 |
16 |
0 |
0 |
T2 |
46689 |
6 |
0 |
0 |
T3 |
67737 |
12 |
0 |
0 |
T4 |
44510 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1635 |
0 |
0 |
0 |
T19 |
207133 |
38 |
0 |
0 |
T20 |
4587 |
0 |
0 |
0 |
T21 |
1491 |
0 |
0 |
0 |
T22 |
3911 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
30948 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
30914 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
498849462 |
30938 |
0 |
0 |
T1 |
92181 |
16 |
0 |
0 |
T2 |
46689 |
6 |
0 |
0 |
T3 |
67737 |
12 |
0 |
0 |
T4 |
44510 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1635 |
0 |
0 |
0 |
T19 |
207133 |
38 |
0 |
0 |
T20 |
4587 |
0 |
0 |
0 |
T21 |
1491 |
0 |
0 |
0 |
T22 |
3911 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239392361 |
24520 |
0 |
0 |
T1 |
44247 |
16 |
0 |
0 |
T2 |
22410 |
6 |
0 |
0 |
T3 |
32515 |
12 |
0 |
0 |
T4 |
21365 |
6 |
0 |
0 |
T8 |
0 |
13 |
0 |
0 |
T11 |
0 |
255 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
784 |
0 |
0 |
0 |
T19 |
108065 |
38 |
0 |
0 |
T20 |
2202 |
0 |
0 |
0 |
T21 |
750 |
0 |
0 |
0 |
T22 |
1877 |
0 |
0 |
0 |
T23 |
725 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
8 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
24937 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
12 |
0 |
0 |
T8 |
0 |
26 |
0 |
0 |
T11 |
0 |
255 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239392361 |
30772 |
0 |
0 |
T1 |
44247 |
16 |
0 |
0 |
T2 |
22410 |
6 |
0 |
0 |
T3 |
32515 |
12 |
0 |
0 |
T4 |
21365 |
24 |
0 |
0 |
T8 |
0 |
39 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
784 |
0 |
0 |
0 |
T19 |
108065 |
38 |
0 |
0 |
T20 |
2202 |
0 |
0 |
0 |
T21 |
750 |
0 |
0 |
0 |
T22 |
1877 |
0 |
0 |
0 |
T23 |
725 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
31 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
30923 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
24 |
0 |
0 |
T8 |
0 |
52 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T4,T2 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
30658 |
0 |
0 |
T1 |
90338 |
16 |
0 |
0 |
T2 |
18675 |
6 |
0 |
0 |
T3 |
61641 |
12 |
0 |
0 |
T4 |
11127 |
18 |
0 |
0 |
T8 |
0 |
39 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
1586 |
0 |
0 |
0 |
T19 |
224206 |
38 |
0 |
0 |
T20 |
1100 |
0 |
0 |
0 |
T21 |
1579 |
0 |
0 |
0 |
T22 |
1917 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
29 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239392361 |
30802 |
0 |
0 |
T1 |
44247 |
16 |
0 |
0 |
T2 |
22410 |
6 |
0 |
0 |
T3 |
32515 |
12 |
0 |
0 |
T4 |
21365 |
24 |
0 |
0 |
T8 |
0 |
39 |
0 |
0 |
T11 |
0 |
266 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T18 |
784 |
0 |
0 |
0 |
T19 |
108065 |
38 |
0 |
0 |
T20 |
2202 |
0 |
0 |
0 |
T21 |
750 |
0 |
0 |
0 |
T22 |
1877 |
0 |
0 |
0 |
T23 |
725 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T51,T52,T54 |
1 | 0 | Covered | T51,T52,T54 |
1 | 1 | Covered | T56,T110,T111 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T51,T52,T54 |
1 | 0 | Covered | T56,T110,T111 |
1 | 1 | Covered | T51,T52,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
42 |
0 |
0 |
T51 |
6490 |
4 |
0 |
0 |
T52 |
8803 |
2 |
0 |
0 |
T53 |
11549 |
2 |
0 |
0 |
T54 |
2857 |
1 |
0 |
0 |
T55 |
7803 |
1 |
0 |
0 |
T56 |
2493 |
2 |
0 |
0 |
T57 |
6524 |
2 |
0 |
0 |
T104 |
5273 |
2 |
0 |
0 |
T105 |
7751 |
2 |
0 |
0 |
T107 |
9954 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468127480 |
42 |
0 |
0 |
T51 |
24921 |
4 |
0 |
0 |
T52 |
33802 |
2 |
0 |
0 |
T53 |
20531 |
2 |
0 |
0 |
T54 |
17145 |
1 |
0 |
0 |
T55 |
31212 |
1 |
0 |
0 |
T56 |
8867 |
2 |
0 |
0 |
T57 |
26094 |
2 |
0 |
0 |
T104 |
20247 |
2 |
0 |
0 |
T105 |
31006 |
2 |
0 |
0 |
T107 |
39816 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T50,T51,T52 |
1 | 0 | Covered | T50,T51,T52 |
1 | 1 | Covered | T56,T112,T108 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T50,T51,T52 |
1 | 0 | Covered | T56,T112,T108 |
1 | 1 | Covered | T50,T51,T52 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
44 |
0 |
0 |
T50 |
13789 |
1 |
0 |
0 |
T51 |
6490 |
3 |
0 |
0 |
T52 |
8803 |
2 |
0 |
0 |
T54 |
2857 |
1 |
0 |
0 |
T56 |
2493 |
2 |
0 |
0 |
T57 |
6524 |
2 |
0 |
0 |
T105 |
7751 |
2 |
0 |
0 |
T106 |
5925 |
1 |
0 |
0 |
T107 |
9954 |
2 |
0 |
0 |
T112 |
7183 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468127480 |
44 |
0 |
0 |
T50 |
13789 |
1 |
0 |
0 |
T51 |
24921 |
3 |
0 |
0 |
T52 |
33802 |
2 |
0 |
0 |
T54 |
17145 |
1 |
0 |
0 |
T56 |
8867 |
2 |
0 |
0 |
T57 |
26094 |
2 |
0 |
0 |
T105 |
31006 |
2 |
0 |
0 |
T106 |
5863 |
1 |
0 |
0 |
T107 |
39816 |
2 |
0 |
0 |
T112 |
25542 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T50,T53,T55 |
1 | 0 | Covered | T50,T53,T55 |
1 | 1 | Covered | T109,T110,T113 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T50,T53,T55 |
1 | 0 | Covered | T109,T110,T113 |
1 | 1 | Covered | T50,T53,T55 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
36 |
0 |
0 |
T50 |
13789 |
2 |
0 |
0 |
T53 |
11549 |
2 |
0 |
0 |
T55 |
7803 |
1 |
0 |
0 |
T57 |
6524 |
1 |
0 |
0 |
T104 |
5273 |
1 |
0 |
0 |
T105 |
7751 |
1 |
0 |
0 |
T106 |
5925 |
1 |
0 |
0 |
T107 |
9954 |
2 |
0 |
0 |
T108 |
4613 |
2 |
0 |
0 |
T109 |
13302 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233316797 |
36 |
0 |
0 |
T50 |
6082 |
2 |
0 |
0 |
T53 |
9247 |
2 |
0 |
0 |
T55 |
14694 |
1 |
0 |
0 |
T57 |
12470 |
1 |
0 |
0 |
T104 |
9599 |
1 |
0 |
0 |
T105 |
14542 |
1 |
0 |
0 |
T106 |
2660 |
1 |
0 |
0 |
T107 |
19085 |
2 |
0 |
0 |
T108 |
9425 |
2 |
0 |
0 |
T109 |
6028 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T50,T53,T56 |
1 | 0 | Covered | T50,T53,T56 |
1 | 1 | Covered | T109,T110,T114 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T50,T53,T56 |
1 | 0 | Covered | T109,T110,T114 |
1 | 1 | Covered | T50,T53,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
29 |
0 |
0 |
T50 |
13789 |
3 |
0 |
0 |
T53 |
11549 |
2 |
0 |
0 |
T56 |
2493 |
1 |
0 |
0 |
T57 |
6524 |
1 |
0 |
0 |
T104 |
5273 |
1 |
0 |
0 |
T106 |
5925 |
1 |
0 |
0 |
T107 |
9954 |
1 |
0 |
0 |
T108 |
4613 |
1 |
0 |
0 |
T109 |
13302 |
2 |
0 |
0 |
T110 |
7136 |
4 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
233316797 |
29 |
0 |
0 |
T50 |
6082 |
3 |
0 |
0 |
T53 |
9247 |
2 |
0 |
0 |
T56 |
4088 |
1 |
0 |
0 |
T57 |
12470 |
1 |
0 |
0 |
T104 |
9599 |
1 |
0 |
0 |
T106 |
2660 |
1 |
0 |
0 |
T107 |
19085 |
1 |
0 |
0 |
T108 |
9425 |
1 |
0 |
0 |
T109 |
6028 |
2 |
0 |
0 |
T110 |
6201 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T51,T52,T55 |
1 | 0 | Covered | T51,T52,T55 |
1 | 1 | Covered | T55,T108,T115 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T51,T52,T55 |
1 | 0 | Covered | T55,T108,T115 |
1 | 1 | Covered | T51,T52,T55 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
34 |
0 |
0 |
T51 |
6490 |
1 |
0 |
0 |
T52 |
8803 |
1 |
0 |
0 |
T55 |
7803 |
3 |
0 |
0 |
T57 |
6524 |
3 |
0 |
0 |
T108 |
4613 |
2 |
0 |
0 |
T110 |
7136 |
1 |
0 |
0 |
T113 |
9476 |
2 |
0 |
0 |
T115 |
11598 |
2 |
0 |
0 |
T116 |
6517 |
1 |
0 |
0 |
T117 |
12993 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116657803 |
34 |
0 |
0 |
T51 |
5833 |
1 |
0 |
0 |
T52 |
8000 |
1 |
0 |
0 |
T55 |
7346 |
3 |
0 |
0 |
T57 |
6234 |
3 |
0 |
0 |
T108 |
4713 |
2 |
0 |
0 |
T110 |
3102 |
1 |
0 |
0 |
T113 |
1904 |
2 |
0 |
0 |
T115 |
2432 |
2 |
0 |
0 |
T116 |
2849 |
1 |
0 |
0 |
T117 |
6105 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T51,T52,T55 |
1 | 0 | Covered | T51,T52,T55 |
1 | 1 | Covered | T55,T118 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T51,T52,T55 |
1 | 0 | Covered | T55,T118 |
1 | 1 | Covered | T51,T52,T55 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
25 |
0 |
0 |
T51 |
6490 |
2 |
0 |
0 |
T52 |
8803 |
1 |
0 |
0 |
T55 |
7803 |
3 |
0 |
0 |
T57 |
6524 |
3 |
0 |
0 |
T104 |
5273 |
1 |
0 |
0 |
T107 |
9954 |
1 |
0 |
0 |
T108 |
4613 |
1 |
0 |
0 |
T113 |
9476 |
1 |
0 |
0 |
T115 |
11598 |
1 |
0 |
0 |
T116 |
6517 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116657803 |
25 |
0 |
0 |
T51 |
5833 |
2 |
0 |
0 |
T52 |
8000 |
1 |
0 |
0 |
T55 |
7346 |
3 |
0 |
0 |
T57 |
6234 |
3 |
0 |
0 |
T104 |
4800 |
1 |
0 |
0 |
T107 |
9544 |
1 |
0 |
0 |
T108 |
4713 |
1 |
0 |
0 |
T113 |
1904 |
1 |
0 |
0 |
T115 |
2432 |
1 |
0 |
0 |
T116 |
2849 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T50,T52,T54 |
1 | 0 | Covered | T50,T52,T54 |
1 | 1 | Covered | T56,T55,T57 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T50,T52,T54 |
1 | 0 | Covered | T56,T55,T57 |
1 | 1 | Covered | T50,T52,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
35 |
0 |
0 |
T50 |
13789 |
1 |
0 |
0 |
T52 |
8803 |
3 |
0 |
0 |
T54 |
2857 |
1 |
0 |
0 |
T55 |
7803 |
2 |
0 |
0 |
T56 |
2493 |
3 |
0 |
0 |
T57 |
6524 |
3 |
0 |
0 |
T105 |
7751 |
3 |
0 |
0 |
T106 |
5925 |
1 |
0 |
0 |
T107 |
9954 |
2 |
0 |
0 |
T108 |
4613 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
498849462 |
35 |
0 |
0 |
T50 |
14365 |
1 |
0 |
0 |
T52 |
35211 |
3 |
0 |
0 |
T54 |
17861 |
1 |
0 |
0 |
T55 |
32514 |
2 |
0 |
0 |
T56 |
9238 |
3 |
0 |
0 |
T57 |
27182 |
3 |
0 |
0 |
T105 |
32300 |
3 |
0 |
0 |
T106 |
6108 |
1 |
0 |
0 |
T107 |
41477 |
2 |
0 |
0 |
T108 |
20968 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T52,T54,T56 |
1 | 0 | Covered | T52,T54,T56 |
1 | 1 | Covered | T57,T105,T106 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T52,T54,T56 |
1 | 0 | Covered | T57,T105,T106 |
1 | 1 | Covered | T52,T54,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
39 |
0 |
0 |
T52 |
8803 |
2 |
0 |
0 |
T54 |
2857 |
2 |
0 |
0 |
T55 |
7803 |
2 |
0 |
0 |
T56 |
2493 |
1 |
0 |
0 |
T57 |
6524 |
2 |
0 |
0 |
T105 |
7751 |
5 |
0 |
0 |
T106 |
5925 |
2 |
0 |
0 |
T107 |
9954 |
2 |
0 |
0 |
T108 |
4613 |
2 |
0 |
0 |
T116 |
6517 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
498849462 |
39 |
0 |
0 |
T52 |
35211 |
2 |
0 |
0 |
T54 |
17861 |
2 |
0 |
0 |
T55 |
32514 |
2 |
0 |
0 |
T56 |
9238 |
1 |
0 |
0 |
T57 |
27182 |
2 |
0 |
0 |
T105 |
32300 |
5 |
0 |
0 |
T106 |
6108 |
2 |
0 |
0 |
T107 |
41477 |
2 |
0 |
0 |
T108 |
20968 |
2 |
0 |
0 |
T116 |
13036 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T50,T51,T52 |
1 | 0 | Covered | T50,T51,T52 |
1 | 1 | Covered | T51,T57,T115 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T50,T51,T52 |
1 | 0 | Covered | T51,T57,T115 |
1 | 1 | Covered | T50,T51,T52 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
30 |
0 |
0 |
T50 |
13789 |
2 |
0 |
0 |
T51 |
6490 |
2 |
0 |
0 |
T52 |
8803 |
1 |
0 |
0 |
T53 |
11549 |
1 |
0 |
0 |
T56 |
2493 |
1 |
0 |
0 |
T57 |
6524 |
2 |
0 |
0 |
T107 |
9954 |
1 |
0 |
0 |
T110 |
7136 |
1 |
0 |
0 |
T119 |
5653 |
1 |
0 |
0 |
T120 |
14344 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239392361 |
30 |
0 |
0 |
T50 |
6895 |
2 |
0 |
0 |
T51 |
12461 |
2 |
0 |
0 |
T52 |
16902 |
1 |
0 |
0 |
T53 |
10265 |
1 |
0 |
0 |
T56 |
4434 |
1 |
0 |
0 |
T57 |
13048 |
2 |
0 |
0 |
T107 |
19909 |
1 |
0 |
0 |
T110 |
7288 |
1 |
0 |
0 |
T119 |
2826 |
1 |
0 |
0 |
T120 |
7325 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T50,T51,T52 |
1 | 0 | Covered | T50,T51,T52 |
1 | 1 | Covered | T50,T51,T52 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T50,T51,T52 |
1 | 0 | Covered | T50,T51,T52 |
1 | 1 | Covered | T50,T51,T52 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
157786120 |
32 |
0 |
0 |
T50 |
13789 |
3 |
0 |
0 |
T51 |
6490 |
2 |
0 |
0 |
T52 |
8803 |
2 |
0 |
0 |
T53 |
11549 |
1 |
0 |
0 |
T55 |
7803 |
1 |
0 |
0 |
T57 |
6524 |
2 |
0 |
0 |
T106 |
5925 |
1 |
0 |
0 |
T110 |
7136 |
1 |
0 |
0 |
T112 |
7183 |
1 |
0 |
0 |
T120 |
14344 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239392361 |
32 |
0 |
0 |
T50 |
6895 |
3 |
0 |
0 |
T51 |
12461 |
2 |
0 |
0 |
T52 |
16902 |
2 |
0 |
0 |
T53 |
10265 |
1 |
0 |
0 |
T55 |
15606 |
1 |
0 |
0 |
T57 |
13048 |
2 |
0 |
0 |
T106 |
2932 |
1 |
0 |
0 |
T110 |
7288 |
1 |
0 |
0 |
T112 |
12771 |
1 |
0 |
0 |
T120 |
7325 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
465363841 |
99285 |
0 |
0 |
T1 |
88491 |
37 |
0 |
0 |
T2 |
44819 |
12 |
0 |
0 |
T3 |
65026 |
27 |
0 |
0 |
T4 |
42728 |
0 |
0 |
0 |
T11 |
0 |
1050 |
0 |
0 |
T12 |
0 |
270 |
0 |
0 |
T13 |
0 |
1764 |
0 |
0 |
T18 |
1569 |
0 |
0 |
0 |
T19 |
164283 |
191 |
0 |
0 |
T20 |
4403 |
0 |
0 |
0 |
T21 |
1465 |
0 |
0 |
0 |
T22 |
3754 |
0 |
0 |
0 |
T23 |
1451 |
0 |
0 |
0 |
T32 |
0 |
47 |
0 |
0 |
T62 |
0 |
163 |
0 |
0 |
T63 |
0 |
192 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17511133 |
98243 |
0 |
0 |
T1 |
189 |
37 |
0 |
0 |
T2 |
1024 |
12 |
0 |
0 |
T3 |
149 |
27 |
0 |
0 |
T4 |
110 |
0 |
0 |
0 |
T11 |
0 |
1050 |
0 |
0 |
T12 |
0 |
270 |
0 |
0 |
T13 |
0 |
1764 |
0 |
0 |
T18 |
114 |
0 |
0 |
0 |
T19 |
373 |
191 |
0 |
0 |
T20 |
320 |
0 |
0 |
0 |
T21 |
120 |
0 |
0 |
0 |
T22 |
273 |
0 |
0 |
0 |
T23 |
106 |
0 |
0 |
0 |
T32 |
0 |
47 |
0 |
0 |
T62 |
0 |
163 |
0 |
0 |
T63 |
0 |
192 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
231981232 |
98023 |
0 |
0 |
T1 |
44233 |
37 |
0 |
0 |
T2 |
23105 |
12 |
0 |
0 |
T3 |
32501 |
27 |
0 |
0 |
T4 |
15300 |
0 |
0 |
0 |
T11 |
0 |
1050 |
0 |
0 |
T12 |
0 |
270 |
0 |
0 |
T13 |
0 |
1764 |
0 |
0 |
T18 |
770 |
0 |
0 |
0 |
T19 |
82027 |
191 |
0 |
0 |
T20 |
2189 |
0 |
0 |
0 |
T21 |
693 |
0 |
0 |
0 |
T22 |
1817 |
0 |
0 |
0 |
T23 |
701 |
0 |
0 |
0 |
T32 |
0 |
47 |
0 |
0 |
T62 |
0 |
163 |
0 |
0 |
T63 |
0 |
192 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17511133 |
96982 |
0 |
0 |
T1 |
189 |
37 |
0 |
0 |
T2 |
1024 |
12 |
0 |
0 |
T3 |
149 |
27 |
0 |
0 |
T4 |
110 |
0 |
0 |
0 |
T11 |
0 |
1050 |
0 |
0 |
T12 |
0 |
270 |
0 |
0 |
T13 |
0 |
1764 |
0 |
0 |
T18 |
114 |
0 |
0 |
0 |
T19 |
373 |
191 |
0 |
0 |
T20 |
320 |
0 |
0 |
0 |
T21 |
120 |
0 |
0 |
0 |
T22 |
273 |
0 |
0 |
0 |
T23 |
106 |
0 |
0 |
0 |
T32 |
0 |
47 |
0 |
0 |
T62 |
0 |
163 |
0 |
0 |
T63 |
0 |
192 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
115990036 |
96372 |
0 |
0 |
T1 |
22117 |
37 |
0 |
0 |
T2 |
11552 |
12 |
0 |
0 |
T3 |
16250 |
27 |
0 |
0 |
T4 |
7649 |
0 |
0 |
0 |
T11 |
0 |
1050 |
0 |
0 |
T12 |
0 |
270 |
0 |
0 |
T13 |
0 |
1762 |
0 |
0 |
T18 |
385 |
0 |
0 |
0 |
T19 |
41014 |
191 |
0 |
0 |
T20 |
1095 |
0 |
0 |
0 |
T21 |
346 |
0 |
0 |
0 |
T22 |
908 |
0 |
0 |
0 |
T23 |
350 |
0 |
0 |
0 |
T32 |
0 |
47 |
0 |
0 |
T62 |
0 |
163 |
0 |
0 |
T63 |
0 |
192 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17511133 |
95344 |
0 |
0 |
T1 |
189 |
37 |
0 |
0 |
T2 |
1024 |
12 |
0 |
0 |
T3 |
149 |
27 |
0 |
0 |
T4 |
110 |
0 |
0 |
0 |
T11 |
0 |
1050 |
0 |
0 |
T12 |
0 |
270 |
0 |
0 |
T13 |
0 |
1762 |
0 |
0 |
T18 |
114 |
0 |
0 |
0 |
T19 |
373 |
191 |
0 |
0 |
T20 |
320 |
0 |
0 |
0 |
T21 |
120 |
0 |
0 |
0 |
T22 |
273 |
0 |
0 |
0 |
T23 |
106 |
0 |
0 |
0 |
T32 |
0 |
47 |
0 |
0 |
T62 |
0 |
163 |
0 |
0 |
T63 |
0 |
192 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
495970562 |
116736 |
0 |
0 |
T1 |
92181 |
37 |
0 |
0 |
T2 |
46689 |
12 |
0 |
0 |
T3 |
67737 |
27 |
0 |
0 |
T4 |
44510 |
0 |
0 |
0 |
T11 |
0 |
1170 |
0 |
0 |
T12 |
0 |
318 |
0 |
0 |
T13 |
0 |
2154 |
0 |
0 |
T18 |
1635 |
0 |
0 |
0 |
T19 |
207133 |
263 |
0 |
0 |
T20 |
4587 |
0 |
0 |
0 |
T21 |
1491 |
0 |
0 |
0 |
T22 |
3911 |
0 |
0 |
0 |
T23 |
1511 |
0 |
0 |
0 |
T32 |
0 |
35 |
0 |
0 |
T62 |
0 |
187 |
0 |
0 |
T63 |
0 |
312 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17555993 |
114750 |
0 |
0 |
T1 |
189 |
37 |
0 |
0 |
T2 |
1024 |
12 |
0 |
0 |
T3 |
149 |
27 |
0 |
0 |
T4 |
110 |
0 |
0 |
0 |
T11 |
0 |
767 |
0 |
0 |
T12 |
0 |
318 |
0 |
0 |
T13 |
0 |
2154 |
0 |
0 |
T18 |
114 |
0 |
0 |
0 |
T19 |
445 |
263 |
0 |
0 |
T20 |
320 |
0 |
0 |
0 |
T21 |
120 |
0 |
0 |
0 |
T22 |
273 |
0 |
0 |
0 |
T23 |
106 |
0 |
0 |
0 |
T32 |
0 |
35 |
0 |
0 |
T62 |
0 |
187 |
0 |
0 |
T63 |
0 |
312 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
238010522 |
114642 |
0 |
0 |
T1 |
44247 |
37 |
0 |
0 |
T2 |
22410 |
12 |
0 |
0 |
T3 |
32515 |
27 |
0 |
0 |
T4 |
21365 |
0 |
0 |
0 |
T11 |
0 |
1194 |
0 |
0 |
T12 |
0 |
318 |
0 |
0 |
T13 |
0 |
2076 |
0 |
0 |
T18 |
784 |
0 |
0 |
0 |
T19 |
108065 |
299 |
0 |
0 |
T20 |
2202 |
0 |
0 |
0 |
T21 |
750 |
0 |
0 |
0 |
T22 |
1877 |
0 |
0 |
0 |
T23 |
725 |
0 |
0 |
0 |
T32 |
0 |
35 |
0 |
0 |
T62 |
0 |
172 |
0 |
0 |
T63 |
0 |
240 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17598580 |
113834 |
0 |
0 |
T1 |
189 |
37 |
0 |
0 |
T2 |
1024 |
12 |
0 |
0 |
T3 |
149 |
27 |
0 |
0 |
T4 |
110 |
0 |
0 |
0 |
T11 |
0 |
1194 |
0 |
0 |
T12 |
0 |
318 |
0 |
0 |
T13 |
0 |
2076 |
0 |
0 |
T18 |
114 |
0 |
0 |
0 |
T19 |
481 |
299 |
0 |
0 |
T20 |
320 |
0 |
0 |
0 |
T21 |
120 |
0 |
0 |
0 |
T22 |
273 |
0 |
0 |
0 |
T23 |
106 |
0 |
0 |
0 |
T32 |
0 |
35 |
0 |
0 |
T62 |
0 |
172 |
0 |
0 |
T63 |
0 |
240 |
0 |
0 |