Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T11,T8
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1577861200	1459672	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1577861200	278018	0	0
SrcBusyKnown_A	1577861200	1550625240	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577861200	1459672	0	0
T1	903380	1269	0	0
T2	186750	273	0	0
T3	616410	865	0	0
T4	111270	572	0	0
T8	0	3162	0	0
T11	0	21168	0	0
T12	0	5477	0	0
T18	15860	0	0	0
T19	2242060	3105	0	0
T20	11000	0	0	0
T21	15790	0	0	0
T22	19170	0	0	0
T23	15110	0	0	0
T32	0	430	0	0
T33	0	2010	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	582538	582228	0	0
T2	297150	295094	0	0
T3	428058	427116	0	0
T4	263104	42606	0	0
T5	17116	16096	0	0
T6	28388	27218	0	0
T7	15116	14280	0	0
T18	10286	9772	0	0
T19	1205044	1202878	0	0
T20	28952	28284	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577861200	278018	0	0
T1	903380	160	0	0
T2	186750	60	0	0
T3	616410	120	0	0
T4	111270	168	0	0
T8	0	364	0	0
T11	0	2605	0	0
T12	0	780	0	0
T18	15860	0	0	0
T19	2242060	380	0	0
T20	11000	0	0	0
T21	15790	0	0	0
T22	19170	0	0	0
T23	15110	0	0	0
T32	0	60	0	0
T33	0	230	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577861200	1550625240	0	0
T1	903380	902850	0	0
T2	186750	185210	0	0
T3	616410	615010	0	0
T4	111270	16910	0	0
T5	13140	12250	0	0
T6	15960	15250	0	0
T7	22890	21410	0	0
T18	15860	14920	0	0
T19	2242060	2238200	0	0
T20	11000	10740	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157786120	90785	0	0
DstReqKnown_A	468127480	463689137	0	0
SrcAckBusyChk_A	157786120	24937	0	0
SrcBusyKnown_A	157786120	155062524	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	90785	0	0
T1	90338	80	0	0
T2	18675	20	0	0
T3	61641	52	0	0
T4	11127	28	0	0
T8	0	138	0	0
T11	0	1296	0	0
T12	0	352	0	0
T18	1586	0	0	0
T19	224206	196	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	26	0	0
T33	0	87	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468127480	463689137	0	0
T1	88491	88438	0	0
T2	44819	44452	0	0
T3	65026	64877	0	0
T4	42728	6471	0	0
T5	2574	2398	0	0
T6	4258	4068	0	0
T7	2289	2141	0	0
T18	1569	1476	0	0
T19	164283	163902	0	0
T20	4403	4296	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	24937	0	0
T1	90338	16	0	0
T2	18675	6	0	0
T3	61641	12	0	0
T4	11127	12	0	0
T8	0	26	0	0
T11	0	255	0	0
T12	0	78	0	0
T18	1586	0	0	0
T19	224206	38	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	6	0	0
T33	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	155062524	0	0
T1	90338	90285	0	0
T2	18675	18521	0	0
T3	61641	61501	0	0
T4	11127	1691	0	0
T5	1314	1225	0	0
T6	1596	1525	0	0
T7	2289	2141	0	0
T18	1586	1492	0	0
T19	224206	223820	0	0
T20	1100	1074	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157786120	129506	0	0
DstReqKnown_A	233316797	232194051	0	0
SrcAckBusyChk_A	157786120	24937	0	0
SrcBusyKnown_A	157786120	155062524	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	129506	0	0
T1	90338	131	0	0
T2	18675	29	0	0
T3	61641	87	0	0
T4	11127	39	0	0
T8	0	216	0	0
T11	0	2087	0	0
T12	0	553	0	0
T18	1586	0	0	0
T19	224206	314	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	44	0	0
T33	0	139	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233316797	232194051	0	0
T1	44233	44219	0	0
T2	23105	23043	0	0
T3	32501	32439	0	0
T4	15300	3238	0	0
T5	1344	1303	0	0
T6	2248	2179	0	0
T7	1160	1132	0	0
T18	770	756	0	0
T19	82027	81951	0	0
T20	2189	2148	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	24937	0	0
T1	90338	16	0	0
T2	18675	6	0	0
T3	61641	12	0	0
T4	11127	12	0	0
T8	0	26	0	0
T11	0	255	0	0
T12	0	78	0	0
T18	1586	0	0	0
T19	224206	38	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	6	0	0
T33	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	155062524	0	0
T1	90338	90285	0	0
T2	18675	18521	0	0
T3	61641	61501	0	0
T4	11127	1691	0	0
T5	1314	1225	0	0
T6	1596	1525	0	0
T7	2289	2141	0	0
T18	1586	1492	0	0
T19	224206	223820	0	0
T20	1100	1074	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157786120	206610	0	0
DstReqKnown_A	116657803	116096556	0	0
SrcAckBusyChk_A	157786120	24937	0	0
SrcBusyKnown_A	157786120	155062524	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	206610	0	0
T1	90338	220	0	0
T2	18675	44	0	0
T3	61641	152	0	0
T4	11127	55	0	0
T8	0	410	0	0
T11	0	3640	0	0
T12	0	934	0	0
T18	1586	0	0	0
T19	224206	541	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	75	0	0
T33	0	240	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116657803	116096556	0	0
T1	22117	22110	0	0
T2	11552	11521	0	0
T3	16250	16219	0	0
T4	7649	1618	0	0
T5	671	650	0	0
T6	1123	1089	0	0
T7	580	566	0	0
T18	385	378	0	0
T19	41014	40976	0	0
T20	1095	1074	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	24937	0	0
T1	90338	16	0	0
T2	18675	6	0	0
T3	61641	12	0	0
T4	11127	12	0	0
T8	0	26	0	0
T11	0	255	0	0
T12	0	78	0	0
T18	1586	0	0	0
T19	224206	38	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	6	0	0
T33	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	155062524	0	0
T1	90338	90285	0	0
T2	18675	18521	0	0
T3	61641	61501	0	0
T4	11127	1691	0	0
T5	1314	1225	0	0
T6	1596	1525	0	0
T7	2289	2141	0	0
T18	1586	1492	0	0
T19	224206	223820	0	0
T20	1100	1074	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157786120	88863	0	0
DstReqKnown_A	498849462	494188865	0	0
SrcAckBusyChk_A	157786120	24937	0	0
SrcBusyKnown_A	157786120	155062524	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	88863	0	0
T1	90338	79	0	0
T2	18675	19	0	0
T3	61641	50	0	0
T4	11127	27	0	0
T8	0	160	0	0
T11	0	1265	0	0
T12	0	333	0	0
T18	1586	0	0	0
T19	224206	193	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	26	0	0
T33	0	86	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498849462	494188865	0	0
T1	92181	92126	0	0
T2	46689	46305	0	0
T3	67737	67582	0	0
T4	44510	6741	0	0
T5	2682	2498	0	0
T6	4436	4238	0	0
T7	2385	2231	0	0
T18	1635	1538	0	0
T19	207133	206735	0	0
T20	4587	4476	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	24937	0	0
T1	90338	16	0	0
T2	18675	6	0	0
T3	61641	12	0	0
T4	11127	12	0	0
T8	0	26	0	0
T11	0	255	0	0
T12	0	78	0	0
T18	1586	0	0	0
T19	224206	38	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	6	0	0
T33	0	16	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	155062524	0	0
T1	90338	90285	0	0
T2	18675	18521	0	0
T3	61641	61501	0	0
T4	11127	1691	0	0
T5	1314	1225	0	0
T6	1596	1525	0	0
T7	2289	2141	0	0
T18	1586	1492	0	0
T19	224206	223820	0	0
T20	1100	1074	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157786120	127070	0	0
DstReqKnown_A	239392361	237143809	0	0
SrcAckBusyChk_A	157786120	24474	0	0
SrcBusyKnown_A	157786120	155062524	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	127070	0	0
T1	90338	129	0	0
T2	18675	27	0	0
T3	61641	90	0	0
T4	11127	28	0	0
T8	0	140	0	0
T11	0	2088	0	0
T12	0	551	0	0
T18	1586	0	0	0
T19	224206	313	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	43	0	0
T33	0	110	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239392361	237143809	0	0
T1	44247	44221	0	0
T2	22410	22226	0	0
T3	32515	32441	0	0
T4	21365	3235	0	0
T5	1287	1199	0	0
T6	2129	2035	0	0
T7	1144	1070	0	0
T18	784	738	0	0
T19	108065	107875	0	0
T20	2202	2148	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	24474	0	0
T1	90338	16	0	0
T2	18675	6	0	0
T3	61641	12	0	0
T4	11127	6	0	0
T8	0	13	0	0
T11	0	255	0	0
T12	0	78	0	0
T18	1586	0	0	0
T19	224206	38	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	6	0	0
T33	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	155062524	0	0
T1	90338	90285	0	0
T2	18675	18521	0	0
T3	61641	61501	0	0
T4	11127	1691	0	0
T5	1314	1225	0	0
T6	1596	1525	0	0
T7	2289	2141	0	0
T18	1586	1492	0	0
T19	224206	223820	0	0
T20	1100	1074	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T11,T8
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157786120	114877	0	0
DstReqKnown_A	468127480	463689137	0	0
SrcAckBusyChk_A	157786120	30951	0	0
SrcBusyKnown_A	157786120	155062524	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	114877	0	0
T1	90338	81	0	0
T2	18675	20	0	0
T3	61641	55	0	0
T4	11127	58	0	0
T8	0	266	0	0
T11	0	1354	0	0
T12	0	351	0	0
T18	1586	0	0	0
T19	224206	194	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	27	0	0
T33	0	168	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468127480	463689137	0	0
T1	88491	88438	0	0
T2	44819	44452	0	0
T3	65026	64877	0	0
T4	42728	6471	0	0
T5	2574	2398	0	0
T6	4258	4068	0	0
T7	2289	2141	0	0
T18	1569	1476	0	0
T19	164283	163902	0	0
T20	4403	4296	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	30951	0	0
T1	90338	16	0	0
T2	18675	6	0	0
T3	61641	12	0	0
T4	11127	24	0	0
T8	0	52	0	0
T11	0	266	0	0
T12	0	78	0	0
T18	1586	0	0	0
T19	224206	38	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	6	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	155062524	0	0
T1	90338	90285	0	0
T2	18675	18521	0	0
T3	61641	61501	0	0
T4	11127	1691	0	0
T5	1314	1225	0	0
T6	1596	1525	0	0
T7	2289	2141	0	0
T18	1586	1492	0	0
T19	224206	223820	0	0
T20	1100	1074	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T11,T8
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157786120	163586	0	0
DstReqKnown_A	233316797	232194051	0	0
SrcAckBusyChk_A	157786120	30646	0	0
SrcBusyKnown_A	157786120	155062524	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	163586	0	0
T1	90338	127	0	0
T2	18675	27	0	0
T3	61641	86	0	0
T4	11127	82	0	0
T8	0	414	0	0
T11	0	2157	0	0
T12	0	546	0	0
T18	1586	0	0	0
T19	224206	310	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	44	0	0
T33	0	277	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233316797	232194051	0	0
T1	44233	44219	0	0
T2	23105	23043	0	0
T3	32501	32439	0	0
T4	15300	3238	0	0
T5	1344	1303	0	0
T6	2248	2179	0	0
T7	1160	1132	0	0
T18	770	756	0	0
T19	82027	81951	0	0
T20	2189	2148	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	30646	0	0
T1	90338	16	0	0
T2	18675	6	0	0
T3	61641	12	0	0
T4	11127	24	0	0
T8	0	52	0	0
T11	0	266	0	0
T12	0	78	0	0
T18	1586	0	0	0
T19	224206	38	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	6	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	155062524	0	0
T1	90338	90285	0	0
T2	18675	18521	0	0
T3	61641	61501	0	0
T4	11127	1691	0	0
T5	1314	1225	0	0
T6	1596	1525	0	0
T7	2289	2141	0	0
T18	1586	1492	0	0
T19	224206	223820	0	0
T20	1100	1074	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T11,T8
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157786120	262685	0	0
DstReqKnown_A	116657803	116096556	0	0
SrcAckBusyChk_A	157786120	30571	0	0
SrcBusyKnown_A	157786120	155062524	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	262685	0	0
T1	90338	224	0	0
T2	18675	42	0	0
T3	61641	151	0	0
T4	11127	117	0	0
T8	0	730	0	0
T11	0	3804	0	0
T12	0	965	0	0
T18	1586	0	0	0
T19	224206	543	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	76	0	0
T33	0	467	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116657803	116096556	0	0
T1	22117	22110	0	0
T2	11552	11521	0	0
T3	16250	16219	0	0
T4	7649	1618	0	0
T5	671	650	0	0
T6	1123	1089	0	0
T7	580	566	0	0
T18	385	378	0	0
T19	41014	40976	0	0
T20	1095	1074	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	30571	0	0
T1	90338	16	0	0
T2	18675	6	0	0
T3	61641	12	0	0
T4	11127	24	0	0
T8	0	52	0	0
T11	0	266	0	0
T12	0	78	0	0
T18	1586	0	0	0
T19	224206	38	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	6	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	155062524	0	0
T1	90338	90285	0	0
T2	18675	18521	0	0
T3	61641	61501	0	0
T4	11127	1691	0	0
T5	1314	1225	0	0
T6	1596	1525	0	0
T7	2289	2141	0	0
T18	1586	1492	0	0
T19	224206	223820	0	0
T20	1100	1074	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T11,T8
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157786120	112269	0	0
DstReqKnown_A	498849462	494188865	0	0
SrcAckBusyChk_A	157786120	30922	0	0
SrcBusyKnown_A	157786120	155062524	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	112269	0	0
T1	90338	78	0	0
T2	18675	19	0	0
T3	61641	53	0	0
T4	11127	57	0	0
T8	0	310	0	0
T11	0	1320	0	0
T12	0	336	0	0
T18	1586	0	0	0
T19	224206	190	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	26	0	0
T33	0	165	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498849462	494188865	0	0
T1	92181	92126	0	0
T2	46689	46305	0	0
T3	67737	67582	0	0
T4	44510	6741	0	0
T5	2682	2498	0	0
T6	4436	4238	0	0
T7	2385	2231	0	0
T18	1635	1538	0	0
T19	207133	206735	0	0
T20	4587	4476	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	30922	0	0
T1	90338	16	0	0
T2	18675	6	0	0
T3	61641	12	0	0
T4	11127	24	0	0
T8	0	52	0	0
T11	0	266	0	0
T12	0	78	0	0
T18	1586	0	0	0
T19	224206	38	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	6	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	155062524	0	0
T1	90338	90285	0	0
T2	18675	18521	0	0
T3	61641	61501	0	0
T4	11127	1691	0	0
T5	1314	1225	0	0
T6	1596	1525	0	0
T7	2289	2141	0	0
T18	1586	1492	0	0
T19	224206	223820	0	0
T20	1100	1074	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T11,T8
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157786120	163421	0	0
DstReqKnown_A	239392361	237143809	0	0
SrcAckBusyChk_A	157786120	30706	0	0
SrcBusyKnown_A	157786120	155062524	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	163421	0	0
T1	90338	120	0	0
T2	18675	26	0	0
T3	61641	89	0	0
T4	11127	81	0	0
T8	0	378	0	0
T11	0	2157	0	0
T12	0	556	0	0
T18	1586	0	0	0
T19	224206	311	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	43	0	0
T33	0	271	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239392361	237143809	0	0
T1	44247	44221	0	0
T2	22410	22226	0	0
T3	32515	32441	0	0
T4	21365	3235	0	0
T5	1287	1199	0	0
T6	2129	2035	0	0
T7	1144	1070	0	0
T18	784	738	0	0
T19	108065	107875	0	0
T20	2202	2148	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	30706	0	0
T1	90338	16	0	0
T2	18675	6	0	0
T3	61641	12	0	0
T4	11127	18	0	0
T8	0	39	0	0
T11	0	266	0	0
T12	0	78	0	0
T18	1586	0	0	0
T19	224206	38	0	0
T20	1100	0	0	0
T21	1579	0	0	0
T22	1917	0	0	0
T23	1511	0	0	0
T32	0	6	0	0
T33	0	30	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157786120	155062524	0	0
T1	90338	90285	0	0
T2	18675	18521	0	0
T3	61641	61501	0	0
T4	11127	1691	0	0
T5	1314	1225	0	0
T6	1596	1525	0	0
T7	2289	2141	0	0
T18	1586	1492	0	0
T19	224206	223820	0	0
T20	1100	1074	0	0