Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	941568	0	0
SrcPulseCheck_M	2147483647	937229	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	941568
T1	2158492	1918
T2	2968839	10028
T3	2650428	2891
T4	326481	130
T5	256856	298
T6	286313	401
T8	7895	0
T11	0	1864
T12	0	1698
T13	0	352
T14	0	2530
T18	12955	0
T25	63710	0
T26	10924	0
T51	7293	2
T52	21010	1
T53	26526	1
T56	11394	0
T57	12498	1
T58	13376	1
T59	7732	1
T60	13020	2
T61	13350	1
T62	21736	2
T109	0	991
T110	11470	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	937229
T1	1219271	1918
T2	2233128	10031
T3	643662	2891
T4	185729	130
T5	148880	298
T6	64204	401
T8	4689	0
T11	0	1864
T12	0	1698
T13	0	352
T14	0	2000
T18	4424	0
T25	16099	0
T26	6416	0
T51	2950	2
T52	34392	1
T53	11852	1
T56	21450	0
T57	5162	1
T58	23802	1
T59	14108	1
T60	5640	2
T61	13214	1
T62	8986	2
T109	0	991
T110	10930	2

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	416514782	25527	0	0
SrcPulseCheck_M	152667191	25527	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	416514782	25527
T1	426291	86
T2	679511	569
T3	895599	144
T4	81115	26
T5	53288	10
T6	70190	12
T8	1669	0
T11	0	116
T12	0	98
T13	0	24
T14	0	127
T18	3236	0
T25	16072	0
T26	2209	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152667191	25527
T1	500598	86
T2	371023	569
T3	75386	144
T4	81115	26
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	116
T12	0	98
T13	0	24
T14	0	127
T18	919	0
T25	1507	0
T26	2300	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	416514782	31220	0	0
SrcPulseCheck_M	152667191	31243	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	416514782	31220
T1	426291	86
T2	679511	580
T3	895599	144
T4	81115	52
T5	53288	10
T6	70190	12
T8	1669	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	3236	0
T25	16072	0
T26	2209	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152667191	31243
T1	500598	86
T2	371023	580
T3	75386	144
T4	81115	52
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	919	0
T25	1507	0
T26	2300	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	31208	0	0
SrcPulseCheck_M	416514782	31227	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	31208
T1	500598	86
T2	371023	580
T3	75386	144
T4	81115	52
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	919	0
T25	1507	0
T26	2300	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	416514782	31227
T1	426291	86
T2	679511	580
T3	895599	144
T4	81115	52
T5	53288	10
T6	70190	12
T8	1669	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	3236	0
T25	16072	0
T26	2209	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	207421871	25527	0	0
SrcPulseCheck_M	152667191	25527	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	207421871	25527
T1	213011	86
T2	339674	569
T3	449414	144
T4	22787	26
T5	26618	10
T6	35076	12
T8	795	0
T11	0	116
T12	0	98
T13	0	24
T14	0	127
T18	1558	0
T25	8397	0
T26	1176	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152667191	25527
T1	500598	86
T2	371023	569
T3	75386	144
T4	81115	26
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	116
T12	0	98
T13	0	24
T14	0	127
T18	919	0
T25	1507	0
T26	2300	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	207421871	31143	0	0
SrcPulseCheck_M	152667191	31165	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	207421871	31143
T1	213011	86
T2	339674	580
T3	449414	144
T4	22787	52
T5	26618	10
T6	35076	12
T8	795	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	1558	0
T25	8397	0
T26	1176	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152667191	31165
T1	500598	86
T2	371023	580
T3	75386	144
T4	81115	52
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	919	0
T25	1507	0
T26	2300	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	31139	0	0
SrcPulseCheck_M	207421871	31144	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	31139
T1	500598	86
T2	371023	580
T3	75386	144
T4	81115	52
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	919	0
T25	1507	0
T26	2300	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	207421871	31144
T1	213011	86
T2	339674	580
T3	449414	144
T4	22787	52
T5	26618	10
T6	35076	12
T8	795	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	1558	0
T25	8397	0
T26	1176	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	103710422	25527	0	0
SrcPulseCheck_M	152667191	25527	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	103710422	25527
T1	106505	86
T2	169836	569
T3	224707	144
T4	11392	26
T5	13309	10
T6	17538	12
T8	397	0
T11	0	116
T12	0	98
T13	0	24
T14	0	127
T18	779	0
T25	4198	0
T26	587	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152667191	25527
T1	500598	86
T2	371023	569
T3	75386	144
T4	81115	26
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	116
T12	0	98
T13	0	24
T14	0	127
T18	919	0
T25	1507	0
T26	2300	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	103710422	31114	0	0
SrcPulseCheck_M	152667191	31159	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	103710422	31114
T1	106505	86
T2	169836	580
T3	224707	144
T4	11392	52
T5	13309	10
T6	17538	12
T8	397	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	779	0
T25	4198	0
T26	587	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152667191	31159
T1	500598	86
T2	371023	580
T3	75386	144
T4	81115	52
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	919	0
T25	1507	0
T26	2300	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	31108	0	0
SrcPulseCheck_M	103710422	31120	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	31108
T1	500598	86
T2	371023	580
T3	75386	144
T4	81115	52
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	919	0
T25	1507	0
T26	2300	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	103710422	31120
T1	106505	86
T2	169836	580
T3	224707	144
T4	11392	52
T5	13309	10
T6	17538	12
T8	397	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	779	0
T25	4198	0
T26	587	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	445279944	25527	0	0
SrcPulseCheck_M	152667191	25527	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	445279944	25527
T1	486065	86
T2	729447	569
T3	106494	144
T4	84498	26
T5	49510	10
T6	79117	12
T8	1739	0
T11	0	116
T12	0	98
T13	0	24
T14	0	127
T18	3347	0
T25	16742	0
T26	2300	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152667191	25527
T1	500598	86
T2	371023	569
T3	75386	144
T4	81115	26
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	116
T12	0	98
T13	0	24
T14	0	127
T18	919	0
T25	1507	0
T26	2300	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	445279944	31272	0	0
SrcPulseCheck_M	152667191	31293	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	445279944	31272
T1	486065	86
T2	729447	580
T3	106494	144
T4	84498	52
T5	49510	10
T6	79117	12
T8	1739	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	3347	0
T25	16742	0
T26	2300	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152667191	31293
T1	500598	86
T2	371023	580
T3	75386	144
T4	81115	52
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	919	0
T25	1507	0
T26	2300	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	31262	0	0
SrcPulseCheck_M	445279944	31277	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	31262
T1	500598	86
T2	371023	580
T3	75386	144
T4	81115	52
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	919	0
T25	1507	0
T26	2300	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	445279944	31277
T1	486065	86
T2	729447	580
T3	106494	144
T4	84498	52
T5	49510	10
T6	79117	12
T8	1739	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	3347	0
T25	16742	0
T26	2300	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	213632817	25078	0	0
SrcPulseCheck_M	152667191	25527	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	213632817	25078
T1	230435	86
T2	350428	569
T3	502540	144
T4	40559	14
T5	26645	10
T6	26456	12
T8	834	0
T11	0	116
T12	0	98
T13	0	24
T14	0	127
T18	1653	0
T25	8036	0
T26	1104	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152667191	25527
T1	500598	86
T2	371023	569
T3	75386	144
T4	81115	26
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	116
T12	0	98
T13	0	24
T14	0	127
T18	919	0
T25	1507	0
T26	2300	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	213632817	31057	0	0
SrcPulseCheck_M	152667191	31197	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	213632817	31057
T1	230435	86
T2	350428	580
T3	502540	144
T4	40559	51
T5	26645	10
T6	26456	12
T8	834	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	1653	0
T25	8036	0
T26	1104	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152667191	31197
T1	500598	86
T2	371023	580
T3	75386	144
T4	81115	52
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	919	0
T25	1507	0
T26	2300	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	30858	0	0
SrcPulseCheck_M	213632817	31076	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	30858
T1	500598	86
T2	371023	580
T3	75386	144
T4	81115	50
T5	60895	10
T6	14240	12
T8	1705	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	919	0
T25	1507	0
T26	2300	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	213632817	31076
T1	230435	86
T2	350428	580
T3	502540	144
T4	40559	51
T5	26645	10
T6	26456	12
T8	834	0
T11	0	120
T12	0	98
T13	0	24
T14	0	133
T18	1653	0
T25	8036	0
T26	1104	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T53,T57,T58
1	0	Covered	T53,T57,T58
1	1	Covered	T111,T112

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T53,T57,T58
1	0	Covered	T111,T112
1	1	Covered	T53,T57,T58

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	36	0	0
SrcPulseCheck_M	416514782	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	36
T53	13263	2
T54	2858	1
T55	3823	1
T57	6249	1
T58	6688	2
T61	6675	1
T62	10868	1
T63	5463	1
T64	6272	1
T110	5735	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	416514782	36
T53	13263	2
T54	11927	1
T55	7340	1
T57	6249	1
T58	25683	2
T61	13634	1
T62	10755	1
T63	21853	1
T64	6207	1
T110	11470	2

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T51,T53,T57
1	0	Covered	T51,T53,T57
1	1	Covered	T53,T55,T113

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T51,T53,T57
1	0	Covered	T53,T55,T113
1	1	Covered	T51,T53,T57

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	39	0	0
SrcPulseCheck_M	416514782	39	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	39
T51	7293	1
T53	13263	3
T55	3823	2
T57	6249	1
T58	6688	1
T59	3866	1
T60	6510	1
T61	6675	1
T63	5463	1
T110	5735	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	416514782	39
T51	7144	1
T53	13263	3
T55	7340	2
T57	6249	1
T58	25683	1
T59	14846	1
T60	6441	1
T61	13634	1
T63	21853	1
T110	11470	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T51,T52,T53
1	0	Covered	T51,T52,T53
1	1	Covered	T110,T62,T60

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T51,T52,T53
1	0	Covered	T110,T62,T60
1	1	Covered	T51,T52,T53

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	36	0	0
SrcPulseCheck_M	207421871	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	36
T51	7293	2
T52	10505	1
T53	13263	1
T57	6249	1
T58	6688	1
T59	3866	1
T60	6510	2
T61	6675	1
T62	10868	2
T110	5735	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	207421871	36
T51	2950	2
T52	17196	1
T53	5926	1
T57	2581	1
T58	11901	1
T59	7054	1
T60	2820	2
T61	6607	1
T62	4493	2
T110	5465	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T52,T53,T57
1	0	Covered	T52,T53,T57
1	1	Covered	T110,T62,T60

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T52,T53,T57
1	0	Covered	T110,T62,T60
1	1	Covered	T52,T53,T57

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	43	0	0
SrcPulseCheck_M	207421871	43	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	43
T52	10505	1
T53	13263	1
T56	11394	1
T57	6249	1
T58	6688	1
T59	3866	1
T60	6510	3
T61	6675	1
T62	10868	2
T110	5735	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	207421871	43
T52	17196	1
T53	5926	1
T56	21450	1
T57	2581	1
T58	11901	1
T59	7054	1
T60	2820	3
T61	6607	1
T62	4493	2
T110	5465	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T51,T56,T59
1	0	Covered	T51,T56,T59
1	1	Covered	T56,T58,T114

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T51,T56,T59
1	0	Covered	T56,T58,T114
1	1	Covered	T51,T56,T59

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	28	0	0
SrcPulseCheck_M	103710422	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	28
T51	7293	1
T54	2858	1
T56	11394	2
T58	6688	3
T59	3866	1
T62	10868	2
T114	5617	3
T115	6112	1
T116	7106	1
T117	15405	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	103710422	28
T51	1476	1
T54	2741	1
T56	10725	2
T58	5951	3
T59	3529	1
T62	2245	2
T114	1134	3
T115	2731	1
T116	5390	1
T117	3156	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T51,T56,T59
1	0	Covered	T51,T56,T59
1	1	Covered	T58,T54,T114

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T51,T56,T59
1	0	Covered	T58,T54,T114
1	1	Covered	T51,T56,T59

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	28	0	0
SrcPulseCheck_M	103710422	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	28
T51	7293	1
T54	2858	2
T56	11394	1
T58	6688	2
T59	3866	1
T60	6510	1
T62	10868	1
T65	6711	1
T115	6112	1
T116	7106	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	103710422	28
T51	1476	1
T54	2741	2
T56	10725	1
T58	5951	2
T59	3529	1
T60	1411	1
T62	2245	1
T65	3075	1
T115	2731	1
T116	5390	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T52,T53,T57
1	0	Covered	T52,T53,T57
1	1	Covered	T110,T111,T117

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T52,T53,T57
1	0	Covered	T110,T111,T117
1	1	Covered	T52,T53,T57

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	28	0	0
SrcPulseCheck_M	445279944	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	28
T52	10505	1
T53	13263	1
T54	2858	2
T55	3823	2
T57	6249	1
T64	6272	1
T110	5735	2
T111	12773	3
T117	15405	3
T118	2807	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	445279944	28
T52	37519	1
T53	13817	1
T54	12426	2
T55	7647	2
T57	6510	1
T64	6466	1
T110	11949	2
T111	12773	3
T117	15405	3
T118	11697	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T51,T52,T53
1	0	Covered	T51,T52,T53
1	1	Covered	T54,T111,T117

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T51,T52,T53
1	0	Covered	T54,T111,T117
1	1	Covered	T51,T52,T53

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	30	0	0
SrcPulseCheck_M	445279944	30	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	30
T51	7293	1
T52	10505	1
T53	13263	1
T54	2858	2
T55	3823	1
T64	6272	1
T110	5735	1
T111	12773	3
T117	15405	3
T118	2807	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	445279944	30
T51	7442	1
T52	37519	1
T53	13817	1
T54	12426	2
T55	7647	1
T64	6466	1
T110	11949	1
T111	12773	3
T117	15405	3
T118	11697	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T52,T53,T59
1	0	Covered	T52,T53,T59
1	1	Covered	T59,T113

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T52,T53,T59
1	0	Covered	T59,T113
1	1	Covered	T52,T53,T59

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	25	0	0
SrcPulseCheck_M	213632817	25	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	25
T52	10505	1
T53	13263	2
T58	6688	1
T59	3866	3
T64	6272	1
T111	12773	2
T113	9592	2
T114	5617	1
T117	15405	1
T118	2807	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	213632817	25
T52	18009	1
T53	6632	2
T58	12842	1
T59	7423	3
T64	3103	1
T111	6131	2
T113	18417	2
T114	2696	1
T117	7395	1
T118	5614	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T59,T58,T62
1	0	Covered	T59,T58,T62
1	1	Covered	T59,T114

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T59,T58,T62
1	0	Covered	T59,T114
1	1	Covered	T59,T58,T62

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152667191	19	0	0
SrcPulseCheck_M	213632817	19	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152667191	19
T58	6688	1
T59	3866	2
T62	10868	1
T111	12773	2
T113	9592	1
T114	5617	2
T118	2807	2
T119	4809	3
T120	2987	1
T121	5524	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	213632817	19
T58	12842	1
T59	7423	2
T62	5377	1
T111	6131	2
T113	18417	1
T114	2696	2
T118	5614	2
T119	46168	3
T120	5974	1
T121	2762	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	414335477	92990	0	0
SrcPulseCheck_M	12866901	91531	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	414335477	92990
T1	426291	394
T2	679511	1968
T3	895599	557
T4	81115	0
T5	53288	70
T6	70190	89
T8	1669	0
T11	0	350
T12	0	324
T13	0	71
T14	0	526
T18	3236	0
T25	16072	0
T26	2209	0
T109	0	228

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12866901	91531
T1	1245	394
T2	287744	1969
T3	10803	557
T4	178	0
T5	121	70
T6	159	89
T8	121	0
T11	0	350
T12	0	324
T13	0	71
T14	0	346
T18	257	0
T25	1172	0
T26	160	0
T109	0	228

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	206375244	92538	0	0
SrcPulseCheck_M	12866901	91080	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	206375244	92538
T1	213011	394
T2	339674	1968
T3	449414	557
T4	22787	0
T5	26618	70
T6	35076	89
T8	795	0
T11	0	350
T12	0	324
T13	0	71
T14	0	524
T18	1558	0
T25	8397	0
T26	1176	0
T109	0	228

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12866901	91080
T1	1245	394
T2	287744	1969
T3	10803	557
T4	178	0
T5	121	70
T6	159	89
T8	121	0
T11	0	350
T12	0	324
T13	0	71
T14	0	345
T18	257	0
T25	1172	0
T26	160	0
T109	0	228

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	103187099	91759	0	0
SrcPulseCheck_M	12866901	90312	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	103187099	91759
T1	106505	394
T2	169836	1968
T3	224707	557
T4	11392	0
T5	13309	70
T6	17538	89
T8	397	0
T11	0	350
T12	0	324
T13	0	71
T14	0	503
T18	779	0
T25	4198	0
T26	587	0
T109	0	228

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12866901	90312
T1	1245	394
T2	287744	1969
T3	10803	557
T4	178	0
T5	121	70
T6	159	89
T8	121	0
T11	0	350
T12	0	324
T13	0	71
T14	0	332
T18	257	0
T25	1172	0
T26	160	0
T109	0	228

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	443009740	113405	0	0
SrcPulseCheck_M	13122150	112919	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	443009740	113405
T1	486065	478
T2	729447	2395
T3	106494	788
T4	84498	0
T5	49510	58
T6	79117	98
T8	1739	0
T11	0	458
T12	0	432
T13	0	67
T14	0	584
T18	3347	0
T25	16742	0
T26	2300	0
T109	0	307

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	13122150	112919
T1	1329	478
T2	288176	2395
T3	11067	788
T4	178	0
T5	109	58
T6	171	98
T8	121	0
T11	0	458
T12	0	432
T13	0	67
T14	0	584
T18	257	0
T25	1172	0
T26	160	0
T109	0	307

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T5,T8
0	Covered	T7,T5,T8

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	212543150	111997	0	0
SrcPulseCheck_M	13111005	111539	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	212543150	111997
T1	230435	466
T2	350428	2407
T3	502540	721
T4	40559	0
T5	26645	70
T6	26456	47
T8	834	0
T11	0	470
T12	0	444
T13	0	61
T14	0	549
T18	1653	0
T25	8036	0
T26	1104	0
T109	0	235

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	13111005	111539
T1	1317	466
T2	288188	2407
T3	11031	721
T4	178	0
T5	121	70
T6	123	47
T8	121	0
T11	0	470
T12	0	444
T13	0	61
T14	0	549
T18	257	0
T25	1172	0
T26	160	0
T109	0	235

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb