Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T4,T2,T11
1	0	Covered	T5,T6,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1526671910	1381632	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1526671910	282778	0	0
SrcBusyKnown_A	1526671910	1502418870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526671910	1381632	0	0
T1	5005980	6894	0	0
T2	3710230	29188	0	0
T3	753860	3749	0	0
T4	811150	3055	0	0
T5	608950	849	0	0
T6	142400	357	0	0
T8	17050	0	0	0
T11	0	6128	0	0
T12	0	5367	0	0
T13	0	812	0	0
T14	0	4472	0	0
T18	9190	0	0	0
T25	15070	0	0	0
T26	23000	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2924614	2921522	0	0
T2	4537792	4528262	0	0
T4	480702	53040	0	0
T5	338740	338110	0	0
T6	456754	456108	0	0
T7	69886	69210	0	0
T8	10868	9736	0	0
T18	21146	20076	0	0
T25	106890	106214	0	0
T26	14752	13414	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526671910	282778	0	0
T1	5005980	860	0	0
T2	3710230	5745	0	0
T3	753860	1440	0	0
T4	811150	376	0	0
T5	608950	100	0	0
T6	142400	120	0	0
T8	17050	0	0	0
T11	0	1180	0	0
T12	0	980	0	0
T13	0	240	0	0
T14	0	1300	0	0
T18	9190	0	0	0
T25	15070	0	0	0
T26	23000	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526671910	1502418870	0	0
T1	5005980	5000600	0	0
T2	3710230	3701280	0	0
T4	811150	80610	0	0
T5	608950	607850	0	0
T6	142400	142200	0	0
T7	21550	21300	0	0
T8	17050	15110	0	0
T18	9190	8700	0	0
T25	15070	14960	0	0
T26	23000	20600	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152667191	86285	0	0
DstReqKnown_A	416514782	412107842	0	0
SrcAckBusyChk_A	152667191	25527	0	0
SrcBusyKnown_A	152667191	150241887	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	86285	0	0
T1	500598	432	0	0
T2	371023	2021	0	0
T3	75386	366	0	0
T4	81115	148	0	0
T5	60895	55	0	0
T6	14240	29	0	0
T8	1705	0	0	0
T11	0	406	0	0
T12	0	364	0	0
T13	0	59	0	0
T14	0	321	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416514782	412107842	0	0
T1	426291	425761	0	0
T2	679511	678068	0	0
T4	81115	8061	0	0
T5	53288	53180	0	0
T6	70190	70083	0	0
T7	10345	10224	0	0
T8	1669	1479	0	0
T18	3236	3046	0	0
T25	16072	15951	0	0
T26	2209	1978	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	25527	0	0
T1	500598	86	0	0
T2	371023	569	0	0
T3	75386	144	0	0
T4	81115	26	0	0
T5	60895	10	0	0
T6	14240	12	0	0
T8	1705	0	0	0
T11	0	116	0	0
T12	0	98	0	0
T13	0	24	0	0
T14	0	127	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	150241887	0	0
T1	500598	500060	0	0
T2	371023	370128	0	0
T4	81115	8061	0	0
T5	60895	60785	0	0
T6	14240	14220	0	0
T7	2155	2130	0	0
T8	1705	1511	0	0
T18	919	870	0	0
T25	1507	1496	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152667191	122582	0	0
DstReqKnown_A	207421871	206318332	0	0
SrcAckBusyChk_A	152667191	25527	0	0
SrcBusyKnown_A	152667191	150241887	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	122582	0	0
T1	500598	694	0	0
T2	371023	2902	0	0
T3	75386	366	0	0
T4	81115	213	0	0
T5	60895	83	0	0
T6	14240	36	0	0
T8	1705	0	0	0
T11	0	580	0	0
T12	0	539	0	0
T13	0	84	0	0
T14	0	448	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207421871	206318332	0	0
T1	213011	212880	0	0
T2	339674	339226	0	0
T4	22787	4033	0	0
T5	26618	26590	0	0
T6	35076	35042	0	0
T7	5766	5745	0	0
T8	795	740	0	0
T18	1558	1523	0	0
T25	8397	8376	0	0
T26	1176	1121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	25527	0	0
T1	500598	86	0	0
T2	371023	569	0	0
T3	75386	144	0	0
T4	81115	26	0	0
T5	60895	10	0	0
T6	14240	12	0	0
T8	1705	0	0	0
T11	0	116	0	0
T12	0	98	0	0
T13	0	24	0	0
T14	0	127	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	150241887	0	0
T1	500598	500060	0	0
T2	371023	370128	0	0
T4	81115	8061	0	0
T5	60895	60785	0	0
T6	14240	14220	0	0
T7	2155	2130	0	0
T8	1705	1511	0	0
T18	919	870	0	0
T25	1507	1496	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152667191	193209	0	0
DstReqKnown_A	103710422	103158743	0	0
SrcAckBusyChk_A	152667191	25527	0	0
SrcBusyKnown_A	152667191	150241887	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	193209	0	0
T1	500598	1200	0	0
T2	371023	4639	0	0
T3	75386	398	0	0
T4	81115	353	0	0
T5	60895	153	0	0
T6	14240	50	0	0
T8	1705	0	0	0
T11	0	930	0	0
T12	0	895	0	0
T13	0	119	0	0
T14	0	646	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103710422	103158743	0	0
T1	106505	106440	0	0
T2	169836	169612	0	0
T4	11392	2015	0	0
T5	13309	13295	0	0
T6	17538	17521	0	0
T7	2882	2872	0	0
T8	397	369	0	0
T18	779	762	0	0
T25	4198	4188	0	0
T26	587	559	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	25527	0	0
T1	500598	86	0	0
T2	371023	569	0	0
T3	75386	144	0	0
T4	81115	26	0	0
T5	60895	10	0	0
T6	14240	12	0	0
T8	1705	0	0	0
T11	0	116	0	0
T12	0	98	0	0
T13	0	24	0	0
T14	0	127	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	150241887	0	0
T1	500598	500060	0	0
T2	371023	370128	0	0
T4	81115	8061	0	0
T5	60895	60785	0	0
T6	14240	14220	0	0
T7	2155	2130	0	0
T8	1705	1511	0	0
T18	919	870	0	0
T25	1507	1496	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152667191	85280	0	0
DstReqKnown_A	445279944	440612038	0	0
SrcAckBusyChk_A	152667191	25527	0	0
SrcBusyKnown_A	152667191	150241887	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	85280	0	0
T1	500598	422	0	0
T2	371023	1977	0	0
T3	75386	366	0	0
T4	81115	120	0	0
T5	60895	52	0	0
T6	14240	29	0	0
T8	1705	0	0	0
T11	0	399	0	0
T12	0	361	0	0
T13	0	58	0	0
T14	0	321	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445279944	440612038	0	0
T1	486065	485511	0	0
T2	729447	727656	0	0
T4	84498	8386	0	0
T5	49510	49398	0	0
T6	79117	79005	0	0
T7	10777	10651	0	0
T8	1739	1541	0	0
T18	3347	3149	0	0
T25	16742	16616	0	0
T26	2300	2060	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	25527	0	0
T1	500598	86	0	0
T2	371023	569	0	0
T3	75386	144	0	0
T4	81115	26	0	0
T5	60895	10	0	0
T6	14240	12	0	0
T8	1705	0	0	0
T11	0	116	0	0
T12	0	98	0	0
T13	0	24	0	0
T14	0	127	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	150241887	0	0
T1	500598	500060	0	0
T2	371023	370128	0	0
T4	81115	8061	0	0
T5	60895	60785	0	0
T6	14240	14220	0	0
T7	2155	2130	0	0
T8	1705	1511	0	0
T18	919	870	0	0
T25	1507	1496	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152667191	121771	0	0
DstReqKnown_A	213632817	211395421	0	0
SrcAckBusyChk_A	152667191	25041	0	0
SrcBusyKnown_A	152667191	150241887	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	121771	0	0
T1	500598	696	0	0
T2	371023	2905	0	0
T3	75386	366	0	0
T4	81115	137	0	0
T5	60895	85	0	0
T6	14240	36	0	0
T8	1705	0	0	0
T11	0	696	0	0
T12	0	532	0	0
T13	0	83	0	0
T14	0	448	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213632817	211395421	0	0
T1	230435	230169	0	0
T2	350428	349569	0	0
T4	40559	4025	0	0
T5	26645	26592	0	0
T6	26456	26403	0	0
T7	5173	5113	0	0
T8	834	739	0	0
T18	1653	1558	0	0
T25	8036	7976	0	0
T26	1104	989	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	25041	0	0
T1	500598	86	0	0
T2	371023	569	0	0
T3	75386	144	0	0
T4	81115	14	0	0
T5	60895	10	0	0
T6	14240	12	0	0
T8	1705	0	0	0
T11	0	116	0	0
T12	0	98	0	0
T13	0	24	0	0
T14	0	127	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	150241887	0	0
T1	500598	500060	0	0
T2	371023	370128	0	0
T4	81115	8061	0	0
T5	60895	60785	0	0
T6	14240	14220	0	0
T7	2155	2130	0	0
T8	1705	1511	0	0
T18	919	870	0	0
T25	1507	1496	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T4,T2,T11
1	0	Covered	T5,T6,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152667191	108243	0	0
DstReqKnown_A	416514782	412107842	0	0
SrcAckBusyChk_A	152667191	31213	0	0
SrcBusyKnown_A	152667191	150241887	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	108243	0	0
T1	500598	432	0	0
T2	371023	2060	0	0
T3	75386	369	0	0
T4	81115	298	0	0
T5	60895	52	0	0
T6	14240	29	0	0
T8	1705	0	0	0
T11	0	420	0	0
T12	0	366	0	0
T13	0	60	0	0
T14	0	337	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416514782	412107842	0	0
T1	426291	425761	0	0
T2	679511	678068	0	0
T4	81115	8061	0	0
T5	53288	53180	0	0
T6	70190	70083	0	0
T7	10345	10224	0	0
T8	1669	1479	0	0
T18	3236	3046	0	0
T25	16072	15951	0	0
T26	2209	1978	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	31213	0	0
T1	500598	86	0	0
T2	371023	580	0	0
T3	75386	144	0	0
T4	81115	52	0	0
T5	60895	10	0	0
T6	14240	12	0	0
T8	1705	0	0	0
T11	0	120	0	0
T12	0	98	0	0
T13	0	24	0	0
T14	0	133	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	150241887	0	0
T1	500598	500060	0	0
T2	371023	370128	0	0
T4	81115	8061	0	0
T5	60895	60785	0	0
T6	14240	14220	0	0
T7	2155	2130	0	0
T8	1705	1511	0	0
T18	919	870	0	0
T25	1507	1496	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T4,T2,T11
1	0	Covered	T5,T6,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152667191	154726	0	0
DstReqKnown_A	207421871	206318332	0	0
SrcAckBusyChk_A	152667191	31140	0	0
SrcBusyKnown_A	152667191	150241887	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	154726	0	0
T1	500598	690	0	0
T2	371023	2958	0	0
T3	75386	369	0	0
T4	81115	425	0	0
T5	60895	84	0	0
T6	14240	37	0	0
T8	1705	0	0	0
T11	0	600	0	0
T12	0	536	0	0
T13	0	85	0	0
T14	0	470	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207421871	206318332	0	0
T1	213011	212880	0	0
T2	339674	339226	0	0
T4	22787	4033	0	0
T5	26618	26590	0	0
T6	35076	35042	0	0
T7	5766	5745	0	0
T8	795	740	0	0
T18	1558	1523	0	0
T25	8397	8376	0	0
T26	1176	1121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	31140	0	0
T1	500598	86	0	0
T2	371023	580	0	0
T3	75386	144	0	0
T4	81115	52	0	0
T5	60895	10	0	0
T6	14240	12	0	0
T8	1705	0	0	0
T11	0	120	0	0
T12	0	98	0	0
T13	0	24	0	0
T14	0	133	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	150241887	0	0
T1	500598	500060	0	0
T2	371023	370128	0	0
T4	81115	8061	0	0
T5	60895	60785	0	0
T6	14240	14220	0	0
T7	2155	2130	0	0
T8	1705	1511	0	0
T18	919	870	0	0
T25	1507	1496	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T4,T2,T11
1	0	Covered	T5,T6,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152667191	246667	0	0
DstReqKnown_A	103710422	103158743	0	0
SrcAckBusyChk_A	152667191	31111	0	0
SrcBusyKnown_A	152667191	150241887	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	246667	0	0
T1	500598	1206	0	0
T2	371023	4748	0	0
T3	75386	411	0	0
T4	81115	725	0	0
T5	60895	151	0	0
T6	14240	47	0	0
T8	1705	0	0	0
T11	0	961	0	0
T12	0	886	0	0
T13	0	121	0	0
T14	0	674	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103710422	103158743	0	0
T1	106505	106440	0	0
T2	169836	169612	0	0
T4	11392	2015	0	0
T5	13309	13295	0	0
T6	17538	17521	0	0
T7	2882	2872	0	0
T8	397	369	0	0
T18	779	762	0	0
T25	4198	4188	0	0
T26	587	559	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	31111	0	0
T1	500598	86	0	0
T2	371023	580	0	0
T3	75386	144	0	0
T4	81115	52	0	0
T5	60895	10	0	0
T6	14240	12	0	0
T8	1705	0	0	0
T11	0	120	0	0
T12	0	98	0	0
T13	0	24	0	0
T14	0	133	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	150241887	0	0
T1	500598	500060	0	0
T2	371023	370128	0	0
T4	81115	8061	0	0
T5	60895	60785	0	0
T6	14240	14220	0	0
T7	2155	2130	0	0
T8	1705	1511	0	0
T18	919	870	0	0
T25	1507	1496	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T4,T2,T11
1	0	Covered	T5,T6,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152667191	107156	0	0
DstReqKnown_A	445279944	440612038	0	0
SrcAckBusyChk_A	152667191	31263	0	0
SrcBusyKnown_A	152667191	150241887	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	107156	0	0
T1	500598	423	0	0
T2	371023	2018	0	0
T3	75386	369	0	0
T4	81115	240	0	0
T5	60895	52	0	0
T6	14240	29	0	0
T8	1705	0	0	0
T11	0	416	0	0
T12	0	359	0	0
T13	0	59	0	0
T14	0	337	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445279944	440612038	0	0
T1	486065	485511	0	0
T2	729447	727656	0	0
T4	84498	8386	0	0
T5	49510	49398	0	0
T6	79117	79005	0	0
T7	10777	10651	0	0
T8	1739	1541	0	0
T18	3347	3149	0	0
T25	16742	16616	0	0
T26	2300	2060	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	31263	0	0
T1	500598	86	0	0
T2	371023	580	0	0
T3	75386	144	0	0
T4	81115	52	0	0
T5	60895	10	0	0
T6	14240	12	0	0
T8	1705	0	0	0
T11	0	120	0	0
T12	0	98	0	0
T13	0	24	0	0
T14	0	133	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	150241887	0	0
T1	500598	500060	0	0
T2	371023	370128	0	0
T4	81115	8061	0	0
T5	60895	60785	0	0
T6	14240	14220	0	0
T7	2155	2130	0	0
T8	1705	1511	0	0
T18	919	870	0	0
T25	1507	1496	0	0
T26	2300	2060	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T4,T2,T11
1	0	Covered	T5,T6,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152667191	155713	0	0
DstReqKnown_A	213632817	211395421	0	0
SrcAckBusyChk_A	152667191	30902	0	0
SrcBusyKnown_A	152667191	150241887	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	155713	0	0
T1	500598	699	0	0
T2	371023	2960	0	0
T3	75386	369	0	0
T4	81115	396	0	0
T5	60895	82	0	0
T6	14240	35	0	0
T8	1705	0	0	0
T11	0	720	0	0
T12	0	529	0	0
T13	0	84	0	0
T14	0	470	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213632817	211395421	0	0
T1	230435	230169	0	0
T2	350428	349569	0	0
T4	40559	4025	0	0
T5	26645	26592	0	0
T6	26456	26403	0	0
T7	5173	5113	0	0
T8	834	739	0	0
T18	1653	1558	0	0
T25	8036	7976	0	0
T26	1104	989	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	30902	0	0
T1	500598	86	0	0
T2	371023	580	0	0
T3	75386	144	0	0
T4	81115	50	0	0
T5	60895	10	0	0
T6	14240	12	0	0
T8	1705	0	0	0
T11	0	120	0	0
T12	0	98	0	0
T13	0	24	0	0
T14	0	133	0	0
T18	919	0	0	0
T25	1507	0	0	0
T26	2300	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152667191	150241887	0	0
T1	500598	500060	0	0
T2	371023	370128	0	0
T4	81115	8061	0	0
T5	60895	60785	0	0
T6	14240	14220	0	0
T7	2155	2130	0	0
T8	1705	1511	0	0
T18	919	870	0	0
T25	1507	1496	0	0
T26	2300	2060	0	0