Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

307988064

1

T4

3452

T5

4968

T6

3908

auto[1]

453192

1

T4

82

T6

762

T24

746

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

307995090

1

T4

3104

T5

4968

T6

4070

auto[1]

446166

1

T4

430

T6

600

T24

78

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

307901648

1

T4

3090

T5

4968

T6

3908

auto[1]

539608

1

T4

444

T6

762

T24

432

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

287318482

1

T4

2424

T5

4968

T6

622

auto[1]

21122774

1

T4

1110

T6

4048

T24

2242

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178423540

1

T4

3160

T5

816

T6

3924

auto[1]

130017716

1

T4

374

T5

4152

T6

746

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

163200208

1

T4

1890

T5

816

T6

216

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

123716916

1

T4

214

T5

4152

T6

164

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

35244

1

T4

30

T24

24

T25

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8104

1

T6

8

T24

80

T25

24

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

14538038

1

T4

772

T6

3058

T24

1428

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6175120

1

T4

82

T6

296

T24

254

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

59570

1

T6

52

T24

152

T25

12

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13356

1

T6

28

T24

78

T25

48

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

90838

1

T25

8

T28

4

T17

20

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1868

1

T4

18

T28

18

T47

14

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

13896

1

T25

92

T28

60

T17

74

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3128

1

T47

60

T10

60

T12

102

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

14012

1

T4

84

T6

2

T25

28

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2642

1

T6

30

T24

16

T37

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

23676

1

T6

54

T2

110

T8

82

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5032

1

T24

62

T64

66

T65

92

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

85748

1

T4

26

T24

4

T25

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4774

1

T4

38

T24

48

T28

14

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33180

1

T24

52

T25

122

T28

58

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8164

1

T24

76

T28

78

T10

52

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

34542

1

T4

52

T6

42

T24

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8004

1

T24

24

T15

8

T2

88

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

59422

1

T6

206

T24

82

T27

230

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14700

1

T24

140

T2

90

T48

52

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

45562

1

T4

156

T6

52

T27

88

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6278

1

T6

14

T25

2

T2

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

52492

1

T4

52

T6

116

T27

224

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12082

1

T6

52

T25

44

T2

108

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

51012

1

T4

98

T6

24

T25

56

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12502

1

T4

22

T6

10

T28

18

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

86100

1

T6

102

T25

82

T27

134

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

25046

1

T6

144

T28

52

T2

170