---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_io_div2_meas.u_meas.MaxWidth_A	0	0	245720031	0	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	18571222	0	0	0
tb.dut.u_io_div4_meas.u_meas.MaxWidth_A	0	0	122859369	0	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	18571222	0	0	0
tb.dut.u_io_meas.u_meas.MaxWidth_A	0	0	493198602	0	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	18571222	0	0	0
tb.dut.u_main_meas.u_meas.MaxWidth_A	0	0	525808928	0	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	18571222	0	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	247242891	0	0	1010
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	123620800	0	0	1010
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	496338708	0	0	1010
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	529079981	0	0	1010
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	254091559	0	0	1010
tb.dut.u_usb_meas.u_meas.MaxWidth_A	0	0	252521490	0	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	18571222	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	156077259	153383260	0	0
tb.dut.AllClkBypReqKnownO_A	0	0	156077259	153383260	0	0
tb.dut.CgEnKnownO_A	0	0	156077259	153383260	0	0
tb.dut.ClocksKownO_A	0	0	156077259	153383260	0	0
tb.dut.FpvSecCmClkMainAesCountCheck_A	0	0	156077259	31	0	0
tb.dut.FpvSecCmClkMainHmacCountCheck_A	0	0	156077259	32	0	0
tb.dut.FpvSecCmClkMainKmacCountCheck_A	0	0	156077259	39	0	0
tb.dut.FpvSecCmClkMainOtbnCountCheck_A	0	0	156077259	40	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	156077259	80	0	0
tb.dut.IoClkBypReqKnownO_A	0	0	156077259	153383260	0	0
tb.dut.JitterEnableKnownO_A	0	0	156077259	153383260	0	0
tb.dut.LcCtrlClkBypAckKnownO_A	0	0	156077259	153383260	0	0
tb.dut.PwrMgrKnownO_A	0	0	156077259	153383260	0	0
tb.dut.TlAReadyKnownO_A	0	0	156077259	153383260	0	0
tb.dut.TlDValidKnownO_A	0	0	156077259	153383260	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStart_A	0	0	525809379	3875	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStop_A	0	0	525809379	1955	0	0
tb.dut.clkmgr_aon_cg_aon_peri.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_secure.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_timers.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_div2_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_div4_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_main_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_usb_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOff_A	0	0	245720031	168	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOn_A	0	0	245720031	168	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOff_A	0	0	245720031	7707	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOn_A	0	0	245720031	5249	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOff_A	0	0	122859369	168	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOn_A	0	0	122859369	168	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOff_A	0	0	122859369	7664	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOn_A	0	0	122859369	5206	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOff_A	0	0	122859369	168	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOn_A	0	0	122859369	168	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOff_A	0	0	122859369	168	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOn_A	0	0	122859369	168	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOff_A	0	0	493198602	168	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOn_A	0	0	493198602	157	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOff_A	0	0	493198602	7690	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOn_A	0	0	493198602	5221	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOff_A	0	0	525808928	4033	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOn_A	0	0	525808928	4030	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOff_A	0	0	525808928	4011	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOn_A	0	0	525808928	4008	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOff_A	0	0	525808928	158	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOn_A	0	0	525808928	155	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOff_A	0	0	525808928	4065	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOn_A	0	0	525808928	4062	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOff_A	0	0	525808928	4043	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOn_A	0	0	525808928	4040	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOff_A	0	0	525808928	158	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOn_A	0	0	525808928	155	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOff_A	0	0	252521490	7638	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOn_A	0	0	252521490	5169	0	0
tb.dut.clkmgr_csr_assert.TlulOOBAddrErr_A	0	0	157019298	4671187	0	0
tb.dut.clkmgr_csr_assert.clk_enables_rd_A	0	0	157019298	60014	0	0
tb.dut.clkmgr_csr_assert.clk_hints_rd_A	0	0	157019298	52845	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_rd_A	0	0	157019298	65578	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_regwen_rd_A	0	0	157019298	50747	0	0
tb.dut.clkmgr_csr_assert.jitter_enable_rd_A	0	0	157019298	71764	0	0
tb.dut.clkmgr_csr_assert.jitter_regwen_rd_A	0	0	157019298	56397	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Stepped_A	0	0	493199037	4625	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Whole_A	0	0	493199037	5383	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Stepped_A	0	0	245720438	4540	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Whole_A	0	0	245720438	5112	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqFall_A	0	0	156077259	4233	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqRise_A	0	0	156077259	4233	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelFall_A	0	0	156077259	2538	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelRise_A	0	0	156077259	2538	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqFall_A	0	0	156077259	5284	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqRise_A	0	0	156077259	5284	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStart_A	0	0	525809379	3853	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStop_A	0	0	525809379	1962	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateClose_A	0	0	245720438	3403	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateOpen_A	0	0	245720438	3403	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateClose_A	0	0	122859770	3373	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateOpen_A	0	0	122859770	3373	0	0
tb.dut.clkmgr_io_peri_sva_if.GateClose_A	0	0	493199037	3435	0	0
tb.dut.clkmgr_io_peri_sva_if.GateOpen_A	0	0	493199037	3435	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStart_A	0	0	525809379	3907	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStop_A	0	0	525809379	1991	0	0
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if.CtrlEnOn_A	0	0	156077259	11037	0	0
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if.CtrlEnOn_A	0	0	156077259	14919	0	0
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if.CtrlEnOn_A	0	0	156077259	22701	0	0
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if.CtrlEnOn_A	0	0	156077259	10785	0	0
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	156077259	16144241	0	61
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if.CtrlEnOn_A	0	0	156077259	14956	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStart_A	0	0	525809379	3885	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStop_A	0	0	525809379	1978	0	0
tb.dut.clkmgr_pwrmgr_sva_if.IoStatusFall_A	0	0	156077259	157	0	0
tb.dut.clkmgr_pwrmgr_sva_if.IoStatusRise_A	0	0	156077259	157	0	0
tb.dut.clkmgr_pwrmgr_sva_if.MainStatusFall_A	0	0	156077259	154	0	0
tb.dut.clkmgr_pwrmgr_sva_if.MainStatusRise_A	0	0	156077259	154	0	0
tb.dut.clkmgr_pwrmgr_sva_if.UsbStatusFall_A	0	0	156077259	148	0	0
tb.dut.clkmgr_pwrmgr_sva_if.UsbStatusRise_A	0	0	156077259	148	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqFalse_A	0	0	156077259	153235127	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqTrue_A	0	0	156077259	145664	0	0
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	156077259	153149257	0	2415
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqTrue_A	0	0	156077259	226596	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckFalse_A	0	0	156077259	153246822	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckTrue_A	0	0	156077259	133969	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateClose_A	0	0	252521901	3393	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateOpen_A	0	0	252521901	3393	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	157019298	18434467	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	157019298	154220628	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	157019298	154220628	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	157019298	22403231	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	157019298	154220628	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	157019298	154220628	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
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tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	157019937	15175842	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	157019298	2519579	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	157019937	217643	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	157019937	152942	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	157019298	2787095	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	157019937	18434467	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	157019937	22403231	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	157019937	18434467	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	157019937	22403231	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	157019937	22403231	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	157019937	22403231	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	157019298	1501738	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	157019298	1143255	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1010	1010	0	0
tb.dut.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_calib_rdy_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_clk_io_div2_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	156077259	153383260	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	156077259	153383260	0	0
tb.dut.u_clk_io_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_peri_scanmode_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_clk_io_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	156077259	153383260	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	525808928	520748747	0	2415
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	525808928	32317	0	0
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	525808928	520748747	0	2415
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	525808928	32465	0	0
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	525808928	520748747	0	2415
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	525808928	32717	0	0
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	525808928	520748747	0	2415
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	525808928	32568	0	0
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	525808928	520756218	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	156077259	153383260	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	156077259	20025	0	0
tb.dut.u_clkmgr_byp.u_all_byp_req.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_clkmgr_byp.u_en_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_en_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_clkmgr_byp.u_hi_speed_sel.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	156077259	17543	0	0
tb.dut.u_clkmgr_byp.u_io_byp_req.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_io_div2_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_div_scanmode_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_io_div2_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	156077259	153383260	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	156077259	3009	0	0
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckHoldReq	0	0	245720031	3009	0	0
tb.dut.u_io_div2_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	245720031	4114137	0	0
tb.dut.u_io_div2_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	245720031	97487	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	18210376	96745	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	245720031	245720031	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	245720031	245720031	0	0
tb.dut.u_io_div4_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_div_scanmode_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_io_div4_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	156077259	153383260	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	156077259	2899	0	0
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckHoldReq	0	0	122859369	2899	0	0
tb.dut.u_io_div4_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	122859369	3925361	0	0
tb.dut.u_io_div4_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	122859369	95952	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	18210376	95219	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	122859369	122859369	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	122859369	122859369	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_io_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	156077259	3233	0	0
tb.dut.u_io_meas.u_err_sync.SyncReqAckHoldReq	0	0	493198602	3233	0	0
tb.dut.u_io_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	493198602	4114248	0	0
tb.dut.u_io_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	493198602	98525	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	18210376	97780	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	493198602	490785204	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	493198602	490785204	0	0
tb.dut.u_io_step_down_req_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_step_down_req_sync.OutputsKnown_A	0	0	493198602	488410110	0	0
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	493198602	488402703	0	2415
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	493198602	28039	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_main_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	156077259	2752	0	0
tb.dut.u_main_meas.u_err_sync.SyncReqAckHoldReq	0	0	525808928	2752	0	0
tb.dut.u_main_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	525808928	4118877	0	0
tb.dut.u_main_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	525808928	118412	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	18555821	118031	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	525808928	523262921	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	525808928	523262921	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.DivEven_A	0	0	805	805	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown0	0	0	245393198	245392393	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown1	0	0	493198602	493197797	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	245720031	245719226	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	493198602	493197797	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.DivEven_A	0	0	805	805	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	122859369	122858564	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	493198602	493197797	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.OutputsKnown_A	0	0	245720031	244532028	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.OutputsKnown_A	0	0	245720031	244532028	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.OutputsKnown_A	0	0	122859369	122265416	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.OutputsKnown_A	0	0	122859369	122265416	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.OutputsKnown_A	0	0	122859369	122265416	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.OutputsKnown_A	0	0	122859369	122265416	0	0
tb.dut.u_prim_mubi4_sender_clk_io_infra.OutputsKnown_A	0	0	493198602	488410110	0	0
tb.dut.u_prim_mubi4_sender_clk_io_peri.OutputsKnown_A	0	0	493198602	488410110	0	0
tb.dut.u_prim_mubi4_sender_clk_main_infra.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_prim_mubi4_sender_clk_main_secure.OutputsKnown_A	0	0	525808928	520756218	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_infra.OutputsKnown_A	0	0	252521490	250094959	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_peri.OutputsKnown_A	0	0	252521490	250094959	0	0
tb.dut.u_reg.en2addrHit	0	0	157019298	801033	0	0
tb.dut.u_reg.reAfterRv	0	0	157019298	801033	0	0
tb.dut.u_reg.rePulse	0	0	157019298	192123	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	157019298	128524	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.DstReqKnown_A	0	0	247242891	246006896	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	157019298	25517	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	157019298	154220628	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	247242891	1145	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	157019298	26662	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	247242891	25513	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	247242891	25517	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	157019298	25517	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	157019298	158193	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	247242891	246006896	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	157019298	31477	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	157019298	154220628	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	157019298	31473	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	247242891	31482	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	247242891	31481	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	157019298	31516	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	247242891	246006896	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	157019298	38	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	247242891	38	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	247242891	246006896	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	157019298	37	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	247242891	37	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	157019298	205200	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.DstReqKnown_A	0	0	123620800	123002889	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	157019298	25517	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	157019298	154220628	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	123620800	1145	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	157019298	26662	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	123620800	25482	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	123620800	25517	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	157019298	25517	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	157019298	251537	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	123620800	123002889	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	157019298	31470	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	157019298	154220628	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	157019298	31470	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	123620800	31476	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	123620800	31472	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	157019298	31508	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	123620800	123002889	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	157019298	33	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	123620800	33	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	123620800	123002889	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	157019298	23	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	123620800	23	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	157019298	90236	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.DstReqKnown_A	0	0	496338708	491359868	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	157019298	25517	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	157019298	154220628	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	496338708	1145	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	157019298	26662	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	496338708	25517	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	496338708	25517	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	157019298	25517	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	157019298	110941	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	496338708	491359868	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	157019298	31495	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	157019298	154220628	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	157019298	31493	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	496338708	31511	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	496338708	31506	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	157019298	31518	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	496338708	491359868	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	157019298	36	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	496338708	36	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	496338708	491359868	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	157019298	25	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	496338708	25	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	157019298	88080	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.DstReqKnown_A	0	0	529079981	523829037	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	157019298	25517	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	157019298	154220628	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	529079981	1145	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	157019298	26662	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	529079981	25517	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	529079981	25517	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	157019298	25517	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	157019298	108888	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	529079981	523829037	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	157019298	31638	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	157019298	154220628	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	157019298	31635	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	529079981	31651	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	529079981	31649	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	157019298	31661	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	529079981	523829037	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	157019298	40	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	529079981	40	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	529079981	523829037	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	157019298	35	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	529079981	35	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	157019298	126299	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.DstReqKnown_A	0	0	254091559	251569914	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	157019298	24950	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	157019298	154220628	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	254091559	1145	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	157019298	26095	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	254091559	24833	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	254091559	25013	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	157019298	25517	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	157019298	157117	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	254091559	251569914	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	157019298	31139	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	157019298	154220628	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	157019298	31095	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	254091559	31292	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	254091559	31253	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	157019298	31426	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	254091559	251569914	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	157019298	29	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	254091559	29	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	254091559	251569914	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	157019298	38	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	254091559	38	0	0
tb.dut.u_reg.wePulse	0	0	157019298	608910	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	156077259	153383260	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_usb_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	156077259	2596	0	0
tb.dut.u_usb_meas.u_err_sync.SyncReqAckHoldReq	0	0	252521490	2596	0	0
tb.dut.u_usb_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	252521490	4118874	0	0
tb.dut.u_usb_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	252521490	117187	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	18495697	117021	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	252521490	251301508	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	252521490	251301508	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	156077259	16144241	0	61
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	156077259	153149257	0	2415
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	525808928	520748747	0	2415
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	525808928	520748747	0	2415
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	525808928	520748747	0	2415
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	525808928	520748747	0	2415
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	493198602	488402703	0	2415
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	247242891	0	0	1010
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	123620800	0	0	1010
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	496338708	0	0	1010
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	529079981	0	0	1010
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	254091559	0	0	1010
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	156077259	153375630	0	2415

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	157019937	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	157019937	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	157019937	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	157019937	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	157019937	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	157019937	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	157019937	7099	7099	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	157019937	2577	2577	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	157019937	11919	11919	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	157019937	96082	96082	756

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	157019937	7099	7099	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	157019937	2577	2577	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	157019937	11919	11919	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	157019937	96082	96082	756