Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1047905	0	0
SrcPulseCheck_M	2147483647	1046622	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1047905
T1	3564767	8161
T2	1989679	6501
T3	0	1258
T4	88033	58
T5	94731	40
T7	20088	0
T8	0	80
T11	0	5293
T12	0	293
T13	0	144
T14	0	7567
T18	9787	0
T19	8478	0
T20	18219	0
T24	0	468
T25	16897	0
T26	29518	0
T27	0	308
T29	0	130
T56	7005	2
T58	5348	1
T60	3369	1
T61	21812	1
T62	23388	1
T63	5596	1
T108	34476	2
T109	9676	1
T110	12304	0
T111	29038	0
T112	3049	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1046622
T1	2658988	8161
T2	1675632	6501
T3	0	1258
T4	22038	58
T5	34415	40
T7	6508	0
T8	0	80
T11	0	5207
T12	0	293
T13	0	144
T14	0	7567
T18	5861	0
T19	5103	0
T20	7607	0
T24	0	468
T25	7150	0
T26	9499	0
T27	0	308
T29	0	130
T56	13257	2
T58	9914	1
T60	3615	1
T61	9054	1
T62	222654	1
T63	11932	1
T108	15204	2
T109	4396	1
T110	21908	0
T111	12200	0
T112	5569	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	669632172	28097	0	0
SrcPulseCheck_M	184902954	28097	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	669632172	28097
T1	852041	462
T2	405782	368
T3	0	54
T4	21816	4
T5	25818	8
T7	4980	0
T8	0	16
T11	0	280
T12	0	20
T18	2054	0
T19	1798	0
T20	4118	0
T24	0	20
T25	3982	0
T26	6904	0
T29	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	184902954	28097
T1	311359	462
T2	440703	368
T3	0	54
T4	5453	4
T5	12909	8
T7	1296	0
T8	0	16
T11	0	280
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	669632172	33738	0	0
SrcPulseCheck_M	184902954	33743	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	669632172	33738
T1	852041	466
T2	405782	378
T3	0	54
T4	21816	4
T5	25818	16
T7	4980	0
T8	0	32
T11	0	287
T12	0	20
T18	2054	0
T19	1798	0
T20	4118	0
T24	0	20
T25	3982	0
T26	6904	0
T29	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	184902954	33743
T1	311359	466
T2	440703	378
T3	0	54
T4	5453	4
T5	12909	16
T7	1296	0
T8	0	32
T11	0	287
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	52

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	33726	0	0
SrcPulseCheck_M	669632172	33739	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	33726
T1	311359	466
T2	440703	378
T3	0	54
T4	5453	4
T5	12909	16
T7	1296	0
T8	0	32
T11	0	287
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	669632172	33739
T1	852041	466
T2	405782	378
T3	0	54
T4	21816	4
T5	25818	16
T7	4980	0
T8	0	32
T11	0	287
T12	0	20
T18	2054	0
T19	1798	0
T20	4118	0
T24	0	20
T25	3982	0
T26	6904	0
T29	0	52

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	334082028	28097	0	0
SrcPulseCheck_M	184902954	28097	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	334082028	28097
T1	426342	462
T2	202426	368
T3	0	54
T4	10868	4
T5	8317	8
T7	2464	0
T8	0	16
T11	0	280
T12	0	20
T18	987	0
T19	839	0
T20	2203	0
T24	0	20
T25	1924	0
T26	3893	0
T29	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	184902954	28097
T1	311359	462
T2	440703	368
T3	0	54
T4	5453	4
T5	12909	8
T7	1296	0
T8	0	16
T11	0	280
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	334082028	33565	0	0
SrcPulseCheck_M	184902954	33589	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	334082028	33565
T1	426342	466
T2	202426	378
T3	0	54
T4	10868	4
T5	8317	16
T7	2464	0
T8	0	32
T11	0	287
T12	0	20
T18	987	0
T19	839	0
T20	2203	0
T24	0	20
T25	1924	0
T26	3893	0
T29	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	184902954	33589
T1	311359	466
T2	440703	378
T3	0	54
T4	5453	4
T5	12909	16
T7	1296	0
T8	0	32
T11	0	287
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	52

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	33562	0	0
SrcPulseCheck_M	334082028	33568	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	33562
T1	311359	466
T2	440703	378
T3	0	54
T4	5453	4
T5	12909	16
T7	1296	0
T8	0	32
T11	0	287
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	334082028	33568
T1	426342	466
T2	202426	378
T3	0	54
T4	10868	4
T5	8317	16
T7	2464	0
T8	0	32
T11	0	287
T12	0	20
T18	987	0
T19	839	0
T20	2203	0
T24	0	20
T25	1924	0
T26	3893	0
T29	0	52

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	167040331	28097	0	0
SrcPulseCheck_M	184902954	28097	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	167040331	28097
T1	213170	462
T2	101213	368
T3	0	54
T4	5434	4
T5	4159	8
T7	1232	0
T8	0	16
T11	0	280
T12	0	20
T18	494	0
T19	419	0
T20	1101	0
T24	0	20
T25	962	0
T26	1946	0
T29	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	184902954	28097
T1	311359	462
T2	440703	368
T3	0	54
T4	5453	4
T5	12909	8
T7	1296	0
T8	0	16
T11	0	280
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	26

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	167040331	33743	0	0
SrcPulseCheck_M	184902954	33790	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	167040331	33743
T1	213170	466
T2	101213	378
T3	0	54
T4	5434	4
T5	4159	16
T7	1232	0
T8	0	32
T11	0	287
T12	0	20
T18	494	0
T19	419	0
T20	1101	0
T24	0	20
T25	962	0
T26	1946	0
T29	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	184902954	33790
T1	311359	466
T2	440703	378
T3	0	54
T4	5453	4
T5	12909	16
T7	1296	0
T8	0	32
T11	0	287
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	52

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	33743	0	0
SrcPulseCheck_M	167040331	33750	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	33743
T1	311359	466
T2	440703	378
T3	0	54
T4	5453	4
T5	12909	16
T7	1296	0
T8	0	32
T11	0	287
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	167040331	33750
T1	213170	466
T2	101213	378
T3	0	54
T4	5434	4
T5	4159	16
T7	1232	0
T8	0	32
T11	0	287
T12	0	20
T18	494	0
T19	419	0
T20	1101	0
T24	0	20
T25	962	0
T26	1946	0
T29	0	52

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	709822792	28097	0	0
SrcPulseCheck_M	184902954	28097	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	709822792	28097
T1	909171	462
T2	434703	368
T3	0	54
T4	22726	4
T5	26894	8
T7	5188	0
T8	0	16
T11	0	280
T12	0	20
T18	2139	0
T19	1872	0
T20	4289	0
T24	0	20
T25	4148	0
T26	7192	0
T29	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	184902954	28097
T1	311359	462
T2	440703	368
T3	0	54
T4	5453	4
T5	12909	8
T7	1296	0
T8	0	16
T11	0	280
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	26

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	709822792	33742	0	0
SrcPulseCheck_M	184902954	33762	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	709822792	33742
T1	909171	466
T2	434703	378
T3	0	54
T4	22726	4
T5	26894	16
T7	5188	0
T8	0	32
T11	0	287
T12	0	20
T18	2139	0
T19	1872	0
T20	4289	0
T24	0	20
T25	4148	0
T26	7192	0
T29	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	184902954	33762
T1	311359	466
T2	440703	378
T3	0	54
T4	5453	4
T5	12909	16
T7	1296	0
T8	0	32
T11	0	287
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	52

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	33726	0	0
SrcPulseCheck_M	709822792	33747	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	33726
T1	311359	466
T2	440703	378
T3	0	54
T4	5453	4
T5	12909	16
T7	1296	0
T8	0	32
T11	0	287
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	709822792	33747
T1	909171	466
T2	434703	378
T3	0	54
T4	22726	4
T5	26894	16
T7	5188	0
T8	0	32
T11	0	287
T12	0	20
T18	2139	0
T19	1872	0
T20	4289	0
T24	0	20
T25	4148	0
T26	7192	0
T29	0	52

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	341024541	27724	0	0
SrcPulseCheck_M	184902954	28097	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	341024541	27724
T1	436121	462
T2	208017	368
T3	0	54
T4	10908	4
T5	12909	4
T7	2490	0
T8	0	8
T11	0	280
T12	0	20
T18	1026	0
T19	899	0
T20	2059	0
T24	0	20
T25	1991	0
T26	3452	0
T29	0	26

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	184902954	28097
T1	311359	462
T2	440703	368
T3	0	54
T4	5453	4
T5	12909	8
T7	1296	0
T8	0	16
T11	0	280
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	26

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	341024541	33436	0	0
SrcPulseCheck_M	184902954	33576	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	341024541	33436
T1	436121	466
T2	208017	378
T3	0	54
T4	10908	4
T5	12909	16
T7	2490	0
T8	0	24
T11	0	287
T12	0	20
T18	1026	0
T19	899	0
T20	2059	0
T24	0	20
T25	1991	0
T26	3452	0
T29	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	184902954	33576
T1	311359	466
T2	440703	378
T3	0	54
T4	5453	4
T5	12909	16
T7	1296	0
T8	0	32
T11	0	287
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	52

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	33317	0	0
SrcPulseCheck_M	341024541	33473	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	33317
T1	311359	466
T2	440703	378
T3	0	54
T4	5453	4
T5	12909	14
T7	1296	0
T8	0	24
T11	0	287
T12	0	20
T18	2139	0
T19	1872	0
T20	2102	0
T24	0	20
T25	2033	0
T26	1797	0
T29	0	39

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	341024541	33473
T1	436121	466
T2	208017	378
T3	0	54
T4	10908	4
T5	12909	16
T7	2490	0
T8	0	24
T11	0	287
T12	0	20
T18	1026	0
T19	899	0
T20	2059	0
T24	0	20
T25	1991	0
T26	3452	0
T29	0	52

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T55,T56,T57
1	0	Covered	T55,T56,T57
1	1	Covered	T59,T113,T114

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T55,T56,T57
1	0	Covered	T59,T113,T114
1	1	Covered	T55,T56,T57

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	33	0	0
SrcPulseCheck_M	669632172	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	33
T55	4148	1
T56	7005	2
T57	7270	1
T58	5348	1
T59	8449	3
T61	10906	1
T63	2798	1
T108	17238	1
T111	14519	1
T115	5216	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	669632172	33
T55	7964	1
T56	28021	2
T57	63442	1
T58	21392	1
T59	15304	3
T61	10793	1
T63	12788	1
T108	17059	1
T111	13937	1
T115	5007	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T56,T57,T58
1	0	Covered	T56,T57,T58
1	1	Covered	T59,T112,T114

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T56,T57,T58
1	0	Covered	T59,T112,T114
1	1	Covered	T56,T57,T58

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	33	0	0
SrcPulseCheck_M	669632172	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	33
T56	7005	1
T57	7270	1
T58	5348	1
T59	8449	4
T61	10906	1
T62	11694	1
T63	2798	1
T108	17238	1
T110	6152	1
T115	5216	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	669632172	33
T56	28021	1
T57	63442	1
T58	21392	1
T59	15304	4
T61	10793	1
T62	224517	1
T63	12788	1
T108	17059	1
T110	23625	1
T115	5007	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T56,T60,T58
1	0	Covered	T56,T60,T58
1	1	Covered	T112,T116,T113

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T56,T60,T58
1	0	Covered	T112,T116,T113
1	1	Covered	T56,T60,T58

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	35	0	0
SrcPulseCheck_M	334082028	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	35
T56	7005	2
T58	5348	1
T60	3369	1
T61	10906	1
T62	11694	1
T63	2798	1
T108	17238	2
T109	4838	1
T110	6152	1
T111	14519	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	334082028	35
T56	13257	2
T58	9914	1
T60	3615	1
T61	4527	1
T62	111327	1
T63	5966	1
T108	7602	2
T109	2198	1
T110	10954	1
T111	6100	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T61,T62,T63
1	0	Covered	T61,T62,T63
1	1	Covered	T61,T112,T116

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T61,T62,T63
1	0	Covered	T61,T112,T116
1	1	Covered	T61,T62,T63

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	31	0	0
SrcPulseCheck_M	334082028	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	31
T61	10906	2
T62	11694	2
T63	2798	1
T108	17238	1
T109	4838	1
T110	6152	1
T111	14519	1
T112	3049	4
T116	6995	3
T117	7042	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	334082028	31
T61	4527	2
T62	111327	2
T63	5966	1
T108	7602	1
T109	2198	1
T110	10954	1
T111	6100	1
T112	5569	4
T116	6142	3
T117	2733	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T55,T56,T60
1	0	Covered	T55,T56,T60
1	1	Covered	T56,T59,T109

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T55,T56,T60
1	0	Covered	T56,T59,T109
1	1	Covered	T55,T56,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	34	0	0
SrcPulseCheck_M	167040331	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	34
T55	4148	1
T56	7005	3
T59	8449	2
T60	3369	1
T61	10906	3
T109	4838	2
T115	5216	1
T116	6995	3
T118	2346	1
T119	5980	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	167040331	34
T55	1761	1
T56	6627	3
T59	3444	2
T60	1806	1
T61	2262	3
T109	1101	2
T115	1072	1
T116	3067	3
T118	6915	1
T119	5493	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T55,T56,T60
1	0	Covered	T55,T56,T60
1	1	Covered	T56,T59,T109

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T55,T56,T60
1	0	Covered	T56,T59,T109
1	1	Covered	T55,T56,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	42	0	0
SrcPulseCheck_M	167040331	42	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	42
T55	4148	1
T56	7005	3
T58	5348	2
T59	8449	2
T60	3369	1
T61	10906	3
T63	2798	1
T109	4838	2
T115	5216	1
T120	3116	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	167040331	42
T55	1761	1
T56	6627	3
T58	4956	2
T59	3444	2
T60	1806	1
T61	2262	3
T63	2982	1
T109	1101	2
T115	1072	1
T120	3256	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T55,T56,T60
1	0	Covered	T55,T56,T60
1	1	Covered	T56,T58,T61

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T55,T56,T60
1	0	Covered	T56,T58,T61
1	1	Covered	T55,T56,T60

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	44	0	0
SrcPulseCheck_M	709822792	44	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	44
T55	4148	1
T56	7005	2
T58	5348	4
T60	3369	1
T61	10906	3
T62	11694	1
T63	2798	1
T108	17238	1
T109	4838	1
T115	5216	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	709822792	44
T55	8297	1
T56	29191	2
T58	22284	4
T60	8641	1
T61	11244	3
T62	233879	1
T63	13323	1
T108	17770	1
T109	5376	1
T115	5216	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T55,T56,T58
1	0	Covered	T55,T56,T58
1	1	Covered	T58,T61,T109

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T55,T56,T58
1	0	Covered	T58,T61,T109
1	1	Covered	T55,T56,T58

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	33	0	0
SrcPulseCheck_M	709822792	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	33
T55	4148	1
T56	7005	1
T58	5348	2
T59	8449	1
T61	10906	3
T62	11694	1
T63	2798	1
T109	4838	2
T110	6152	1
T115	5216	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	709822792	33
T55	8297	1
T56	29191	1
T58	22284	2
T59	15943	1
T61	11244	3
T62	233879	1
T63	13323	1
T109	5376	2
T110	24611	1
T115	5216	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T60,T58,T59
1	0	Covered	T60,T58,T59
1	1	Covered	T108,T109,T112

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T60,T58,T59
1	0	Covered	T108,T109,T112
1	1	Covered	T60,T58,T59

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	33	0	0
SrcPulseCheck_M	341024541	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	33
T58	5348	1
T59	8449	1
T60	3369	1
T61	10906	2
T62	11694	1
T108	17238	2
T109	4838	2
T112	3049	4
T116	6995	1
T121	16421	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	341024541	33
T58	10696	1
T59	7652	1
T60	4148	1
T61	5397	2
T62	112263	1
T108	8529	2
T109	2580	2
T112	5855	4
T116	6995	1
T121	8126	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T60,T58,T59
1	0	Covered	T60,T58,T59
1	1	Covered	T59,T109,T112

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T60,T58,T59
1	0	Covered	T59,T109,T112
1	1	Covered	T60,T58,T59

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	184902954	31	0	0
SrcPulseCheck_M	341024541	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	184902954	31
T58	5348	2
T59	8449	4
T60	3369	1
T61	10906	3
T108	17238	1
T109	4838	2
T110	6152	1
T112	3049	3
T116	6995	1
T121	16421	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	341024541	31
T58	10696	2
T59	7652	4
T60	4148	1
T61	5397	3
T108	8529	1
T109	2580	2
T110	11813	1
T112	5855	3
T116	6995	1
T121	8126	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T24
1	1	Covered	T4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	667037787	107004	0	0
SrcPulseCheck_M	26366072	106544	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	667037787	107004
T1	852041	1584
T2	405782	1285
T3	0	256
T4	21816	12
T5	25818	0
T7	4980	0
T11	0	1107
T12	0	61
T13	0	36
T14	0	1744
T18	2054	0
T19	1798	0
T20	4118	0
T24	0	108
T25	3982	0
T26	6904	0
T27	0	77

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	26366072	106544
T1	402374	1584
T2	147890	1285
T3	0	256
T4	66	12
T5	70	0
T7	363	0
T11	0	1107
T12	0	61
T13	0	36
T14	0	1744
T18	149	0
T19	130	0
T20	300	0
T24	0	108
T25	290	0
T26	503	0
T27	0	77

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T24
1	1	Covered	T4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	332829027	105972	0	0
SrcPulseCheck_M	26366072	105514	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	332829027	105972
T1	426342	1584
T2	202426	1285
T3	0	256
T4	10868	12
T5	8317	0
T7	2464	0
T11	0	1095
T12	0	58
T13	0	36
T14	0	1734
T18	987	0
T19	839	0
T20	2203	0
T24	0	108
T25	1924	0
T26	3893	0
T27	0	77

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	26366072	105514
T1	402374	1584
T2	147890	1285
T3	0	256
T4	66	12
T5	70	0
T7	363	0
T11	0	1095
T12	0	58
T13	0	36
T14	0	1734
T18	149	0
T19	130	0
T20	300	0
T24	0	108
T25	290	0
T26	503	0
T27	0	77

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T24
1	1	Covered	T4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166413837	104450	0	0
SrcPulseCheck_M	26366072	103996	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166413837	104450
T1	213170	1584
T2	101213	1285
T3	0	256
T4	5434	12
T5	4159	0
T7	1232	0
T11	0	1035
T12	0	57
T13	0	36
T14	0	1721
T18	494	0
T19	419	0
T20	1101	0
T24	0	108
T25	962	0
T26	1946	0
T27	0	77

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	26366072	103996
T1	402374	1584
T2	147890	1285
T3	0	256
T4	66	12
T5	70	0
T7	363	0
T11	0	1035
T12	0	57
T13	0	36
T14	0	1721
T18	149	0
T19	130	0
T20	300	0
T24	0	108
T25	290	0
T26	503	0
T27	0	77

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	707120195	127135	0	0
SrcPulseCheck_M	26367939	126688	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	707120195	127135
T1	909171	2015
T2	434703	1522
T3	0	328
T4	22726	10
T5	26894	0
T7	5188	0
T11	0	1202
T12	0	57
T13	0	36
T14	0	2368
T18	2139	0
T19	1872	0
T20	4289	0
T24	0	84
T25	4148	0
T26	7192	0
T27	0	77

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	26367939	126688
T1	402806	2015
T2	148130	1522
T3	0	328
T4	66	10
T5	70	0
T7	363	0
T11	0	1116
T12	0	57
T13	0	36
T14	0	2368
T18	149	0
T19	130	0
T20	300	0
T24	0	84
T25	290	0
T26	503	0
T27	0	77

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T4,T7
0	Covered	T6,T4,T7

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	339727317	126585	0	0
SrcPulseCheck_M	26343979	126309	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	339727317	126585
T1	436121	1999
T2	208017	1495
T3	0	352
T4	10908	10
T5	12909	0
T7	2490	0
T11	0	1140
T12	0	56
T13	0	36
T14	0	2408
T18	1026	0
T19	899	0
T20	2059	0
T24	0	156
T25	1991	0
T26	3452	0
T27	0	77

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	26343979	126309
T1	402794	1999
T2	100299	1435
T3	0	352
T4	66	10
T5	70	0
T7	363	0
T11	0	1140
T12	0	56
T13	0	36
T14	0	2408
T18	149	0
T19	130	0
T20	300	0
T24	0	156
T25	290	0
T26	503	0
T27	0	77

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb