Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1849029540	1468264	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1849029540	308160	0	0
SrcBusyKnown_A	1849029540	1826407800	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1849029540	1468264	0	0
T1	3113590	19024	0	0
T2	4407030	32038	0	0
T3	0	4489	0	0
T4	54530	136	0	0
T5	129090	599	0	0
T7	12960	0	0	0
T8	0	1848	0	0
T11	0	9925	0	0
T12	0	525	0	0
T18	21390	0	0	0
T19	18720	0	0	0
T20	21020	0	0	0
T24	0	1312	0	0
T25	20330	0	0	0
T26	17970	0	0	0
T29	0	910	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5673690	5669896	0	0
T4	143504	142378	0	0
T5	156194	29592	0	0
T6	123052	121904	0	0
T7	32708	31626	0	0
T18	13400	12272	0	0
T19	11654	10316	0	0
T20	27540	26160	0	0
T25	26014	24788	0	0
T26	46774	46076	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1849029540	308160	0	0
T1	3113590	4640	0	0
T2	4407030	3730	0	0
T3	0	540	0	0
T4	54530	40	0	0
T5	129090	114	0	0
T7	12960	0	0	0
T8	0	224	0	0
T11	0	2835	0	0
T12	0	200	0	0
T18	21390	0	0	0
T19	18720	0	0	0
T20	21020	0	0	0
T24	0	200	0	0
T25	20330	0	0	0
T26	17970	0	0	0
T29	0	370	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1849029540	1826407800	0	0
T1	3113590	3111340	0	0
T4	54530	54060	0	0
T5	129090	22480	0	0
T6	11680	11570	0	0
T7	12960	12510	0	0
T18	21390	19420	0	0
T19	18720	16320	0	0
T20	21020	19840	0	0
T25	20330	19220	0	0
T26	17970	17660	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	184902954	94169	0	0
DstReqKnown_A	669632172	665310889	0	0
SrcAckBusyChk_A	184902954	28097	0	0
SrcBusyKnown_A	184902954	182640780	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	94169	0	0
T1	311359	1414	0	0
T2	440703	1940	0	0
T3	0	281	0	0
T4	5453	10	0	0
T5	12909	28	0	0
T7	1296	0	0	0
T8	0	79	0	0
T11	0	731	0	0
T12	0	50	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	83	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	62	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669632172	665310889	0	0
T1	852041	851405	0	0
T4	21816	21627	0	0
T5	25818	4494	0	0
T6	18707	18517	0	0
T7	4980	4804	0	0
T18	2054	1864	0	0
T19	1798	1567	0	0
T20	4118	3887	0	0
T25	3982	3765	0	0
T26	6904	6783	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	28097	0	0
T1	311359	462	0	0
T2	440703	368	0	0
T3	0	54	0	0
T4	5453	4	0	0
T5	12909	8	0	0
T7	1296	0	0	0
T8	0	16	0	0
T11	0	280	0	0
T12	0	20	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	20	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	182640780	0	0
T1	311359	311134	0	0
T4	5453	5406	0	0
T5	12909	2248	0	0
T6	1168	1157	0	0
T7	1296	1251	0	0
T18	2139	1942	0	0
T19	1872	1632	0	0
T20	2102	1984	0	0
T25	2033	1922	0	0
T26	1797	1766	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	184902954	132431	0	0
DstReqKnown_A	334082028	333007217	0	0
SrcAckBusyChk_A	184902954	28097	0	0
SrcBusyKnown_A	184902954	182640780	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	132431	0	0
T1	311359	1885	0	0
T2	440703	3092	0	0
T3	0	448	0	0
T4	5453	14	0	0
T5	12909	40	0	0
T7	1296	0	0	0
T8	0	127	0	0
T11	0	1010	0	0
T12	0	50	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	130	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	62	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334082028	333007217	0	0
T1	426342	426155	0	0
T4	10868	10813	0	0
T5	8317	2248	0	0
T6	9320	9258	0	0
T7	2464	2402	0	0
T18	987	932	0	0
T19	839	784	0	0
T20	2203	2134	0	0
T25	1924	1883	0	0
T26	3893	3865	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	28097	0	0
T1	311359	462	0	0
T2	440703	368	0	0
T3	0	54	0	0
T4	5453	4	0	0
T5	12909	8	0	0
T7	1296	0	0	0
T8	0	16	0	0
T11	0	280	0	0
T12	0	20	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	20	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	182640780	0	0
T1	311359	311134	0	0
T4	5453	5406	0	0
T5	12909	2248	0	0
T6	1168	1157	0	0
T7	1296	1251	0	0
T18	2139	1942	0	0
T19	1872	1632	0	0
T20	2102	1984	0	0
T25	2033	1922	0	0
T26	1797	1766	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	184902954	207663	0	0
DstReqKnown_A	167040331	166503036	0	0
SrcAckBusyChk_A	184902954	28097	0	0
SrcBusyKnown_A	184902954	182640780	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	207663	0	0
T1	311359	2868	0	0
T2	440703	5449	0	0
T3	0	785	0	0
T4	5453	20	0	0
T5	12909	62	0	0
T7	1296	0	0	0
T8	0	231	0	0
T11	0	1452	0	0
T12	0	65	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	225	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	62	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167040331	166503036	0	0
T1	213170	213076	0	0
T4	5434	5407	0	0
T5	4159	1124	0	0
T6	4660	4629	0	0
T7	1232	1201	0	0
T18	494	466	0	0
T19	419	391	0	0
T20	1101	1067	0	0
T25	962	941	0	0
T26	1946	1932	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	28097	0	0
T1	311359	462	0	0
T2	440703	368	0	0
T3	0	54	0	0
T4	5453	4	0	0
T5	12909	8	0	0
T7	1296	0	0	0
T8	0	16	0	0
T11	0	280	0	0
T12	0	20	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	20	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	182640780	0	0
T1	311359	311134	0	0
T4	5453	5406	0	0
T5	12909	2248	0	0
T6	1168	1157	0	0
T7	1296	1251	0	0
T18	2139	1942	0	0
T19	1872	1632	0	0
T20	2102	1984	0	0
T25	2033	1922	0	0
T26	1797	1766	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	184902954	92625	0	0
DstReqKnown_A	709822792	705274919	0	0
SrcAckBusyChk_A	184902954	28097	0	0
SrcBusyKnown_A	184902954	182640780	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	92625	0	0
T1	311359	1394	0	0
T2	440703	2246	0	0
T3	0	273	0	0
T4	5453	10	0	0
T5	12909	28	0	0
T7	1296	0	0	0
T8	0	78	0	0
T11	0	709	0	0
T12	0	50	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	79	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	62	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709822792	705274919	0	0
T1	909171	908509	0	0
T4	22726	22528	0	0
T5	26894	4682	0	0
T6	19486	19289	0	0
T7	5188	5004	0	0
T18	2139	1942	0	0
T19	1872	1632	0	0
T20	4289	4049	0	0
T25	4148	3922	0	0
T26	7192	7066	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	28097	0	0
T1	311359	462	0	0
T2	440703	368	0	0
T3	0	54	0	0
T4	5453	4	0	0
T5	12909	8	0	0
T7	1296	0	0	0
T8	0	16	0	0
T11	0	280	0	0
T12	0	20	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	20	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	26	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	182640780	0	0
T1	311359	311134	0	0
T4	5453	5406	0	0
T5	12909	2248	0	0
T6	1168	1157	0	0
T7	1296	1251	0	0
T18	2139	1942	0	0
T19	1872	1632	0	0
T20	2102	1984	0	0
T25	2033	1922	0	0
T26	1797	1766	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	184902954	130749	0	0
DstReqKnown_A	341024541	338830416	0	0
SrcAckBusyChk_A	184902954	27648	0	0
SrcBusyKnown_A	184902954	182640780	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	130749	0	0
T1	311359	1882	0	0
T2	440703	3105	0	0
T3	0	443	0	0
T4	5453	14	0	0
T5	12909	28	0	0
T7	1296	0	0	0
T8	0	74	0	0
T11	0	1006	0	0
T12	0	50	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	132	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	42	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341024541	338830416	0	0
T1	436121	435803	0	0
T4	10908	10814	0	0
T5	12909	2248	0	0
T6	9353	9259	0	0
T7	2490	2402	0	0
T18	1026	932	0	0
T19	899	784	0	0
T20	2059	1943	0	0
T25	1991	1883	0	0
T26	3452	3392	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	27648	0	0
T1	311359	462	0	0
T2	440703	368	0	0
T3	0	54	0	0
T4	5453	4	0	0
T5	12909	4	0	0
T7	1296	0	0	0
T8	0	8	0	0
T11	0	280	0	0
T12	0	20	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	20	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	13	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	182640780	0	0
T1	311359	311134	0	0
T4	5453	5406	0	0
T5	12909	2248	0	0
T6	1168	1157	0	0
T7	1296	1251	0	0
T18	2139	1942	0	0
T19	1872	1632	0	0
T20	2102	1984	0	0
T25	2033	1922	0	0
T26	1797	1766	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	184902954	115466	0	0
DstReqKnown_A	669632172	665310889	0	0
SrcAckBusyChk_A	184902954	33729	0	0
SrcBusyKnown_A	184902954	182640780	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	115466	0	0
T1	311359	1444	0	0
T2	440703	1967	0	0
T3	0	281	0	0
T4	5453	10	0	0
T5	12909	56	0	0
T7	1296	0	0	0
T8	0	164	0	0
T11	0	749	0	0
T12	0	49	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	85	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	124	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669632172	665310889	0	0
T1	852041	851405	0	0
T4	21816	21627	0	0
T5	25818	4494	0	0
T6	18707	18517	0	0
T7	4980	4804	0	0
T18	2054	1864	0	0
T19	1798	1567	0	0
T20	4118	3887	0	0
T25	3982	3765	0	0
T26	6904	6783	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	33729	0	0
T1	311359	466	0	0
T2	440703	378	0	0
T3	0	54	0	0
T4	5453	4	0	0
T5	12909	16	0	0
T7	1296	0	0	0
T8	0	32	0	0
T11	0	287	0	0
T12	0	20	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	20	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	52	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	182640780	0	0
T1	311359	311134	0	0
T4	5453	5406	0	0
T5	12909	2248	0	0
T6	1168	1157	0	0
T7	1296	1251	0	0
T18	2139	1942	0	0
T19	1872	1632	0	0
T20	2102	1984	0	0
T25	2033	1922	0	0
T26	1797	1766	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	184902954	162251	0	0
DstReqKnown_A	334082028	333007217	0	0
SrcAckBusyChk_A	184902954	33563	0	0
SrcBusyKnown_A	184902954	182640780	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	162251	0	0
T1	311359	1895	0	0
T2	440703	3183	0	0
T3	0	456	0	0
T4	5453	14	0	0
T5	12909	80	0	0
T7	1296	0	0	0
T8	0	260	0	0
T11	0	1038	0	0
T12	0	49	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	129	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	124	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334082028	333007217	0	0
T1	426342	426155	0	0
T4	10868	10813	0	0
T5	8317	2248	0	0
T6	9320	9258	0	0
T7	2464	2402	0	0
T18	987	932	0	0
T19	839	784	0	0
T20	2203	2134	0	0
T25	1924	1883	0	0
T26	3893	3865	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	33563	0	0
T1	311359	466	0	0
T2	440703	378	0	0
T3	0	54	0	0
T4	5453	4	0	0
T5	12909	16	0	0
T7	1296	0	0	0
T8	0	32	0	0
T11	0	287	0	0
T12	0	20	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	20	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	52	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	182640780	0	0
T1	311359	311134	0	0
T4	5453	5406	0	0
T5	12909	2248	0	0
T6	1168	1157	0	0
T7	1296	1251	0	0
T18	2139	1942	0	0
T19	1872	1632	0	0
T20	2102	1984	0	0
T25	2033	1922	0	0
T26	1797	1766	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	184902954	258063	0	0
DstReqKnown_A	167040331	166503036	0	0
SrcAckBusyChk_A	184902954	33744	0	0
SrcBusyKnown_A	184902954	182640780	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	258063	0	0
T1	311359	2943	0	0
T2	440703	5576	0	0
T3	0	798	0	0
T4	5453	20	0	0
T5	12909	127	0	0
T7	1296	0	0	0
T8	0	458	0	0
T11	0	1479	0	0
T12	0	64	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	235	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	124	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167040331	166503036	0	0
T1	213170	213076	0	0
T4	5434	5407	0	0
T5	4159	1124	0	0
T6	4660	4629	0	0
T7	1232	1201	0	0
T18	494	466	0	0
T19	419	391	0	0
T20	1101	1067	0	0
T25	962	941	0	0
T26	1946	1932	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	33744	0	0
T1	311359	466	0	0
T2	440703	378	0	0
T3	0	54	0	0
T4	5453	4	0	0
T5	12909	16	0	0
T7	1296	0	0	0
T8	0	32	0	0
T11	0	287	0	0
T12	0	20	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	20	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	52	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	182640780	0	0
T1	311359	311134	0	0
T4	5453	5406	0	0
T5	12909	2248	0	0
T6	1168	1157	0	0
T7	1296	1251	0	0
T18	2139	1942	0	0
T19	1872	1632	0	0
T20	2102	1984	0	0
T25	2033	1922	0	0
T26	1797	1766	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	184902954	113177	0	0
DstReqKnown_A	709822792	705274919	0	0
SrcAckBusyChk_A	184902954	33729	0	0
SrcBusyKnown_A	184902954	182640780	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	113177	0	0
T1	311359	1410	0	0
T2	440703	2300	0	0
T3	0	273	0	0
T4	5453	10	0	0
T5	12909	55	0	0
T7	1296	0	0	0
T8	0	159	0	0
T11	0	722	0	0
T12	0	49	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	82	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	124	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709822792	705274919	0	0
T1	909171	908509	0	0
T4	22726	22528	0	0
T5	26894	4682	0	0
T6	19486	19289	0	0
T7	5188	5004	0	0
T18	2139	1942	0	0
T19	1872	1632	0	0
T20	4289	4049	0	0
T25	4148	3922	0	0
T26	7192	7066	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	33729	0	0
T1	311359	466	0	0
T2	440703	378	0	0
T3	0	54	0	0
T4	5453	4	0	0
T5	12909	16	0	0
T7	1296	0	0	0
T8	0	32	0	0
T11	0	287	0	0
T12	0	20	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	20	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	52	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	182640780	0	0
T1	311359	311134	0	0
T4	5453	5406	0	0
T5	12909	2248	0	0
T6	1168	1157	0	0
T7	1296	1251	0	0
T18	2139	1942	0	0
T19	1872	1632	0	0
T20	2102	1984	0	0
T25	2033	1922	0	0
T26	1797	1766	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T4,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	184902954	161670	0	0
DstReqKnown_A	341024541	338830416	0	0
SrcAckBusyChk_A	184902954	33359	0	0
SrcBusyKnown_A	184902954	182640780	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	161670	0	0
T1	311359	1889	0	0
T2	440703	3180	0	0
T3	0	451	0	0
T4	5453	14	0	0
T5	12909	95	0	0
T7	1296	0	0	0
T8	0	218	0	0
T11	0	1029	0	0
T12	0	49	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	132	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	124	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341024541	338830416	0	0
T1	436121	435803	0	0
T4	10908	10814	0	0
T5	12909	2248	0	0
T6	9353	9259	0	0
T7	2490	2402	0	0
T18	1026	932	0	0
T19	899	784	0	0
T20	2059	1943	0	0
T25	1991	1883	0	0
T26	3452	3392	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	33359	0	0
T1	311359	466	0	0
T2	440703	378	0	0
T3	0	54	0	0
T4	5453	4	0	0
T5	12909	14	0	0
T7	1296	0	0	0
T8	0	24	0	0
T11	0	287	0	0
T12	0	20	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T24	0	20	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T29	0	45	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	182640780	0	0
T1	311359	311134	0	0
T4	5453	5406	0	0
T5	12909	2248	0	0
T6	1168	1157	0	0
T7	1296	1251	0	0
T18	2139	1942	0	0
T19	1872	1632	0	0
T20	2102	1984	0	0
T25	2033	1922	0	0
T26	1797	1766	0	0