Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	575615	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3245762

1

T5

4

T6

4

T1

158

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	943277	1			T5	3		T6	5		T1	43
values[0x0]	1323741	1			T5	4		T6	5		T1	133
values[0x1]	1554359	1			T5	3		T6	6		T1	142

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	320242	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3501135

1

T5

5

T6

4

T1

201

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14885	1			T2	1		T19	1		T3	234
valid_sources[0x01]	14679	1			T3	236		T9	16		T24	3
valid_sources[0x02]	14358	1			T1	5		T2	2		T4	1
valid_sources[0x03]	15152	1			T19	2		T4	1		T104	5
valid_sources[0x04]	15199	1			T2	5		T3	226		T74	1
valid_sources[0x05]	15877	1			T2	1		T4	1		T40	1
valid_sources[0x06]	14871	1			T19	2		T4	1		T3	222
valid_sources[0x07]	14801	1			T1	4		T4	3		T3	159
valid_sources[0x08]	13975	1			T4	2		T3	217		T75	1
valid_sources[0x09]	14569	1			T19	1		T4	2		T104	15
valid_sources[0x0a]	15502	1			T2	1		T4	4		T3	260
valid_sources[0x0b]	14409	1			T22	1		T4	1		T41	81
valid_sources[0x0c]	15228	1			T2	1		T4	2		T40	1
valid_sources[0x0d]	15488	1			T3	202		T74	1		T9	1
valid_sources[0x0e]	15605	1			T2	1		T4	5		T3	164
valid_sources[0x0f]	16448	1			T6	2		T4	5		T104	2
valid_sources[0x10]	15075	1			T18	2		T4	2		T37	81
valid_sources[0x11]	15552	1			T2	3		T3	200		T9	116
valid_sources[0x12]	15033	1			T18	1		T2	5		T4	2
valid_sources[0x13]	14857	1			T2	1		T4	3		T3	220
valid_sources[0x14]	14468	1			T1	9		T2	1		T4	1
valid_sources[0x15]	15144	1			T22	2		T4	3		T3	216
valid_sources[0x16]	14813	1			T2	1		T23	7		T4	2
valid_sources[0x17]	14611	1			T4	3		T3	164		T75	1
valid_sources[0x18]	14894	1			T1	3		T2	4		T4	1
valid_sources[0x19]	13531	1			T6	3		T4	2		T3	252
valid_sources[0x1a]	14716	1			T2	5		T19	1		T3	214
valid_sources[0x1b]	15412	1			T1	11		T2	9		T3	180
valid_sources[0x1c]	14479	1			T81	11		T3	188		T80	1
valid_sources[0x1d]	14699	1			T4	3		T3	231		T77	1
valid_sources[0x1e]	15912	1			T1	3		T4	3		T3	169
valid_sources[0x1f]	14588	1			T1	15		T2	3		T4	1
valid_sources[0x20]	15238	1			T1	9		T18	1		T2	1
valid_sources[0x21]	16114	1			T4	1		T3	194		T9	213
valid_sources[0x22]	16050	1			T2	4		T4	1		T3	164
valid_sources[0x23]	14426	1			T2	3		T4	2		T3	143
valid_sources[0x24]	14353	1			T19	1		T4	2		T104	1
valid_sources[0x25]	15446	1			T2	1		T19	2		T4	2
valid_sources[0x26]	16381	1			T1	9		T19	6		T4	1
valid_sources[0x27]	13745	1			T3	203		T74	1		T9	9
valid_sources[0x28]	14839	1			T18	1		T2	1		T19	3
valid_sources[0x29]	23508	1			T1	5		T4	3		T113	24
valid_sources[0x2a]	14677	1			T3	177		T9	203		T27	1
valid_sources[0x2b]	13112	1			T6	2		T1	11		T2	2
valid_sources[0x2c]	14669	1			T4	2		T3	192		T75	1
valid_sources[0x2d]	13328	1			T3	197		T74	1		T9	159
valid_sources[0x2e]	15071	1			T2	1		T4	1		T3	182
valid_sources[0x2f]	14165	1			T1	7		T18	2		T2	2
valid_sources[0x30]	14540	1			T2	6		T4	4		T3	215
valid_sources[0x31]	14146	1			T2	1		T4	1		T3	242
valid_sources[0x32]	15111	1			T17	81		T23	1		T4	1
valid_sources[0x33]	15065	1			T20	2		T4	2		T3	276
valid_sources[0x34]	14275	1			T1	1		T23	1		T4	1
valid_sources[0x35]	16989	1			T2	1		T3	192		T9	2
valid_sources[0x36]	15593	1			T19	1		T22	1		T4	2
valid_sources[0x37]	14687	1			T23	3		T4	1		T3	197
valid_sources[0x38]	14495	1			T22	1		T4	5		T3	224
valid_sources[0x39]	14389	1			T3	208		T24	2		T151	1
valid_sources[0x3a]	15414	1			T4	1		T3	271		T9	3
valid_sources[0x3b]	13860	1			T2	3		T4	2		T3	168
valid_sources[0x3c]	15989	1			T3	216		T9	2		T80	2
valid_sources[0x3d]	15872	1			T2	1		T20	2		T3	197
valid_sources[0x3e]	15952	1			T1	1		T23	3		T3	241
valid_sources[0x3f]	14239	1			T1	5		T2	1		T22	1
valid_sources[0x40]	14086	1			T4	2		T3	228		T77	1
valid_sources[0x41]	13449	1			T22	2		T4	3		T3	201
valid_sources[0x42]	14464	1			T18	2		T2	1		T3	201
valid_sources[0x43]	17189	1			T1	7		T2	4		T4	2
valid_sources[0x44]	13871	1			T2	2		T4	2		T3	213
valid_sources[0x45]	14432	1			T4	1		T104	9		T3	214
valid_sources[0x46]	13953	1			T23	3		T4	2		T3	203
valid_sources[0x47]	15220	1			T2	2		T4	5		T3	206
valid_sources[0x48]	14764	1			T22	1		T4	1		T104	1
valid_sources[0x49]	13606	1			T2	7		T4	3		T40	1
valid_sources[0x4a]	14241	1			T2	1		T4	1		T3	195
valid_sources[0x4b]	14153	1			T1	6		T2	2		T4	1
valid_sources[0x4c]	14359	1			T4	2		T3	213		T74	1
valid_sources[0x4d]	14389	1			T4	1		T3	189		T77	2
valid_sources[0x4e]	15287	1			T4	2		T40	2		T3	217
valid_sources[0x4f]	15061	1			T5	1		T4	1		T3	204
valid_sources[0x50]	14802	1			T1	9		T2	5		T4	2
valid_sources[0x51]	15026	1			T5	4		T4	2		T3	178
valid_sources[0x52]	14296	1			T1	8		T3	197		T74	1
valid_sources[0x53]	14010	1			T4	1		T3	194		T74	1
valid_sources[0x54]	14733	1			T4	2		T3	183		T74	3
valid_sources[0x55]	16558	1			T18	3		T4	3		T3	275
valid_sources[0x56]	15233	1			T18	1		T4	1		T3	167
valid_sources[0x57]	15294	1			T18	3		T2	2		T23	1
valid_sources[0x58]	14244	1			T2	1		T4	1		T3	241
valid_sources[0x59]	14606	1			T5	1		T4	1		T3	170
valid_sources[0x5a]	15490	1			T1	7		T22	1		T3	168
valid_sources[0x5b]	14332	1			T4	2		T3	244		T74	1
valid_sources[0x5c]	14465	1			T1	2		T18	6		T2	1
valid_sources[0x5d]	14709	1			T4	2		T3	264		T79	3
valid_sources[0x5e]	14709	1			T4	2		T3	226		T74	1
valid_sources[0x5f]	13725	1			T22	1		T3	185		T75	1
valid_sources[0x60]	14215	1			T2	1		T4	4		T3	227
valid_sources[0x61]	15698	1			T1	4		T4	1		T104	2
valid_sources[0x62]	14755	1			T3	179		T115	3		T24	4
valid_sources[0x63]	14999	1			T1	3		T18	1		T4	2
valid_sources[0x64]	14807	1			T2	4		T4	1		T3	232
valid_sources[0x65]	14923	1			T22	1		T4	3		T3	226
valid_sources[0x66]	15927	1			T23	2		T3	189		T114	2
valid_sources[0x67]	15333	1			T2	1		T4	2		T3	148
valid_sources[0x68]	14112	1			T4	2		T3	109		T9	1
valid_sources[0x69]	13823	1			T4	1		T3	215		T75	3
valid_sources[0x6a]	14623	1			T2	1		T4	3		T3	242
valid_sources[0x6b]	16201	1			T4	3		T3	248		T9	210
valid_sources[0x6c]	14775	1			T3	204		T9	180		T77	1
valid_sources[0x6d]	13777	1			T4	5		T3	200		T77	3
valid_sources[0x6e]	14327	1			T4	4		T104	2		T3	219
valid_sources[0x6f]	14446	1			T21	29		T22	2		T4	1
valid_sources[0x70]	15191	1			T3	258		T74	1		T114	1
valid_sources[0x71]	14079	1			T2	2		T20	2		T4	2
valid_sources[0x72]	15232	1			T3	188		T9	1		T114	1
valid_sources[0x73]	15721	1			T4	2		T3	200		T9	1
valid_sources[0x74]	15981	1			T1	4		T2	6		T4	2
valid_sources[0x75]	14992	1			T4	2		T3	172		T77	2
valid_sources[0x76]	13875	1			T19	2		T4	2		T3	167
valid_sources[0x77]	15105	1			T2	2		T4	2		T104	1
valid_sources[0x78]	15205	1			T6	1		T18	3		T2	1
valid_sources[0x79]	13509	1			T2	3		T3	197		T9	101
valid_sources[0x7a]	14024	1			T2	1		T4	2		T3	220
valid_sources[0x7b]	14025	1			T1	4		T22	1		T3	216
valid_sources[0x7c]	15929	1			T4	1		T3	197		T26	1
valid_sources[0x7d]	13745	1			T1	1		T3	221		T9	3
valid_sources[0x7e]	14181	1			T2	1		T3	206		T26	1
valid_sources[0x7f]	14154	1			T2	2		T4	3		T3	128
valid_sources[0x80]	15666	1			T2	1		T19	1		T23	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

820586

1

T5

2

T6

3

T1

18

values[0x0]

all_enables

biggest_size

1234873

1

T5

2

T6

1

T1

91

values[0x1]

all_enables

biggest_size

1190303

1

T1

49

T17

3

T2

40