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tb.dut.u_io_step_down_req_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_io_step_down_req_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_div2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
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100.00 |
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tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_step_down_acks_sync.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_io_byp_req.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_send.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_all_byp_req.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clkmgr_byp.u_hi_speed_sel.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
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|
100.00 |
|
tb.dut.u_main_status.u_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
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|
100.00 |
|
tb.dut.u_io_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_status.u_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_status.u_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_meas.u_ref_meas_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_meas.u_ref_meas_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_meas.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_meas.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_meas.u_ref_meas_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_meas.u_ref_meas_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_meas.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_meas.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div2_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_meas.u_ref_meas_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_meas.u_ref_meas_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_meas.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_meas.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_io_div4_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_meas.u_ref_meas_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
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|
100.00 |
|
tb.dut.u_main_meas.u_meas.u_ref_meas_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
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|
100.00 |
|
tb.dut.u_main_meas.u_meas.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_meas.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
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|
100.00 |
|
tb.dut.u_main_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
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|
100.00 |
|
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_main_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_meas.u_ref_meas_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_meas.u_ref_meas_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_meas.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_meas.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_usb_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_prim_mubi4_sender_clk_main_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_prim_mubi4_sender_clk_usb_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_prim_mubi4_sender_clk_io_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_prim_mubi4_sender_clk_main_secure.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_io_div4_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_io_div4_peri_sw_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_io_div2_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_io_div2_peri_sw_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_io_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_io_peri_sw_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_prim_mubi4_sender_clk_io_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_usb_peri_sw_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_usb_peri_sw_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_prim_mubi4_sender_clk_usb_peri.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_aes_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_aes_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_aes_trans.u_err_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_aes_trans.u_err_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_aes_trans.u_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_aes_trans.u_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_hmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_hmac_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_hmac_trans.u_err_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_hmac_trans.u_err_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_hmac_trans.u_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_hmac_trans.u_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_kmac_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_kmac_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_kmac_trans.u_err_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_kmac_trans.u_err_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_kmac_trans.u_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_kmac_trans.u_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_otbn_trans.u_hint_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_otbn_trans.u_hint_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_otbn_trans.u_err_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_otbn_trans.u_err_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_otbn_trans.u_en_sync.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_clk_main_otbn_trans.u_en_sync.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|