Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	698729805	70675	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698729805	70675	0	0
T1	199960	203	0	0
T2	309030	214	0	0
T3	0	220	0	0
T9	0	1194	0	0
T10	0	468	0	0
T11	0	210	0	0
T12	0	546	0	0
T13	0	912	0	0
T14	0	198	0	0
T15	0	259	0	0
T16	8005	0	0	0
T17	10375	0	0	0
T18	8420	0	0	0
T19	10785	0	0	0
T20	5045	0	0	0
T21	6575	0	0	0
T22	9740	0	0	0
T23	5755	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	139745961	10354	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139745961	10354	0	0
T1	39992	32	0	0
T2	61806	31	0	0
T3	0	42	0	0
T9	0	190	0	0
T10	0	91	0	0
T11	0	34	0	0
T12	0	78	0	0
T13	0	118	0	0
T14	0	32	0	0
T15	0	43	0	0
T16	1601	0	0	0
T17	2075	0	0	0
T18	1684	0	0	0
T19	2157	0	0	0
T20	1009	0	0	0
T21	1315	0	0	0
T22	1948	0	0	0
T23	1151	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	139745961	14160	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139745961	14160	0	0
T1	39992	41	0	0
T2	61806	42	0	0
T3	0	42	0	0
T9	0	242	0	0
T10	0	91	0	0
T11	0	42	0	0
T12	0	106	0	0
T13	0	185	0	0
T14	0	41	0	0
T15	0	52	0	0
T16	1601	0	0	0
T17	2075	0	0	0
T18	1684	0	0	0
T19	2157	0	0	0
T20	1009	0	0	0
T21	1315	0	0	0
T22	1948	0	0	0
T23	1151	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	139745961	21623	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139745961	21623	0	0
T1	39992	57	0	0
T2	61806	62	0	0
T3	0	52	0	0
T9	0	332	0	0
T10	0	104	0	0
T11	0	58	0	0
T12	0	163	0	0
T13	0	308	0	0
T14	0	53	0	0
T15	0	68	0	0
T16	1601	0	0	0
T17	2075	0	0	0
T18	1684	0	0	0
T19	2157	0	0	0
T20	1009	0	0	0
T21	1315	0	0	0
T22	1948	0	0	0
T23	1151	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	139745961	10335	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139745961	10335	0	0
T1	39992	32	0	0
T2	61806	31	0	0
T3	0	42	0	0
T9	0	188	0	0
T10	0	91	0	0
T11	0	34	0	0
T12	0	77	0	0
T13	0	117	0	0
T14	0	32	0	0
T15	0	43	0	0
T16	1601	0	0	0
T17	2075	0	0	0
T18	1684	0	0	0
T19	2157	0	0	0
T20	1009	0	0	0
T21	1315	0	0	0
T22	1948	0	0	0
T23	1151	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	139745961	14203	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139745961	14203	0	0
T1	39992	41	0	0
T2	61806	48	0	0
T3	0	42	0	0
T9	0	242	0	0
T10	0	91	0	0
T11	0	42	0	0
T12	0	122	0	0
T13	0	184	0	0
T14	0	40	0	0
T15	0	53	0	0
T16	1601	0	0	0
T17	2075	0	0	0
T18	1684	0	0	0
T19	2157	0	0	0
T20	1009	0	0	0
T21	1315	0	0	0
T22	1948	0	0	0
T23	1151	0	0	0