Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Unreachable
1	0	Covered	T3,T9,T27

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	139745961	137342548	0	0
AllClkBypReqTrue_A	139745961	112346	0	0
IoClkBypReqFalse_A	139745961	137269488	0	2415
IoClkBypReqTrue_A	139745961	180688	0	0
LcClkBypAckFalse_A	139745961	137349706	0	0
LcClkBypAckTrue_A	139745961	105188	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139745961	137342548	0	0
T1	39992	39956	0	0
T2	61806	61710	0	0
T5	1308	1171	0	0
T6	1365	1225	0	0
T16	1601	1489	0	0
T17	2075	1962	0	0
T18	1684	1665	0	0
T19	2157	1933	0	0
T20	1009	944	0	0
T21	1315	1197	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139745961	112346	0	0
T1	39992	0	0	0
T2	61806	0	0	0
T3	0	178	0	0
T6	1365	100	0	0
T9	0	1326	0	0
T16	1601	0	0	0
T17	2075	0	0	0
T18	1684	0	0	0
T19	2157	174	0	0
T20	1009	29	0	0
T21	1315	0	0	0
T22	1948	0	0	0
T40	0	29	0	0
T73	0	45	0	0
T76	0	127	0	0
T104	0	200	0	0
T113	0	168	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139745961	137269488	0	2415
T1	39992	39954	0	3
T2	61806	61708	0	3
T5	1308	1113	0	3
T6	1365	1243	0	3
T16	1601	1487	0	3
T17	2075	1960	0	3
T18	1684	1663	0	3
T19	2157	2105	0	3
T20	1009	971	0	3
T21	1315	1195	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139745961	180688	0	0
T1	39992	0	0	0
T2	61806	0	0	0
T3	0	296	0	0
T5	1308	56	0	0
T6	1365	80	0	0
T9	0	2374	0	0
T16	1601	0	0	0
T17	2075	0	0	0
T18	1684	0	0	0
T19	2157	0	0	0
T20	1009	0	0	0
T21	1315	0	0	0
T22	0	282	0	0
T40	0	88	0	0
T73	0	81	0	0
T76	0	214	0	0
T104	0	280	0	0
T113	0	286	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139745961	137349706	0	0
T1	39992	39956	0	0
T2	61806	61710	0	0
T5	1308	1154	0	0
T6	1365	1283	0	0
T16	1601	1489	0	0
T17	2075	1962	0	0
T18	1684	1665	0	0
T19	2157	2107	0	0
T20	1009	973	0	0
T21	1315	1197	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139745961	105188	0	0
T1	39992	0	0	0
T2	61806	0	0	0
T3	0	154	0	0
T5	1308	17	0	0
T6	1365	42	0	0
T9	0	1289	0	0
T16	1601	0	0	0
T17	2075	0	0	0
T18	1684	0	0	0
T19	2157	0	0	0
T20	1009	0	0	0
T21	1315	0	0	0
T22	0	164	0	0
T40	0	45	0	0
T73	0	35	0	0
T76	0	152	0	0
T104	0	151	0	0
T113	0	118	0	0