Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2051336768	15714	0	0
TransStop_A	2051336768	7811	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051336768	15714	0	0
T2	515040	0	0	0
T3	0	61	0	0
T4	815980	0	0	0
T9	0	284	0	0
T17	8304	4	0	0
T18	67408	11	0	0
T19	34528	0	0	0
T20	16156	0	0	0
T21	10736	0	0	0
T22	33884	0	0	0
T23	9592	0	0	0
T37	0	4	0	0
T40	9848	0	0	0
T41	0	4	0	0
T74	0	27	0	0
T75	0	9	0	0
T77	0	32	0	0
T114	0	38	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051336768	7811	0	0
T2	515040	0	0	0
T3	0	20	0	0
T4	815980	0	0	0
T9	0	136	0	0
T17	8304	4	0	0
T18	67408	2	0	0
T19	34528	0	0	0
T20	16156	0	0	0
T21	10736	0	0	0
T22	33884	0	0	0
T23	9592	0	0	0
T24	0	22	0	0
T37	0	4	0	0
T40	9848	0	0	0
T41	0	4	0	0
T74	0	14	0	0
T75	0	2	0	0
T77	0	15	0	0
T114	0	22	0	0
T115	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	512834192	3901	0	0
TransStop_A	512834192	1969	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512834192	3901	0	0
T2	128760	0	0	0
T3	0	16	0	0
T4	203995	0	0	0
T9	0	74	0	0
T17	2076	1	0	0
T18	16852	3	0	0
T19	8632	0	0	0
T20	4039	0	0	0
T21	2684	0	0	0
T22	8471	0	0	0
T23	2398	0	0	0
T37	0	1	0	0
T40	2462	0	0	0
T41	0	1	0	0
T74	0	7	0	0
T75	0	3	0	0
T77	0	7	0	0
T114	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512834192	1969	0	0
T2	128760	0	0	0
T3	0	6	0	0
T4	203995	0	0	0
T9	0	35	0	0
T17	2076	1	0	0
T18	16852	1	0	0
T19	8632	0	0	0
T20	4039	0	0	0
T21	2684	0	0	0
T22	8471	0	0	0
T23	2398	0	0	0
T37	0	1	0	0
T40	2462	0	0	0
T41	0	1	0	0
T74	0	5	0	0
T75	0	1	0	0
T77	0	3	0	0
T114	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	512834192	3958	0	0
TransStop_A	512834192	1949	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512834192	3958	0	0
T2	128760	0	0	0
T3	0	13	0	0
T4	203995	0	0	0
T9	0	72	0	0
T17	2076	1	0	0
T18	16852	2	0	0
T19	8632	0	0	0
T20	4039	0	0	0
T21	2684	0	0	0
T22	8471	0	0	0
T23	2398	0	0	0
T37	0	1	0	0
T40	2462	0	0	0
T41	0	1	0	0
T74	0	8	0	0
T75	0	4	0	0
T77	0	7	0	0
T114	0	15	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512834192	1949	0	0
T2	128760	0	0	0
T3	0	3	0	0
T4	203995	0	0	0
T9	0	32	0	0
T17	2076	1	0	0
T18	16852	1	0	0
T19	8632	0	0	0
T20	4039	0	0	0
T21	2684	0	0	0
T22	8471	0	0	0
T23	2398	0	0	0
T37	0	1	0	0
T40	2462	0	0	0
T41	0	1	0	0
T74	0	4	0	0
T75	0	1	0	0
T77	0	3	0	0
T114	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	512834192	3933	0	0
TransStop_A	512834192	1930	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512834192	3933	0	0
T2	128760	0	0	0
T3	0	16	0	0
T4	203995	0	0	0
T9	0	68	0	0
T17	2076	1	0	0
T18	16852	3	0	0
T19	8632	0	0	0
T20	4039	0	0	0
T21	2684	0	0	0
T22	8471	0	0	0
T23	2398	0	0	0
T37	0	1	0	0
T40	2462	0	0	0
T41	0	1	0	0
T74	0	6	0	0
T75	0	1	0	0
T77	0	6	0	0
T114	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512834192	1930	0	0
T2	128760	0	0	0
T3	0	6	0	0
T4	203995	0	0	0
T9	0	31	0	0
T17	2076	1	0	0
T18	16852	0	0	0
T19	8632	0	0	0
T20	4039	0	0	0
T21	2684	0	0	0
T22	8471	0	0	0
T23	2398	0	0	0
T24	0	11	0	0
T37	0	1	0	0
T40	2462	0	0	0
T41	0	1	0	0
T74	0	4	0	0
T77	0	3	0	0
T114	0	6	0	0
T115	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	512834192	3922	0	0
TransStop_A	512834192	1963	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512834192	3922	0	0
T2	128760	0	0	0
T3	0	16	0	0
T4	203995	0	0	0
T9	0	70	0	0
T17	2076	1	0	0
T18	16852	3	0	0
T19	8632	0	0	0
T20	4039	0	0	0
T21	2684	0	0	0
T22	8471	0	0	0
T23	2398	0	0	0
T37	0	1	0	0
T40	2462	0	0	0
T41	0	1	0	0
T74	0	6	0	0
T75	0	1	0	0
T77	0	12	0	0
T114	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512834192	1963	0	0
T2	128760	0	0	0
T3	0	5	0	0
T4	203995	0	0	0
T9	0	38	0	0
T17	2076	1	0	0
T18	16852	0	0	0
T19	8632	0	0	0
T20	4039	0	0	0
T21	2684	0	0	0
T22	8471	0	0	0
T23	2398	0	0	0
T24	0	11	0	0
T37	0	1	0	0
T40	2462	0	0	0
T41	0	1	0	0
T74	0	1	0	0
T77	0	6	0	0
T114	0	6	0	0
T115	0	1	0	0