Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	140670137	4752986	0	0
clk_enables_rd_A	140670137	18916	0	0
clk_hints_rd_A	140670137	16706	0	0
extclk_ctrl_rd_A	140670137	22828	0	0
extclk_ctrl_regwen_rd_A	140670137	16244	0	0
jitter_enable_rd_A	140670137	23290	0	0
jitter_regwen_rd_A	140670137	17377	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140670137	4752986	0	0
T3	142622	70290	0	0
T9	900479	5103	0	0
T13	0	63006	0	0
T15	0	64563	0	0
T67	0	59923	0	0
T68	0	61169	0	0
T69	0	58255	0	0
T70	0	148977	0	0
T71	0	188807	0	0
T72	0	42775	0	0
T73	748	0	0	0
T74	1825	0	0	0
T75	1411	0	0	0
T76	1813	0	0	0
T77	3259	0	0	0
T78	1763	0	0	0
T79	1138	0	0	0
T80	1400	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140670137	18916	0	0
T10	149679	12	0	0
T11	32521	0	0	0
T13	0	2575	0	0
T25	8482	0	0	0
T31	1497	0	0	0
T32	1359	0	0	0
T33	1380	0	0	0
T38	1257	0	0	0
T39	1510	0	0	0
T50	0	11	0	0
T68	0	1287	0	0
T136	0	1	0	0
T137	0	10	0	0
T138	0	4	0	0
T139	0	6	0	0
T140	0	1828	0	0
T141	0	3	0	0
T142	1599	0	0	0
T143	1186	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140670137	16706	0	0
T3	142622	0	0	0
T9	900479	0	0	0
T10	0	2	0	0
T13	0	2135	0	0
T41	1997	3	0	0
T50	0	13	0	0
T68	0	1077	0	0
T73	748	0	0	0
T74	1825	0	0	0
T75	1411	0	0	0
T76	1813	0	0	0
T77	3259	0	0	0
T104	1723	0	0	0
T113	2100	0	0	0
T136	0	1	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	10	0	0
T140	0	1536	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140670137	22828	0	0
T1	39992	0	0	0
T2	61806	0	0	0
T6	1365	21	0	0
T10	0	97	0	0
T16	1601	0	0	0
T17	2075	0	0	0
T18	1684	0	0	0
T19	2157	60	0	0
T20	1009	15	0	0
T21	1315	0	0	0
T22	1948	0	0	0
T27	0	160	0	0
T29	0	79	0	0
T76	0	28	0	0
T113	0	26	0	0
T143	0	6	0	0
T144	0	42	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140670137	16244	0	0
T10	149679	0	0	0
T13	0	1980	0	0
T24	114851	0	0	0
T27	36285	36	0	0
T28	18962	0	0	0
T29	12748	57	0	0
T68	0	889	0	0
T101	0	52	0	0
T115	1877	0	0	0
T140	0	1717	0	0
T144	1914	0	0	0
T145	0	43	0	0
T146	0	52	0	0
T147	0	63	0	0
T148	0	46	0	0
T149	974	0	0	0
T150	706	0	0	0
T151	2872	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140670137	23290	0	0
T3	142622	0	0	0
T9	900479	0	0	0
T10	0	144	0	0
T13	0	2714	0	0
T37	1888	55	0	0
T41	1997	71	0	0
T50	0	421	0	0
T68	0	1544	0	0
T73	748	0	0	0
T74	1825	0	0	0
T75	1411	0	0	0
T76	1813	0	0	0
T104	1723	0	0	0
T113	2100	0	0	0
T136	0	88	0	0
T137	0	134	0	0
T138	0	122	0	0
T139	0	227	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140670137	17377	0	0
T13	214134	2354	0	0
T14	62392	0	0	0
T56	0	102	0	0
T68	0	1307	0	0
T83	32201	0	0	0
T105	0	214	0	0
T140	0	1929	0	0
T152	0	3880	0	0
T153	0	1103	0	0
T154	0	1998	0	0
T155	0	2851	0	0
T156	0	12	0	0
T157	1816	0	0	0
T158	1844	0	0	0
T159	1880	0	0	0
T160	1851	0	0	0
T161	862	0	0	0
T162	1569	0	0	0
T163	1283	0	0	0