Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T3,T9
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	46758	0	0
CgEnOn_A	2147483647	37307	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46758	0	0
T1	345503	3	0	0
T2	1328656	3	0	0
T4	1547861	0	0	0
T5	2885	3	0	0
T6	6254	3	0	0
T16	15678	39	0	0
T17	21336	7	0	0
T18	173741	6	0	0
T19	90112	3	0	0
T20	41840	3	0	0
T21	27426	32	0	0
T22	69907	0	0	0
T23	19512	0	0	0
T37	0	1	0	0
T38	0	5	0	0
T39	0	20	0	0
T41	0	1	0	0
T71	0	5	0	0
T162	0	25	0	0
T164	0	25	0	0
T165	0	15	0	0
T166	0	20	0	0
T167	0	15	0	0
T168	0	20	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37307	0	0
T2	1328656	0	0	0
T3	0	158	0	0
T4	1897714	0	0	0
T9	0	360	0	0
T16	15678	36	0	0
T17	21336	4	0	0
T18	173741	3	0	0
T19	90112	0	0	0
T20	41840	0	0	0
T21	27426	29	0	0
T22	88680	0	0	0
T23	24661	45	0	0
T37	0	4	0	0
T38	0	5	0	0
T39	0	20	0	0
T41	0	4	0	0
T71	0	4	0	0
T81	0	11	0	0
T162	0	25	0	0
T164	0	25	0	0
T165	0	15	0	0
T166	0	20	0	0
T167	0	15	0	0
T168	0	20	0	0
T169	0	3	0	0
T170	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T3,T9
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	240119590	145	0	0
CgEnOn_A	240119590	145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240119590	145	0	0
T2	61770	0	0	0
T4	71963	0	0	0
T16	726	4	0	0
T17	977	0	0	0
T18	8049	0	0	0
T19	4404	0	0	0
T20	1980	0	0	0
T21	1221	0	0	0
T22	4385	0	0	0
T23	1131	0	0	0
T38	0	1	0	0
T39	0	4	0	0
T71	0	1	0	0
T162	0	5	0	0
T164	0	5	0	0
T165	0	3	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240119590	145	0	0
T2	61770	0	0	0
T4	71963	0	0	0
T16	726	4	0	0
T17	977	0	0	0
T18	8049	0	0	0
T19	4404	0	0	0
T20	1980	0	0	0
T21	1221	0	0	0
T22	4385	0	0	0
T23	1131	0	0	0
T38	0	1	0	0
T39	0	4	0	0
T71	0	1	0	0
T162	0	5	0	0
T164	0	5	0	0
T165	0	3	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T3,T9
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120059242	145	0	0
CgEnOn_A	120059242	145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120059242	145	0	0
T2	30885	0	0	0
T4	35981	0	0	0
T16	363	4	0	0
T17	488	0	0	0
T18	4024	0	0	0
T19	2201	0	0	0
T20	990	0	0	0
T21	610	0	0	0
T22	2190	0	0	0
T23	566	0	0	0
T38	0	1	0	0
T39	0	4	0	0
T71	0	1	0	0
T162	0	5	0	0
T164	0	5	0	0
T165	0	3	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120059242	145	0	0
T2	30885	0	0	0
T4	35981	0	0	0
T16	363	4	0	0
T17	488	0	0	0
T18	4024	0	0	0
T19	2201	0	0	0
T20	990	0	0	0
T21	610	0	0	0
T22	2190	0	0	0
T23	566	0	0	0
T38	0	1	0	0
T39	0	4	0	0
T71	0	1	0	0
T162	0	5	0	0
T164	0	5	0	0
T165	0	3	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T3,T9
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	481803884	145	0	0
CgEnOn_A	481803884	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481803884	145	0	0
T2	123605	0	0	0
T4	143991	0	0	0
T16	1490	4	0	0
T17	1992	0	0	0
T18	16176	0	0	0
T19	8286	0	0	0
T20	3877	0	0	0
T21	2576	0	0	0
T22	8132	0	0	0
T23	2301	0	0	0
T38	0	1	0	0
T39	0	4	0	0
T71	0	1	0	0
T162	0	5	0	0
T164	0	5	0	0
T165	0	3	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481803884	142	0	0
T2	123605	0	0	0
T4	143991	0	0	0
T16	1490	4	0	0
T17	1992	0	0	0
T18	16176	0	0	0
T19	8286	0	0	0
T20	3877	0	0	0
T21	2576	0	0	0
T22	8132	0	0	0
T23	2301	0	0	0
T38	0	1	0	0
T39	0	4	0	0
T162	0	5	0	0
T164	0	5	0	0
T165	0	3	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0
T169	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T3,T9
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	512833746	160	0	0
CgEnOn_A	512833746	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512833746	160	0	0
T2	128760	0	0	0
T4	203994	0	0	0
T13	0	1	0	0
T16	1510	4	0	0
T17	2075	0	0	0
T18	16851	0	0	0
T19	8631	0	0	0
T20	4038	0	0	0
T21	2684	0	0	0
T22	8470	0	0	0
T23	2397	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T162	0	4	0	0
T164	0	2	0	0
T165	0	4	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512833746	156	0	0
T2	128760	0	0	0
T4	203994	0	0	0
T16	1510	4	0	0
T17	2075	0	0	0
T18	16851	0	0	0
T19	8631	0	0	0
T20	4038	0	0	0
T21	2684	0	0	0
T22	8470	0	0	0
T23	2397	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T162	0	4	0	0
T164	0	2	0	0
T165	0	4	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0
T169	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T3,T9
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120059242	145	0	0
CgEnOn_A	120059242	145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120059242	145	0	0
T2	30885	0	0	0
T4	35981	0	0	0
T16	363	4	0	0
T17	488	0	0	0
T18	4024	0	0	0
T19	2201	0	0	0
T20	990	0	0	0
T21	610	0	0	0
T22	2190	0	0	0
T23	566	0	0	0
T38	0	1	0	0
T39	0	4	0	0
T71	0	1	0	0
T162	0	5	0	0
T164	0	5	0	0
T165	0	3	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120059242	145	0	0
T2	30885	0	0	0
T4	35981	0	0	0
T16	363	4	0	0
T17	488	0	0	0
T18	4024	0	0	0
T19	2201	0	0	0
T20	990	0	0	0
T21	610	0	0	0
T22	2190	0	0	0
T23	566	0	0	0
T38	0	1	0	0
T39	0	4	0	0
T71	0	1	0	0
T162	0	5	0	0
T164	0	5	0	0
T165	0	3	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T3,T9
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	512833746	160	0	0
CgEnOn_A	512833746	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512833746	160	0	0
T2	128760	0	0	0
T4	203994	0	0	0
T13	0	1	0	0
T16	1510	4	0	0
T17	2075	0	0	0
T18	16851	0	0	0
T19	8631	0	0	0
T20	4038	0	0	0
T21	2684	0	0	0
T22	8470	0	0	0
T23	2397	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T162	0	4	0	0
T164	0	2	0	0
T165	0	4	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512833746	156	0	0
T2	128760	0	0	0
T4	203994	0	0	0
T16	1510	4	0	0
T17	2075	0	0	0
T18	16851	0	0	0
T19	8631	0	0	0
T20	4038	0	0	0
T21	2684	0	0	0
T22	8470	0	0	0
T23	2397	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T162	0	4	0	0
T164	0	2	0	0
T165	0	4	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0
T169	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T3,T9
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120059242	145	0	0
CgEnOn_A	120059242	145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120059242	145	0	0
T2	30885	0	0	0
T4	35981	0	0	0
T16	363	4	0	0
T17	488	0	0	0
T18	4024	0	0	0
T19	2201	0	0	0
T20	990	0	0	0
T21	610	0	0	0
T22	2190	0	0	0
T23	566	0	0	0
T38	0	1	0	0
T39	0	4	0	0
T71	0	1	0	0
T162	0	5	0	0
T164	0	5	0	0
T165	0	3	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120059242	145	0	0
T2	30885	0	0	0
T4	35981	0	0	0
T16	363	4	0	0
T17	488	0	0	0
T18	4024	0	0	0
T19	2201	0	0	0
T20	990	0	0	0
T21	610	0	0	0
T22	2190	0	0	0
T23	566	0	0	0
T38	0	1	0	0
T39	0	4	0	0
T71	0	1	0	0
T162	0	5	0	0
T164	0	5	0	0
T165	0	3	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T38,T39
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	240119590	7341	0	0
CgEnOn_A	240119590	4987	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240119590	7341	0	0
T1	76765	1	0	0
T2	61770	1	0	0
T5	630	1	0	0
T6	1440	1	0	0
T16	726	5	0	0
T17	977	2	0	0
T18	8049	1	0	0
T19	4404	1	0	0
T20	1980	1	0	0
T21	1221	11	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240119590	4987	0	0
T2	61770	0	0	0
T3	0	49	0	0
T4	71963	0	0	0
T9	0	95	0	0
T16	726	4	0	0
T17	977	1	0	0
T18	8049	0	0	0
T19	4404	0	0	0
T20	1980	0	0	0
T21	1221	10	0	0
T22	4385	0	0	0
T23	1131	15	0	0
T37	0	1	0	0
T41	0	1	0	0
T81	0	3	0	0
T170	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T38,T39
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120059242	7293	0	0
CgEnOn_A	120059242	4939	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120059242	7293	0	0
T1	38382	1	0	0
T2	30885	1	0	0
T5	315	1	0	0
T6	720	1	0	0
T16	363	5	0	0
T17	488	2	0	0
T18	4024	1	0	0
T19	2201	1	0	0
T20	990	1	0	0
T21	610	11	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120059242	4939	0	0
T2	30885	0	0	0
T3	0	48	0	0
T4	35981	0	0	0
T9	0	94	0	0
T16	363	4	0	0
T17	488	1	0	0
T18	4024	0	0	0
T19	2201	0	0	0
T20	990	0	0	0
T21	610	10	0	0
T22	2190	0	0	0
T23	566	15	0	0
T37	0	1	0	0
T41	0	1	0	0
T81	0	4	0	0
T170	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T38,T39
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	481803884	7384	0	0
CgEnOn_A	481803884	5027	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481803884	7384	0	0
T1	153568	1	0	0
T2	123605	1	0	0
T5	1294	1	0	0
T6	2729	1	0	0
T16	1490	5	0	0
T17	1992	2	0	0
T18	16176	1	0	0
T19	8286	1	0	0
T20	3877	1	0	0
T21	2576	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481803884	5027	0	0
T2	123605	0	0	0
T3	0	45	0	0
T4	143991	0	0	0
T9	0	97	0	0
T16	1490	4	0	0
T17	1992	1	0	0
T18	16176	0	0	0
T19	8286	0	0	0
T20	3877	0	0	0
T21	2576	9	0	0
T22	8132	0	0	0
T23	2301	15	0	0
T37	0	1	0	0
T41	0	1	0	0
T81	0	4	0	0
T170	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T38,T39
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	246202209	7341	0	0
CgEnOn_A	246202209	4982	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246202209	7341	0	0
T1	76788	1	0	0
T2	61806	1	0	0
T5	646	1	0	0
T6	1365	1	0	0
T16	734	4	0	0
T17	996	2	0	0
T18	8089	1	0	0
T19	4142	1	0	0
T20	1938	1	0	0
T21	1288	13	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246202209	4982	0	0
T2	61806	0	0	0
T3	0	44	0	0
T4	97918	0	0	0
T9	0	90	0	0
T16	734	3	0	0
T17	996	1	0	0
T18	8089	0	0	0
T19	4142	0	0	0
T20	1938	0	0	0
T21	1288	12	0	0
T22	4066	0	0	0
T23	1151	16	0	0
T37	0	1	0	0
T41	0	1	0	0
T81	0	4	0	0
T170	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T3,T9
1	0	Covered	T17,T18,T37
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	512833746	4061	0	0
CgEnOn_A	512833746	4057	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512833746	4061	0	0
T2	128760	0	0	0
T3	0	16	0	0
T4	203994	0	0	0
T9	0	74	0	0
T16	1510	4	0	0
T17	2075	1	0	0
T18	16851	3	0	0
T19	8631	0	0	0
T20	4038	0	0	0
T21	2684	0	0	0
T22	8470	0	0	0
T23	2397	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T74	0	7	0	0
T75	0	3	0	0
T77	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512833746	4057	0	0
T2	128760	0	0	0
T3	0	16	0	0
T4	203994	0	0	0
T9	0	74	0	0
T16	1510	4	0	0
T17	2075	1	0	0
T18	16851	3	0	0
T19	8631	0	0	0
T20	4038	0	0	0
T21	2684	0	0	0
T22	8470	0	0	0
T23	2397	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T74	0	7	0	0
T75	0	3	0	0
T77	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T3,T9
1	0	Covered	T17,T18,T37
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	512833746	4118	0	0
CgEnOn_A	512833746	4114	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512833746	4118	0	0
T2	128760	0	0	0
T3	0	13	0	0
T4	203994	0	0	0
T9	0	72	0	0
T16	1510	4	0	0
T17	2075	1	0	0
T18	16851	2	0	0
T19	8631	0	0	0
T20	4038	0	0	0
T21	2684	0	0	0
T22	8470	0	0	0
T23	2397	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T74	0	8	0	0
T75	0	4	0	0
T77	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512833746	4114	0	0
T2	128760	0	0	0
T3	0	13	0	0
T4	203994	0	0	0
T9	0	72	0	0
T16	1510	4	0	0
T17	2075	1	0	0
T18	16851	2	0	0
T19	8631	0	0	0
T20	4038	0	0	0
T21	2684	0	0	0
T22	8470	0	0	0
T23	2397	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T74	0	8	0	0
T75	0	4	0	0
T77	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T3,T9
1	0	Covered	T17,T18,T37
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	512833746	4093	0	0
CgEnOn_A	512833746	4089	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512833746	4093	0	0
T2	128760	0	0	0
T3	0	16	0	0
T4	203994	0	0	0
T9	0	68	0	0
T16	1510	4	0	0
T17	2075	1	0	0
T18	16851	3	0	0
T19	8631	0	0	0
T20	4038	0	0	0
T21	2684	0	0	0
T22	8470	0	0	0
T23	2397	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T74	0	6	0	0
T75	0	1	0	0
T77	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512833746	4089	0	0
T2	128760	0	0	0
T3	0	16	0	0
T4	203994	0	0	0
T9	0	68	0	0
T16	1510	4	0	0
T17	2075	1	0	0
T18	16851	3	0	0
T19	8631	0	0	0
T20	4038	0	0	0
T21	2684	0	0	0
T22	8470	0	0	0
T23	2397	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T74	0	6	0	0
T75	0	1	0	0
T77	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T3,T9
1	0	Covered	T17,T18,T37
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	512833746	4082	0	0
CgEnOn_A	512833746	4078	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512833746	4082	0	0
T2	128760	0	0	0
T3	0	16	0	0
T4	203994	0	0	0
T9	0	70	0	0
T16	1510	4	0	0
T17	2075	1	0	0
T18	16851	3	0	0
T19	8631	0	0	0
T20	4038	0	0	0
T21	2684	0	0	0
T22	8470	0	0	0
T23	2397	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T74	0	6	0	0
T75	0	1	0	0
T77	0	12	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512833746	4078	0	0
T2	128760	0	0	0
T3	0	16	0	0
T4	203994	0	0	0
T9	0	70	0	0
T16	1510	4	0	0
T17	2075	1	0	0
T18	16851	3	0	0
T19	8631	0	0	0
T20	4038	0	0	0
T21	2684	0	0	0
T22	8470	0	0	0
T23	2397	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T74	0	6	0	0
T75	0	1	0	0
T77	0	12	0	0