Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T21
0	1	Covered	T21,T23,T81
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T21,T23
1	0	Covered	T16,T38,T39
1	1	Covered	T5,T6,T1

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1088186535	13071	0	0
GateOpen_A	1088186535	13071	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088186535	13071	0	0
T2	278066	0	0	0
T3	0	135	0	0
T4	349855	0	0	0
T9	0	226	0	0
T16	3314	15	0	0
T17	4456	4	0	0
T18	36340	0	0	0
T19	19035	0	0	0
T20	8787	0	0	0
T21	5697	22	0	0
T22	18775	0	0	0
T23	5151	36	0	0
T37	0	4	0	0
T41	0	4	0	0
T81	0	11	0	0
T170	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088186535	13071	0	0
T2	278066	0	0	0
T3	0	135	0	0
T4	349855	0	0	0
T9	0	226	0	0
T16	3314	15	0	0
T17	4456	4	0	0
T18	36340	0	0	0
T19	19035	0	0	0
T20	8787	0	0	0
T21	5697	22	0	0
T22	18775	0	0	0
T23	5151	36	0	0
T37	0	4	0	0
T41	0	4	0	0
T81	0	11	0	0
T170	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T21
0	1	Covered	T21,T23,T81
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T21,T23
1	0	Covered	T16,T38,T39
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	120059649	3245	0	0
GateOpen_A	120059649	3245	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120059649	3245	0	0
T2	30885	0	0	0
T3	0	37	0	0
T4	35982	0	0	0
T9	0	56	0	0
T16	363	4	0	0
T17	489	1	0	0
T18	4025	0	0	0
T19	2202	0	0	0
T20	991	0	0	0
T21	611	5	0	0
T22	2191	0	0	0
T23	566	10	0	0
T37	0	1	0	0
T41	0	1	0	0
T81	0	3	0	0
T170	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120059649	3245	0	0
T2	30885	0	0	0
T3	0	37	0	0
T4	35982	0	0	0
T9	0	56	0	0
T16	363	4	0	0
T17	489	1	0	0
T18	4025	0	0	0
T19	2202	0	0	0
T20	991	0	0	0
T21	611	5	0	0
T22	2191	0	0	0
T23	566	10	0	0
T37	0	1	0	0
T41	0	1	0	0
T81	0	3	0	0
T170	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T21
0	1	Covered	T21,T23,T81
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T21,T23
1	0	Covered	T16,T38,T39
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	240119973	3276	0	0
GateOpen_A	240119973	3276	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240119973	3276	0	0
T2	61770	0	0	0
T3	0	35	0	0
T4	71963	0	0	0
T9	0	56	0	0
T16	726	4	0	0
T17	977	1	0	0
T18	8049	0	0	0
T19	4404	0	0	0
T20	1981	0	0	0
T21	1221	5	0	0
T22	4385	0	0	0
T23	1132	8	0	0
T37	0	1	0	0
T41	0	1	0	0
T81	0	2	0	0
T170	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240119973	3276	0	0
T2	61770	0	0	0
T3	0	35	0	0
T4	71963	0	0	0
T9	0	56	0	0
T16	726	4	0	0
T17	977	1	0	0
T18	8049	0	0	0
T19	4404	0	0	0
T20	1981	0	0	0
T21	1221	5	0	0
T22	4385	0	0	0
T23	1132	8	0	0
T37	0	1	0	0
T41	0	1	0	0
T81	0	2	0	0
T170	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T21
0	1	Covered	T21,T23,T81
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T21,T23
1	0	Covered	T16,T38,T39
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	481804305	3288	0	0
GateOpen_A	481804305	3288	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481804305	3288	0	0
T2	123605	0	0	0
T3	0	31	0	0
T4	143991	0	0	0
T9	0	59	0	0
T16	1491	4	0	0
T17	1993	1	0	0
T18	16177	0	0	0
T19	8286	0	0	0
T20	3877	0	0	0
T21	2577	5	0	0
T22	8132	0	0	0
T23	2302	9	0	0
T37	0	1	0	0
T41	0	1	0	0
T81	0	3	0	0
T170	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481804305	3288	0	0
T2	123605	0	0	0
T3	0	31	0	0
T4	143991	0	0	0
T9	0	59	0	0
T16	1491	4	0	0
T17	1993	1	0	0
T18	16177	0	0	0
T19	8286	0	0	0
T20	3877	0	0	0
T21	2577	5	0	0
T22	8132	0	0	0
T23	2302	9	0	0
T37	0	1	0	0
T41	0	1	0	0
T81	0	3	0	0
T170	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T21
0	1	Covered	T21,T23,T81
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T21,T23
1	0	Covered	T16,T38,T39
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	246202608	3262	0	0
GateOpen_A	246202608	3262	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246202608	3262	0	0
T2	61806	0	0	0
T3	0	32	0	0
T4	97919	0	0	0
T9	0	55	0	0
T16	734	3	0	0
T17	997	1	0	0
T18	8089	0	0	0
T19	4143	0	0	0
T20	1938	0	0	0
T21	1288	7	0	0
T22	4067	0	0	0
T23	1151	9	0	0
T37	0	1	0	0
T41	0	1	0	0
T81	0	3	0	0
T170	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246202608	3262	0	0
T2	61806	0	0	0
T3	0	32	0	0
T4	97919	0	0	0
T9	0	55	0	0
T16	734	3	0	0
T17	997	1	0	0
T18	8089	0	0	0
T19	4143	0	0	0
T20	1938	0	0	0
T21	1288	7	0	0
T22	4067	0	0	0
T23	1151	9	0	0
T37	0	1	0	0
T41	0	1	0	0
T81	0	3	0	0
T170	0	2	0	0