Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	842427	0	0
SrcPulseCheck_M	2147483647	839074	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	842427
T1	1757308	3870
T2	0	1433
T3	0	5412
T4	323725	120
T5	610199	726
T6	413854	422
T11	0	8249
T12	0	1229
T23	0	212
T26	11209	0
T27	24587	0
T28	90487	0
T29	39931	0
T30	20813	0
T33	29204	0
T34	0	282
T35	0	20
T36	0	124
T60	22820	2
T61	34432	1
T65	10388	2
T67	21838	2
T117	4904	1
T118	11494	1
T119	20684	3
T120	5260	2
T121	9493	1
T122	2871	0
T123	8105	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	839074
T1	997230	3870
T2	0	1433
T3	0	4657
T4	78640	120
T5	245054	726
T6	249809	422
T11	0	7946
T12	0	1229
T23	0	212
T26	6509	0
T27	9033	0
T28	23444	0
T29	13112	0
T30	6741	0
T33	9379	0
T34	0	282
T35	0	20
T36	0	124
T60	9618	2
T61	15646	1
T65	18966	2
T67	42450	2
T117	38808	1
T118	21142	1
T119	9048	3
T120	9912	2
T121	19880	1
T122	5328	0
T123	7243	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	289417735	22867	0	0
SrcPulseCheck_M	153576157	22867	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	289417735	22867
T1	436109	246
T2	0	70
T3	0	250
T4	95082	24
T5	129428	30
T6	76611	18
T11	0	430
T23	0	8
T26	2267	0
T27	5726	0
T28	21276	0
T29	9876	0
T30	5147	0
T33	6696	0
T34	0	10
T35	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153576157	22867
T1	101395	246
T2	0	70
T3	0	250
T4	23770	24
T5	89586	30
T6	105410	18
T11	0	430
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	4

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	289417735	28665	0	0
SrcPulseCheck_M	153576157	28675	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	289417735	28665
T1	436109	251
T2	0	70
T3	0	257
T4	95082	48
T5	129428	30
T6	76611	18
T11	0	441
T23	0	8
T26	2267	0
T27	5726	0
T28	21276	0
T29	9876	0
T30	5147	0
T33	6696	0
T34	0	10
T35	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153576157	28675
T1	101395	251
T2	0	70
T3	0	257
T4	23770	48
T5	89586	30
T6	105410	18
T11	0	441
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	8

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	28659	0	0
SrcPulseCheck_M	289417735	28667	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	28659
T1	101395	251
T2	0	70
T3	0	257
T4	23770	48
T5	89586	30
T6	105410	18
T11	0	441
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	289417735	28667
T1	436109	251
T2	0	70
T3	0	257
T4	95082	48
T5	129428	30
T6	76611	18
T11	0	441
T23	0	8
T26	2267	0
T27	5726	0
T28	21276	0
T29	9876	0
T30	5147	0
T33	6696	0
T34	0	10
T35	0	8

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	144663091	22867	0	0
SrcPulseCheck_M	153576157	22867	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	144663091	22867
T1	217860	246
T2	0	70
T3	0	250
T4	30236	24
T5	64674	30
T6	38293	18
T11	0	430
T23	0	8
T26	1219	0
T27	3071	0
T28	12810	0
T29	4884	0
T30	2561	0
T33	3941	0
T34	0	10
T35	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153576157	22867
T1	101395	246
T2	0	70
T3	0	250
T4	23770	24
T5	89586	30
T6	105410	18
T11	0	430
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	4

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	144663091	28807	0	0
SrcPulseCheck_M	153576157	28828	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	144663091	28807
T1	217860	251
T2	0	70
T3	0	257
T4	30236	48
T5	64674	30
T6	38293	18
T11	0	441
T23	0	8
T26	1219	0
T27	3071	0
T28	12810	0
T29	4884	0
T30	2561	0
T33	3941	0
T34	0	10
T35	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153576157	28828
T1	101395	251
T2	0	70
T3	0	257
T4	23770	48
T5	89586	30
T6	105410	18
T11	0	441
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	8

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	28797	0	0
SrcPulseCheck_M	144663091	28810	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	28797
T1	101395	251
T2	0	70
T3	0	257
T4	23770	48
T5	89586	30
T6	105410	18
T11	0	441
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	144663091	28810
T1	217860	251
T2	0	70
T3	0	257
T4	30236	48
T5	64674	30
T6	38293	18
T11	0	441
T23	0	8
T26	1219	0
T27	3071	0
T28	12810	0
T29	4884	0
T30	2561	0
T33	3941	0
T34	0	10
T35	0	8

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	72330963	22867	0	0
SrcPulseCheck_M	153576157	22867	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	72330963	22867
T1	108929	246
T2	0	70
T3	0	250
T4	15118	24
T5	32337	30
T6	19147	18
T11	0	430
T23	0	8
T26	609	0
T27	1535	0
T28	6403	0
T29	2442	0
T30	1281	0
T33	1968	0
T34	0	10
T35	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153576157	22867
T1	101395	246
T2	0	70
T3	0	250
T4	23770	24
T5	89586	30
T6	105410	18
T11	0	430
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	4

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	72330963	28649	0	0
SrcPulseCheck_M	153576157	28680	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	72330963	28649
T1	108929	251
T2	0	70
T3	0	257
T4	15118	48
T5	32337	30
T6	19147	18
T11	0	441
T23	0	8
T26	609	0
T27	1535	0
T28	6403	0
T29	2442	0
T30	1281	0
T33	1968	0
T34	0	10
T35	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153576157	28680
T1	101395	251
T2	0	70
T3	0	257
T4	23770	48
T5	89586	30
T6	105410	18
T11	0	441
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	8

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	28649	0	0
SrcPulseCheck_M	72330963	28655	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	28649
T1	101395	251
T2	0	70
T3	0	257
T4	23770	48
T5	89586	30
T6	105410	18
T11	0	441
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	72330963	28655
T1	108929	251
T2	0	70
T3	0	257
T4	15118	48
T5	32337	30
T6	19147	18
T11	0	441
T23	0	8
T26	609	0
T27	1535	0
T28	6403	0
T29	2442	0
T30	1281	0
T33	1968	0
T34	0	10
T35	0	8

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	311155203	22867	0	0
SrcPulseCheck_M	153576157	22867	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	311155203	22867
T1	457295	246
T2	0	70
T3	0	250
T4	99047	24
T5	164826	30
T6	97807	18
T11	0	430
T23	0	8
T26	2361	0
T27	5966	0
T28	22163	0
T29	10287	0
T30	5362	0
T33	6974	0
T34	0	10
T35	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153576157	22867
T1	101395	246
T2	0	70
T3	0	250
T4	23770	24
T5	89586	30
T6	105410	18
T11	0	430
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	4

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	311155203	28771	0	0
SrcPulseCheck_M	153576157	28790	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	311155203	28771
T1	457295	251
T2	0	70
T3	0	257
T4	99047	48
T5	164826	30
T6	97807	18
T11	0	441
T23	0	8
T26	2361	0
T27	5966	0
T28	22163	0
T29	10287	0
T30	5362	0
T33	6974	0
T34	0	10
T35	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153576157	28790
T1	101395	251
T2	0	70
T3	0	257
T4	23770	48
T5	89586	30
T6	105410	18
T11	0	441
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	8

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	28757	0	0
SrcPulseCheck_M	311155203	28775	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	28757
T1	101395	251
T2	0	70
T3	0	257
T4	23770	48
T5	89586	30
T6	105410	18
T11	0	441
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	311155203	28775
T1	457295	251
T2	0	70
T3	0	257
T4	99047	48
T5	164826	30
T6	97807	18
T11	0	441
T23	0	8
T26	2361	0
T27	5966	0
T28	22163	0
T29	10287	0
T30	5362	0
T33	6974	0
T34	0	10
T35	0	8

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	149452656	22413	0	0
SrcPulseCheck_M	153576157	22867	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	149452656	22413
T1	220657	246
T2	0	70
T3	0	250
T4	47543	12
T5	84877	30
T6	46948	18
T11	0	430
T23	0	8
T26	1134	0
T27	2864	0
T28	10638	0
T29	4938	0
T30	2574	0
T33	3347	0
T34	0	10
T35	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153576157	22867
T1	101395	246
T2	0	70
T3	0	250
T4	23770	24
T5	89586	30
T6	105410	18
T11	0	430
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	4

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	149452656	28332	0	0
SrcPulseCheck_M	153576157	28572	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	149452656	28332
T1	220657	251
T2	0	70
T3	0	257
T4	47543	48
T5	84877	30
T6	46948	18
T11	0	441
T23	0	8
T26	1134	0
T27	2864	0
T28	10638	0
T29	4938	0
T30	2574	0
T33	3347	0
T34	0	10
T35	0	6

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	153576157	28572
T1	101395	251
T2	0	70
T3	0	257
T4	23770	48
T5	89586	30
T6	105410	18
T11	0	441
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	8

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T4,T6
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	28225	0	0
SrcPulseCheck_M	149452656	28398	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	28225
T1	101395	251
T2	0	70
T3	0	257
T4	23770	46
T5	89586	30
T6	105410	18
T11	0	441
T23	0	8
T26	2315	0
T27	2147	0
T28	2215	0
T29	2674	0
T30	1340	0
T33	1743	0
T34	0	10
T35	0	6

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	149452656	28398
T1	220657	251
T2	0	70
T3	0	257
T4	47543	48
T5	84877	30
T6	46948	18
T11	0	441
T23	0	8
T26	1134	0
T27	2864	0
T28	10638	0
T29	4938	0
T30	2574	0
T33	3347	0
T34	0	10
T35	0	6

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T62,T65,T63
1	0	Covered	T62,T65,T63
1	1	Covered	T124

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T62,T65,T63
1	0	Covered	T124
1	1	Covered	T62,T65,T63

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	19	0	0
SrcPulseCheck_M	289417735	19	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	19
T62	5169	1
T63	3809	2
T65	5194	1
T118	5747	1
T120	2630	1
T124	8977	2
T125	16674	1
T126	2204	1
T127	9837	2
T128	4194	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	289417735	19
T62	49621	1
T63	7313	2
T65	20775	1
T118	22067	1
T120	10519	1
T124	18335	2
T125	16674	1
T126	17631	1
T127	37774	2
T128	8217	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T62,T63
1	0	Covered	T60,T62,T63
1	1	Covered	T123,T129,T130

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T62,T63
1	0	Covered	T123,T129,T130
1	1	Covered	T60,T62,T63

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	30	0	0
SrcPulseCheck_M	289417735	30	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	30
T60	11410	1
T62	5169	2
T63	3809	2
T118	5747	1
T120	2630	1
T125	16674	1
T126	2204	1
T131	3291	1
T132	6035	1
T133	10689	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	289417735	30
T60	10952	1
T62	49621	2
T63	7313	2
T118	22067	1
T120	10519	1
T125	16674	1
T126	17631	1
T131	13164	1
T132	57946	1
T133	41046	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T61,T67
1	0	Covered	T60,T61,T67
1	1	Covered	T67,T65,T119

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T61,T67
1	0	Covered	T67,T65,T119
1	1	Covered	T60,T61,T67

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	36	0	0
SrcPulseCheck_M	144663091	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	36
T60	11410	2
T61	17216	1
T65	5194	2
T67	10919	2
T117	2452	1
T118	5747	1
T119	10342	3
T120	2630	2
T121	9493	1
T122	2871	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	144663091	36
T60	4809	2
T61	7823	1
T65	9483	2
T67	21225	2
T117	19404	1
T118	10571	1
T119	4524	3
T120	4956	2
T121	19880	1
T122	5328	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T61,T67
1	0	Covered	T60,T61,T67
1	1	Covered	T67,T134,T135

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T61,T67
1	0	Covered	T67,T134,T135
1	1	Covered	T60,T61,T67

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	35	0	0
SrcPulseCheck_M	144663091	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	35
T60	11410	2
T61	17216	1
T65	5194	2
T67	10919	2
T117	2452	2
T118	5747	1
T119	10342	2
T120	2630	2
T123	8105	3
T136	4643	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	144663091	35
T60	4809	2
T61	7823	1
T65	9483	2
T67	21225	2
T117	19404	2
T118	10571	1
T119	4524	2
T120	4956	2
T123	7243	3
T136	27166	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T61,T62
1	0	Covered	T60,T61,T62
1	1	Covered	T61,T63,T125

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T61,T62
1	0	Covered	T61,T63,T125
1	1	Covered	T60,T61,T62

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	28	0	0
SrcPulseCheck_M	72330963	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	28
T60	11410	2
T61	17216	2
T62	5169	2
T63	3809	2
T65	5194	1
T67	10919	3
T119	10342	1
T120	2630	1
T125	16674	2
T126	2204	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	72330963	28
T60	2406	2
T61	3912	2
T62	11974	2
T63	1634	2
T65	4741	1
T67	10613	3
T119	2261	1
T120	2476	1
T125	3787	2
T126	4211	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T61,T62
1	0	Covered	T60,T61,T62
1	1	Covered	T118

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T61,T62
1	0	Covered	T118
1	1	Covered	T60,T61,T62

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	25	0	0
SrcPulseCheck_M	72330963	25	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	25
T60	11410	3
T61	17216	1
T62	5169	2
T67	10919	3
T118	5747	2
T119	10342	2
T123	8105	2
T128	4194	1
T137	2810	1
T138	5311	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	72330963	25
T60	2406	3
T61	3912	1
T62	11974	2
T67	10613	3
T118	5285	2
T119	2261	2
T123	3620	2
T128	1899	1
T137	2584	1
T138	7158	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T64,T66
1	0	Covered	T60,T64,T66
1	1	Covered	T119,T139,T133

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T64,T66
1	0	Covered	T119,T139,T133
1	1	Covered	T60,T64,T66

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	37	0	0
SrcPulseCheck_M	311155203	37	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	37
T60	11410	2
T63	3809	1
T64	5200	1
T65	5194	4
T66	7114	2
T117	2452	1
T119	10342	4
T123	8105	1
T133	10689	2
T139	17380	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	311155203	37
T60	11410	2
T63	7618	1
T64	5252	1
T65	21642	4
T66	7114	2
T117	40880	1
T119	10774	4
T123	16886	1
T133	42759	2
T139	17380	4

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T62,T66
1	0	Covered	T60,T62,T66
1	1	Covered	T119,T139,T133

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T62,T66
1	0	Covered	T119,T139,T133
1	1	Covered	T60,T62,T66

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	28	0	0
SrcPulseCheck_M	311155203	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	28
T60	11410	1
T62	5169	1
T65	5194	3
T66	7114	1
T119	10342	4
T123	8105	1
T133	10689	3
T136	4643	1
T137	2810	1
T139	17380	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	311155203	28
T60	11410	1
T62	51691	1
T65	21642	3
T66	7114	1
T119	10774	4
T123	16886	1
T133	42759	3
T136	58042	1
T137	11711	1
T139	17380	3

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T61,T62
1	0	Covered	T60,T61,T62
1	1	Covered	T63,T140,T130

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T61,T62
1	0	Covered	T63,T140,T130
1	1	Covered	T60,T61,T62

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	32	0	0
SrcPulseCheck_M	149452656	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	32
T60	11410	2
T61	17216	1
T62	5169	1
T63	3809	2
T64	5200	1
T65	5194	2
T120	2630	1
T132	6035	1
T133	10689	1
T139	17380	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	149452656	32
T60	5476	2
T61	8608	1
T62	24812	1
T63	3656	2
T64	2521	1
T65	10388	2
T120	5260	1
T132	28974	1
T133	20524	1
T139	8342	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T62,T64
1	0	Covered	T60,T62,T64
1	1	Covered	T63,T123,T136

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T60,T62,T64
1	0	Covered	T63,T123,T136
1	1	Covered	T60,T62,T64

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	153576157	34	0	0
SrcPulseCheck_M	149452656	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	153576157	34
T60	11410	2
T62	5169	3
T63	3809	2
T64	5200	1
T65	5194	2
T117	2452	1
T120	2630	1
T126	2204	2
T132	6035	1
T139	17380	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	149452656	34
T60	5476	2
T62	24812	3
T63	3656	2
T64	2521	1
T65	10388	2
T117	19622	1
T120	5260	1
T126	8816	2
T132	28974	1
T139	8342	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	286805371	81538	0	0
SrcPulseCheck_M	10075226	80438	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	286805371	81538
T1	436109	766
T2	0	304
T3	0	1195
T4	95082	0
T5	129428	144
T6	76611	83
T11	0	1609
T12	0	308
T23	0	41
T26	2267	0
T27	5726	0
T28	21276	0
T29	9876	0
T30	5147	0
T33	6696	0
T34	0	60
T36	0	31

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10075226	80438
T1	144130	766
T2	0	304
T3	0	926
T4	216	0
T5	287	144
T6	165	83
T11	0	1609
T12	0	308
T23	0	41
T26	165	0
T27	417	0
T28	1551	0
T29	720	0
T30	375	0
T33	488	0
T34	0	60
T36	0	31

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	143399245	81275	0	0
SrcPulseCheck_M	10075226	80193	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	143399245	81275
T1	217860	766
T2	0	304
T3	0	1142
T4	30236	0
T5	64674	144
T6	38293	83
T11	0	1609
T12	0	308
T23	0	41
T26	1219	0
T27	3071	0
T28	12810	0
T29	4884	0
T30	2561	0
T33	3941	0
T34	0	60
T36	0	31

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10075226	80193
T1	144130	766
T2	0	304
T3	0	888
T4	216	0
T5	287	144
T6	165	83
T11	0	1609
T12	0	308
T23	0	41
T26	165	0
T27	417	0
T28	1551	0
T29	720	0
T30	375	0
T33	488	0
T34	0	60
T36	0	31

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71699037	80766	0	0
SrcPulseCheck_M	10075226	79712	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71699037	80766
T1	108929	765
T2	0	284
T3	0	1065
T4	15118	0
T5	32337	144
T6	19147	83
T11	0	1606
T12	0	308
T23	0	41
T26	609	0
T27	1535	0
T28	6403	0
T29	2442	0
T30	1281	0
T33	1968	0
T34	0	60
T36	0	31

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10075226	79712
T1	144130	765
T2	0	284
T3	0	833
T4	216	0
T5	287	144
T6	165	83
T11	0	1606
T12	0	308
T23	0	41
T26	165	0
T27	417	0
T28	1551	0
T29	720	0
T30	375	0
T33	488	0
T34	0	60
T36	0	31

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	308433880	99327	0	0
SrcPulseCheck_M	10128541	98323	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	308433880	99327
T1	457295	825
T2	0	331
T3	0	1246
T4	99047	0
T5	164826	204
T6	97807	119
T11	0	2113
T12	0	305
T23	0	65
T26	2361	0
T27	5966	0
T28	22163	0
T29	10287	0
T30	5362	0
T33	6974	0
T34	0	72
T36	0	31

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10128541	98323
T1	144190	825
T2	0	331
T3	0	1246
T4	216	0
T5	347	204
T6	201	119
T11	0	1810
T12	0	305
T23	0	65
T26	165	0
T27	417	0
T28	1551	0
T29	720	0
T30	375	0
T33	488	0
T34	0	72
T36	0	31

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	148146453	99025	0	0
SrcPulseCheck_M	10136540	98919	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	148146453	99025
T1	220657	869
T2	0	343
T3	0	1263
T4	47543	0
T5	84877	228
T6	46948	119
T11	0	2092
T12	0	266
T23	0	53
T26	1134	0
T27	2864	0
T28	10638	0
T29	4938	0
T30	2574	0
T33	3347	0
T34	0	56
T36	0	31

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	10136540	98919
T1	144238	869
T2	0	343
T3	0	1263
T4	216	0
T5	371	228
T6	201	119
T11	0	2092
T12	0	266
T23	0	53
T26	165	0
T27	417	0
T28	1551	0
T29	720	0
T30	375	0
T33	488	0
T34	0	56
T36	0	31

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb