Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T4,T1,T3
1	0	Covered	T5,T4,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1535761570	1509828	0	0
DstReqKnown_A	1934039296	1908192720	0	0
SrcAckBusyChk_A	1535761570	256953	0	0
SrcBusyKnown_A	1535761570	1506227140	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535761570	1509828	0	0
T1	1013950	8231	0	0
T2	0	2165	0	0
T3	0	6840	0	0
T4	237700	1218	0	0
T5	895860	1451	0	0
T6	1054100	1454	0	0
T11	0	35224	0	0
T23	0	484	0	0
T26	23150	0	0	0
T27	21470	0	0	0
T28	22150	0	0	0
T29	26740	0	0	0
T30	13400	0	0	0
T33	17430	0	0	0
T34	0	321	0	0
T35	0	282	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1934039296	1908192720	0	0
T4	574052	128604	0	0
T5	952284	951066	0	0
T6	557612	557214	0	0
T7	65566	64598	0	0
T8	13488	12930	0	0
T26	15180	14690	0	0
T27	38324	37458	0	0
T28	146580	145782	0	0
T29	64854	63406	0	0
T30	33850	33272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535761570	256953	0	0
T1	1013950	2485	0	0
T2	0	700	0	0
T3	0	2535	0	0
T4	237700	346	0	0
T5	895860	300	0	0
T6	1054100	180	0	0
T11	0	4355	0	0
T23	0	80	0	0
T26	23150	0	0	0
T27	21470	0	0	0
T28	22150	0	0	0
T29	26740	0	0	0
T30	13400	0	0	0
T33	17430	0	0	0
T34	0	100	0	0
T35	0	56	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535761570	1506227140	0	0
T4	237700	48950	0	0
T5	895860	894820	0	0
T6	1054100	1053440	0	0
T7	8270	8140	0	0
T8	21430	20460	0	0
T26	23150	22330	0	0
T27	21470	20860	0	0
T28	22150	22000	0	0
T29	26740	26080	0	0
T30	13400	13160	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153576157	89960	0	0
DstReqKnown_A	289417735	285037229	0	0
SrcAckBusyChk_A	153576157	22867	0	0
SrcBusyKnown_A	153576157	150622714	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	89960	0	0
T1	101395	617	0	0
T2	0	175	0	0
T3	0	628	0	0
T4	23770	61	0	0
T5	89586	103	0	0
T6	105410	104	0	0
T11	0	2179	0	0
T23	0	31	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	24	0	0
T35	0	15	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289417735	285037229	0	0
T4	95082	19535	0	0
T5	129428	129225	0	0
T6	76611	76545	0	0
T7	9939	9777	0	0
T8	2057	1964	0	0
T26	2267	2187	0	0
T27	5726	5564	0	0
T28	21276	21127	0	0
T29	9876	9631	0	0
T30	5147	5054	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	22867	0	0
T1	101395	246	0	0
T2	0	70	0	0
T3	0	250	0	0
T4	23770	24	0	0
T5	89586	30	0	0
T6	105410	18	0	0
T11	0	430	0	0
T23	0	8	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	10	0	0
T35	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	150622714	0	0
T4	23770	4895	0	0
T5	89586	89482	0	0
T6	105410	105344	0	0
T7	827	814	0	0
T8	2143	2046	0	0
T26	2315	2233	0	0
T27	2147	2086	0	0
T28	2215	2200	0	0
T29	2674	2608	0	0
T30	1340	1316	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153576157	134230	0	0
DstReqKnown_A	144663091	143572009	0	0
SrcAckBusyChk_A	153576157	22867	0	0
SrcBusyKnown_A	153576157	150622714	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	134230	0	0
T1	101395	837	0	0
T2	0	221	0	0
T3	0	628	0	0
T4	23770	85	0	0
T5	89586	146	0	0
T6	105410	153	0	0
T11	0	3478	0	0
T23	0	50	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	32	0	0
T35	0	20	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144663091	143572009	0	0
T4	30236	9767	0	0
T5	64674	64612	0	0
T6	38293	38272	0	0
T7	5015	4967	0	0
T8	1010	982	0	0
T26	1219	1191	0	0
T27	3071	3057	0	0
T28	12810	12796	0	0
T29	4884	4815	0	0
T30	2561	2527	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	22867	0	0
T1	101395	246	0	0
T2	0	70	0	0
T3	0	250	0	0
T4	23770	24	0	0
T5	89586	30	0	0
T6	105410	18	0	0
T11	0	430	0	0
T23	0	8	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	10	0	0
T35	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	150622714	0	0
T4	23770	4895	0	0
T5	89586	89482	0	0
T6	105410	105344	0	0
T7	827	814	0	0
T8	2143	2046	0	0
T26	2315	2233	0	0
T27	2147	2086	0	0
T28	2215	2200	0	0
T29	2674	2608	0	0
T30	1340	1316	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153576157	220977	0	0
DstReqKnown_A	72330963	71785543	0	0
SrcAckBusyChk_A	153576157	22867	0	0
SrcBusyKnown_A	153576157	150622714	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	220977	0	0
T1	101395	1174	0	0
T2	0	287	0	0
T3	0	856	0	0
T4	23770	122	0	0
T5	89586	232	0	0
T6	105410	246	0	0
T11	0	6112	0	0
T23	0	75	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	46	0	0
T35	0	31	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72330963	71785543	0	0
T4	15118	4884	0	0
T5	32337	32306	0	0
T6	19147	19137	0	0
T7	2507	2483	0	0
T8	505	491	0	0
T26	609	595	0	0
T27	1535	1528	0	0
T28	6403	6396	0	0
T29	2442	2408	0	0
T30	1281	1264	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	22867	0	0
T1	101395	246	0	0
T2	0	70	0	0
T3	0	250	0	0
T4	23770	24	0	0
T5	89586	30	0	0
T6	105410	18	0	0
T11	0	430	0	0
T23	0	8	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	10	0	0
T35	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	150622714	0	0
T4	23770	4895	0	0
T5	89586	89482	0	0
T6	105410	105344	0	0
T7	827	814	0	0
T8	2143	2046	0	0
T26	2315	2233	0	0
T27	2147	2086	0	0
T28	2215	2200	0	0
T29	2674	2608	0	0
T30	1340	1316	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153576157	88063	0	0
DstReqKnown_A	311155203	306488773	0	0
SrcAckBusyChk_A	153576157	22867	0	0
SrcBusyKnown_A	153576157	150622714	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	88063	0	0
T1	101395	617	0	0
T2	0	175	0	0
T3	0	628	0	0
T4	23770	61	0	0
T5	89586	99	0	0
T6	105410	84	0	0
T11	0	2141	0	0
T23	0	31	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	24	0	0
T35	0	14	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311155203	306488773	0	0
T4	99047	20349	0	0
T5	164826	164614	0	0
T6	97807	97738	0	0
T7	10353	10184	0	0
T8	2143	2046	0	0
T26	2361	2278	0	0
T27	5966	5797	0	0
T28	22163	22008	0	0
T29	10287	10033	0	0
T30	5362	5264	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	22867	0	0
T1	101395	246	0	0
T2	0	70	0	0
T3	0	250	0	0
T4	23770	24	0	0
T5	89586	30	0	0
T6	105410	18	0	0
T11	0	430	0	0
T23	0	8	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	10	0	0
T35	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	150622714	0	0
T4	23770	4895	0	0
T5	89586	89482	0	0
T6	105410	105344	0	0
T7	827	814	0	0
T8	2143	2046	0	0
T26	2315	2233	0	0
T27	2147	2086	0	0
T28	2215	2200	0	0
T29	2674	2608	0	0
T30	1340	1316	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153576157	132527	0	0
DstReqKnown_A	149452656	147212806	0	0
SrcAckBusyChk_A	153576157	22377	0	0
SrcBusyKnown_A	153576157	150622714	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	132527	0	0
T1	101395	834	0	0
T2	0	223	0	0
T3	0	628	0	0
T4	23770	55	0	0
T5	89586	145	0	0
T6	105410	136	0	0
T11	0	3484	0	0
T23	0	48	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	34	0	0
T35	0	13	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149452656	147212806	0	0
T4	47543	9767	0	0
T5	84877	84776	0	0
T6	46948	46915	0	0
T7	4969	4888	0	0
T8	1029	982	0	0
T26	1134	1094	0	0
T27	2864	2783	0	0
T28	10638	10564	0	0
T29	4938	4816	0	0
T30	2574	2527	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	22377	0	0
T1	101395	246	0	0
T2	0	70	0	0
T3	0	250	0	0
T4	23770	12	0	0
T5	89586	30	0	0
T6	105410	18	0	0
T11	0	430	0	0
T23	0	8	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	10	0	0
T35	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	150622714	0	0
T4	23770	4895	0	0
T5	89586	89482	0	0
T6	105410	105344	0	0
T7	827	814	0	0
T8	2143	2046	0	0
T26	2315	2233	0	0
T27	2147	2086	0	0
T28	2215	2200	0	0
T29	2674	2608	0	0
T30	1340	1316	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T4,T1,T3
1	0	Covered	T5,T4,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153576157	114234	0	0
DstReqKnown_A	289417735	285037229	0	0
SrcAckBusyChk_A	153576157	28660	0	0
SrcBusyKnown_A	153576157	150622714	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	114234	0	0
T1	101395	625	0	0
T2	0	174	0	0
T3	0	647	0	0
T4	23770	123	0	0
T5	89586	102	0	0
T6	105410	104	0	0
T11	0	2228	0	0
T23	0	32	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	24	0	0
T35	0	28	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289417735	285037229	0	0
T4	95082	19535	0	0
T5	129428	129225	0	0
T6	76611	76545	0	0
T7	9939	9777	0	0
T8	2057	1964	0	0
T26	2267	2187	0	0
T27	5726	5564	0	0
T28	21276	21127	0	0
T29	9876	9631	0	0
T30	5147	5054	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	28660	0	0
T1	101395	251	0	0
T2	0	70	0	0
T3	0	257	0	0
T4	23770	48	0	0
T5	89586	30	0	0
T6	105410	18	0	0
T11	0	441	0	0
T23	0	8	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	10	0	0
T35	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	150622714	0	0
T4	23770	4895	0	0
T5	89586	89482	0	0
T6	105410	105344	0	0
T7	827	814	0	0
T8	2143	2046	0	0
T26	2315	2233	0	0
T27	2147	2086	0	0
T28	2215	2200	0	0
T29	2674	2608	0	0
T30	1340	1316	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T4,T1,T3
1	0	Covered	T5,T4,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153576157	170004	0	0
DstReqKnown_A	144663091	143572009	0	0
SrcAckBusyChk_A	153576157	28799	0	0
SrcBusyKnown_A	153576157	150622714	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	170004	0	0
T1	101395	847	0	0
T2	0	220	0	0
T3	0	647	0	0
T4	23770	171	0	0
T5	89586	146	0	0
T6	105410	148	0	0
T11	0	3585	0	0
T23	0	48	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	34	0	0
T35	0	39	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144663091	143572009	0	0
T4	30236	9767	0	0
T5	64674	64612	0	0
T6	38293	38272	0	0
T7	5015	4967	0	0
T8	1010	982	0	0
T26	1219	1191	0	0
T27	3071	3057	0	0
T28	12810	12796	0	0
T29	4884	4815	0	0
T30	2561	2527	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	28799	0	0
T1	101395	251	0	0
T2	0	70	0	0
T3	0	257	0	0
T4	23770	48	0	0
T5	89586	30	0	0
T6	105410	18	0	0
T11	0	441	0	0
T23	0	8	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	10	0	0
T35	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	150622714	0	0
T4	23770	4895	0	0
T5	89586	89482	0	0
T6	105410	105344	0	0
T7	827	814	0	0
T8	2143	2046	0	0
T26	2315	2233	0	0
T27	2147	2086	0	0
T28	2215	2200	0	0
T29	2674	2608	0	0
T30	1340	1316	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T4,T1,T3
1	0	Covered	T5,T4,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153576157	279438	0	0
DstReqKnown_A	72330963	71785543	0	0
SrcAckBusyChk_A	153576157	28649	0	0
SrcBusyKnown_A	153576157	150622714	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	279438	0	0
T1	101395	1201	0	0
T2	0	296	0	0
T3	0	884	0	0
T4	23770	246	0	0
T5	89586	234	0	0
T6	105410	256	0	0
T11	0	6267	0	0
T23	0	88	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	45	0	0
T35	0	62	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72330963	71785543	0	0
T4	15118	4884	0	0
T5	32337	32306	0	0
T6	19147	19137	0	0
T7	2507	2483	0	0
T8	505	491	0	0
T26	609	595	0	0
T27	1535	1528	0	0
T28	6403	6396	0	0
T29	2442	2408	0	0
T30	1281	1264	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	28649	0	0
T1	101395	251	0	0
T2	0	70	0	0
T3	0	257	0	0
T4	23770	48	0	0
T5	89586	30	0	0
T6	105410	18	0	0
T11	0	441	0	0
T23	0	8	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	10	0	0
T35	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	150622714	0	0
T4	23770	4895	0	0
T5	89586	89482	0	0
T6	105410	105344	0	0
T7	827	814	0	0
T8	2143	2046	0	0
T26	2315	2233	0	0
T27	2147	2086	0	0
T28	2215	2200	0	0
T29	2674	2608	0	0
T30	1340	1316	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T4,T1,T3
1	0	Covered	T5,T4,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153576157	111975	0	0
DstReqKnown_A	311155203	306488773	0	0
SrcAckBusyChk_A	153576157	28757	0	0
SrcBusyKnown_A	153576157	150622714	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	111975	0	0
T1	101395	625	0	0
T2	0	174	0	0
T3	0	647	0	0
T4	23770	123	0	0
T5	89586	100	0	0
T6	105410	85	0	0
T11	0	2187	0	0
T23	0	30	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	24	0	0
T35	0	27	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311155203	306488773	0	0
T4	99047	20349	0	0
T5	164826	164614	0	0
T6	97807	97738	0	0
T7	10353	10184	0	0
T8	2143	2046	0	0
T26	2361	2278	0	0
T27	5966	5797	0	0
T28	22163	22008	0	0
T29	10287	10033	0	0
T30	5362	5264	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	28757	0	0
T1	101395	251	0	0
T2	0	70	0	0
T3	0	257	0	0
T4	23770	48	0	0
T5	89586	30	0	0
T6	105410	18	0	0
T11	0	441	0	0
T23	0	8	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	10	0	0
T35	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	150622714	0	0
T4	23770	4895	0	0
T5	89586	89482	0	0
T6	105410	105344	0	0
T7	827	814	0	0
T8	2143	2046	0	0
T26	2315	2233	0	0
T27	2147	2086	0	0
T28	2215	2200	0	0
T29	2674	2608	0	0
T30	1340	1316	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T4,T1,T3
1	0	Covered	T5,T4,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T4,T6
1	1	Covered	T5,T4,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T4,T6
0	0	1	Covered	T5,T4,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153576157	168420	0	0
DstReqKnown_A	149452656	147212806	0	0
SrcAckBusyChk_A	153576157	28243	0	0
SrcBusyKnown_A	153576157	150622714	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	168420	0	0
T1	101395	854	0	0
T2	0	220	0	0
T3	0	647	0	0
T4	23770	171	0	0
T5	89586	144	0	0
T6	105410	138	0	0
T11	0	3563	0	0
T23	0	51	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	34	0	0
T35	0	33	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149452656	147212806	0	0
T4	47543	9767	0	0
T5	84877	84776	0	0
T6	46948	46915	0	0
T7	4969	4888	0	0
T8	1029	982	0	0
T26	1134	1094	0	0
T27	2864	2783	0	0
T28	10638	10564	0	0
T29	4938	4816	0	0
T30	2574	2527	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	28243	0	0
T1	101395	251	0	0
T2	0	70	0	0
T3	0	257	0	0
T4	23770	46	0	0
T5	89586	30	0	0
T6	105410	18	0	0
T11	0	441	0	0
T23	0	8	0	0
T26	2315	0	0	0
T27	2147	0	0	0
T28	2215	0	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	0	0	0
T34	0	10	0	0
T35	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	150622714	0	0
T4	23770	4895	0	0
T5	89586	89482	0	0
T6	105410	105344	0	0
T7	827	814	0	0
T8	2143	2046	0	0
T26	2315	2233	0	0
T27	2147	2086	0	0
T28	2215	2200	0	0
T29	2674	2608	0	0
T30	1340	1316	0	0