Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	613033	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3519830

1

T4

6

T1

174

T14

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1017393	1			T1	46		T2	61		T16	76
values[0x0]	1432120	1			T4	23		T1	168		T14	1
values[0x1]	1683350	1			T4	8		T1	170		T14	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	338068	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3794795

1

T4

9

T1

231

T14

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16918	1			T2	3		T7	215		T8	1
valid_sources[0x01]	15847	1			T3	2		T7	332		T8	1
valid_sources[0x02]	16684	1			T7	169		T27	1		T9	1
valid_sources[0x03]	15482	1			T2	1		T16	2		T7	210
valid_sources[0x04]	15355	1			T2	1		T3	2		T19	1
valid_sources[0x05]	15792	1			T2	1		T3	3		T7	445
valid_sources[0x06]	15756	1			T2	2		T18	3		T21	1
valid_sources[0x07]	15406	1			T2	3		T16	3		T3	1
valid_sources[0x08]	16361	1			T3	2		T136	1		T7	2
valid_sources[0x09]	15090	1			T2	1		T3	3		T36	126
valid_sources[0x0a]	15607	1			T2	4		T3	3		T21	1
valid_sources[0x0b]	15627	1			T4	1		T2	4		T3	2
valid_sources[0x0c]	16612	1			T2	1		T3	2		T19	1
valid_sources[0x0d]	14306	1			T2	1		T3	3		T18	1
valid_sources[0x0e]	17320	1			T2	5		T7	328		T27	1
valid_sources[0x0f]	16588	1			T2	1		T3	1		T137	2
valid_sources[0x10]	15815	1			T2	6		T17	2		T3	5
valid_sources[0x11]	16589	1			T2	1		T9	3		T91	2
valid_sources[0x12]	15583	1			T2	2		T17	13		T7	412
valid_sources[0x13]	15664	1			T2	1		T3	5		T21	1
valid_sources[0x14]	16182	1			T16	4		T3	1		T135	13
valid_sources[0x15]	16757	1			T3	1		T20	441		T7	215
valid_sources[0x16]	14723	1			T2	2		T16	1		T3	1
valid_sources[0x17]	16890	1			T3	2		T8	1		T9	1
valid_sources[0x18]	16867	1			T2	6		T7	593		T8	2
valid_sources[0x19]	15950	1			T3	3		T19	1		T21	1
valid_sources[0x1a]	15608	1			T3	1		T19	1		T7	6
valid_sources[0x1b]	16433	1			T2	2		T3	1		T7	143
valid_sources[0x1c]	16678	1			T15	1		T2	3		T3	1
valid_sources[0x1d]	15843	1			T2	3		T3	2		T7	742
valid_sources[0x1e]	16171	1			T4	1		T3	2		T18	2
valid_sources[0x1f]	15870	1			T16	1		T7	181		T9	2
valid_sources[0x20]	14794	1			T4	1		T2	4		T7	10
valid_sources[0x21]	16454	1			T2	1		T3	1		T21	2
valid_sources[0x22]	15651	1			T4	2		T2	1		T3	2
valid_sources[0x23]	15951	1			T2	3		T16	1		T19	1
valid_sources[0x24]	14972	1			T3	2		T27	1		T8	1
valid_sources[0x25]	16312	1			T2	1		T16	1		T3	4
valid_sources[0x26]	18034	1			T2	1		T3	2		T21	2
valid_sources[0x27]	16044	1			T2	1		T7	586		T8	1
valid_sources[0x28]	17040	1			T21	2		T136	4		T7	200
valid_sources[0x29]	17223	1			T2	3		T3	1		T19	1
valid_sources[0x2a]	18061	1			T2	4		T3	2		T7	144
valid_sources[0x2b]	15868	1			T2	2		T3	3		T19	1
valid_sources[0x2c]	15017	1			T14	4		T2	1		T3	1
valid_sources[0x2d]	16239	1			T3	2		T42	6		T9	4
valid_sources[0x2e]	15008	1			T2	7		T3	1		T19	1
valid_sources[0x2f]	15973	1			T4	1		T3	2		T136	3
valid_sources[0x30]	17271	1			T4	1		T15	1		T2	1
valid_sources[0x31]	16325	1			T7	218		T8	1		T9	1
valid_sources[0x32]	18315	1			T2	4		T3	1		T135	1
valid_sources[0x33]	16526	1			T3	1		T18	2		T25	725
valid_sources[0x34]	17516	1			T2	3		T3	2		T27	2
valid_sources[0x35]	17007	1			T2	4		T21	1		T7	280
valid_sources[0x36]	16704	1			T3	1		T7	133		T87	3
valid_sources[0x37]	18023	1			T3	1		T7	93		T9	1
valid_sources[0x38]	16339	1			T2	3		T21	2		T7	208
valid_sources[0x39]	13890	1			T4	1		T15	1		T3	1
valid_sources[0x3a]	18772	1			T2	2		T3	3		T7	2
valid_sources[0x3b]	15562	1			T16	1		T3	2		T21	1
valid_sources[0x3c]	16412	1			T15	2		T2	1		T3	3
valid_sources[0x3d]	17088	1			T2	1		T3	3		T18	1
valid_sources[0x3e]	16015	1			T16	3		T7	301		T89	1
valid_sources[0x3f]	16979	1			T3	5		T7	254		T9	1
valid_sources[0x40]	15904	1			T4	1		T3	1		T7	1
valid_sources[0x41]	14920	1			T3	1		T7	304		T87	1
valid_sources[0x42]	15226	1			T4	1		T2	1		T3	2
valid_sources[0x43]	16427	1			T2	2		T3	5		T19	1
valid_sources[0x44]	14709	1			T2	2		T3	3		T19	4
valid_sources[0x45]	14827	1			T2	1		T135	2		T136	2
valid_sources[0x46]	14423	1			T3	1		T7	9		T87	2
valid_sources[0x47]	16386	1			T2	5		T7	400		T27	3
valid_sources[0x48]	16094	1			T2	1		T3	6		T7	333
valid_sources[0x49]	15795	1			T4	1		T2	5		T27	2
valid_sources[0x4a]	15474	1			T2	4		T3	4		T19	1
valid_sources[0x4b]	14890	1			T19	1		T21	1		T7	17
valid_sources[0x4c]	16947	1			T3	1		T18	1		T7	593
valid_sources[0x4d]	17146	1			T3	2		T7	120		T27	2
valid_sources[0x4e]	15826	1			T2	2		T3	4		T21	1
valid_sources[0x4f]	16763	1			T15	1		T7	405		T8	1
valid_sources[0x50]	14971	1			T2	4		T3	1		T21	1
valid_sources[0x51]	14958	1			T4	1		T3	2		T21	1
valid_sources[0x52]	14825	1			T2	4		T16	6		T3	1
valid_sources[0x53]	16899	1			T3	4		T7	2		T8	2
valid_sources[0x54]	15506	1			T2	3		T3	4		T21	1
valid_sources[0x55]	15991	1			T4	1		T2	6		T3	2
valid_sources[0x56]	15217	1			T2	3		T16	9		T21	1
valid_sources[0x57]	15103	1			T2	3		T3	2		T21	1
valid_sources[0x58]	15498	1			T3	1		T18	1		T21	2
valid_sources[0x59]	17291	1			T15	1		T2	1		T3	3
valid_sources[0x5a]	16121	1			T4	1		T2	3		T3	1
valid_sources[0x5b]	16499	1			T2	2		T3	2		T21	3
valid_sources[0x5c]	16003	1			T2	1		T18	2		T137	1
valid_sources[0x5d]	17539	1			T2	4		T3	1		T21	1
valid_sources[0x5e]	15414	1			T2	1		T3	1		T7	188
valid_sources[0x5f]	17154	1			T15	1		T2	6		T3	1
valid_sources[0x60]	16074	1			T4	1		T21	1		T8	2
valid_sources[0x61]	16472	1			T2	1		T16	1		T3	2
valid_sources[0x62]	14944	1			T2	3		T16	9		T3	1
valid_sources[0x63]	16800	1			T2	1		T3	3		T21	1
valid_sources[0x64]	15730	1			T4	1		T15	1		T2	1
valid_sources[0x65]	15037	1			T2	3		T3	2		T7	205
valid_sources[0x66]	15413	1			T2	1		T16	2		T3	5
valid_sources[0x67]	17071	1			T3	3		T21	1		T7	189
valid_sources[0x68]	15600	1			T7	6		T27	2		T9	1
valid_sources[0x69]	14942	1			T4	1		T2	1		T3	1
valid_sources[0x6a]	17094	1			T2	1		T3	1		T7	2
valid_sources[0x6b]	16148	1			T2	2		T3	2		T123	1
valid_sources[0x6c]	16389	1			T2	4		T7	3		T9	1
valid_sources[0x6d]	15772	1			T2	3		T3	1		T8	1
valid_sources[0x6e]	15431	1			T15	1		T3	2		T21	1
valid_sources[0x6f]	17526	1			T2	1		T3	2		T7	253
valid_sources[0x70]	16738	1			T2	1		T3	2		T136	4
valid_sources[0x71]	15264	1			T19	1		T7	119		T87	1
valid_sources[0x72]	17502	1			T4	1		T2	4		T16	10
valid_sources[0x73]	15762	1			T2	2		T3	1		T7	17
valid_sources[0x74]	16828	1			T3	1		T7	178		T27	2
valid_sources[0x75]	16958	1			T17	2		T3	1		T7	1
valid_sources[0x76]	16543	1			T7	321		T27	1		T42	5
valid_sources[0x77]	16293	1			T2	4		T3	1		T135	14
valid_sources[0x78]	18613	1			T2	1		T3	2		T7	538
valid_sources[0x79]	14382	1			T16	3		T3	2		T21	4
valid_sources[0x7a]	15097	1			T3	4		T18	1		T21	1
valid_sources[0x7b]	15831	1			T2	8		T18	1		T21	1
valid_sources[0x7c]	16859	1			T2	1		T3	1		T19	1
valid_sources[0x7d]	16539	1			T2	3		T7	182		T168	1
valid_sources[0x7e]	17733	1			T3	1		T7	90		T87	1
valid_sources[0x7f]	15376	1			T2	7		T3	3		T18	2
valid_sources[0x80]	15871	1			T15	1		T2	3		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

888283

1

T1

23

T2

32

T16

46

values[0x0]

all_enables

biggest_size

1338948

1

T4

5

T1

95

T15

6

values[0x1]

all_enables

biggest_size

1292599

1

T4

1

T1

56

T14

1