Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	825069390	82494	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	825069390	82494	0	0
T1	904070	412	0	0
T2	1077235	582	0	0
T3	246325	92	0	0
T5	7535	0	0	0
T7	0	719	0	0
T8	0	218	0	0
T9	0	293	0	0
T10	0	162	0	0
T11	0	41	0	0
T12	0	488	0	0
T13	0	129	0	0
T14	6405	0	0	0
T15	4140	0	0	0
T16	18370	0	0	0
T17	11965	0	0	0
T18	11230	0	0	0
T19	11180	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165013878	12090	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165013878	12090	0	0
T1	180814	60	0	0
T2	215447	85	0	0
T3	49265	15	0	0
T5	1507	0	0	0
T7	0	109	0	0
T8	0	33	0	0
T9	0	43	0	0
T10	0	21	0	0
T11	0	7	0	0
T12	0	61	0	0
T13	0	20	0	0
T14	1281	0	0	0
T15	828	0	0	0
T16	3674	0	0	0
T17	2393	0	0	0
T18	2246	0	0	0
T19	2236	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165013878	16508	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165013878	16508	0	0
T1	180814	82	0	0
T2	215447	117	0	0
T3	49265	19	0	0
T5	1507	0	0	0
T7	0	147	0	0
T8	0	43	0	0
T9	0	59	0	0
T10	0	32	0	0
T11	0	8	0	0
T12	0	96	0	0
T13	0	26	0	0
T14	1281	0	0	0
T15	828	0	0	0
T16	3674	0	0	0
T17	2393	0	0	0
T18	2246	0	0	0
T19	2236	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165013878	25458	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165013878	25458	0	0
T1	180814	139	0	0
T2	215447	189	0	0
T3	49265	26	0	0
T5	1507	0	0	0
T7	0	215	0	0
T8	0	68	0	0
T9	0	96	0	0
T10	0	55	0	0
T11	0	12	0	0
T12	0	162	0	0
T13	0	37	0	0
T14	1281	0	0	0
T15	828	0	0	0
T16	3674	0	0	0
T17	2393	0	0	0
T18	2246	0	0	0
T19	2236	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165013878	11826	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165013878	11826	0	0
T1	180814	52	0	0
T2	215447	73	0	0
T3	49265	14	0	0
T5	1507	0	0	0
T7	0	105	0	0
T8	0	30	0	0
T9	0	37	0	0
T10	0	21	0	0
T11	0	6	0	0
T12	0	70	0	0
T13	0	20	0	0
T14	1281	0	0	0
T15	828	0	0	0
T16	3674	0	0	0
T17	2393	0	0	0
T18	2246	0	0	0
T19	2236	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165013878	16612	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165013878	16612	0	0
T1	180814	79	0	0
T2	215447	118	0	0
T3	49265	18	0	0
T5	1507	0	0	0
T7	0	143	0	0
T8	0	44	0	0
T9	0	58	0	0
T10	0	33	0	0
T11	0	8	0	0
T12	0	99	0	0
T13	0	26	0	0
T14	1281	0	0	0
T15	828	0	0	0
T16	3674	0	0	0
T17	2393	0	0	0
T18	2246	0	0	0
T19	2236	0	0	0