Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T24,T25,T26

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	165013878	162543129	0	0
AllClkBypReqTrue_A	165013878	137015	0	0
IoClkBypReqFalse_A	165013878	162461296	0	2415
IoClkBypReqTrue_A	165013878	214054	0	0
LcClkBypAckFalse_A	165013878	162555986	0	0
LcClkBypAckTrue_A	165013878	124158	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165013878	162543129	0	0
T1	180814	180541	0	0
T2	215447	215188	0	0
T3	49265	49208	0	0
T4	975	960	0	0
T5	1507	1426	0	0
T14	1281	1157	0	0
T15	828	797	0	0
T16	3674	3476	0	0
T17	2393	2038	0	0
T18	2246	2008	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165013878	137015	0	0
T3	49265	0	0	0
T7	0	947	0	0
T17	2393	157	0	0
T18	2246	140	0	0
T19	2236	177	0	0
T20	234202	0	0	0
T21	16478	0	0	0
T36	2410	0	0	0
T41	0	163	0	0
T76	1282	80	0	0
T83	0	27	0	0
T84	0	48	0	0
T135	1666	147	0	0
T136	0	90	0	0
T137	1645	0	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165013878	162461296	0	2415
T1	180814	180539	0	3
T2	215447	215186	0	3
T3	49265	49206	0	3
T4	975	958	0	3
T5	1507	1424	0	3
T14	1281	1155	0	3
T15	828	795	0	3
T16	3674	3474	0	3
T17	2393	1905	0	3
T18	2246	1974	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165013878	214054	0	0
T3	49265	0	0	0
T7	0	1404	0	0
T17	2393	288	0	0
T18	2246	172	0	0
T19	2236	327	0	0
T20	234202	0	0	0
T21	16478	0	0	0
T36	2410	0	0	0
T41	0	167	0	0
T76	1282	212	0	0
T83	0	164	0	0
T135	1666	78	0	0
T136	0	365	0	0
T137	1645	131	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165013878	162555986	0	0
T1	180814	180541	0	0
T2	215447	215188	0	0
T3	49265	49208	0	0
T4	975	960	0	0
T5	1507	1426	0	0
T14	1281	1157	0	0
T15	828	797	0	0
T16	3674	3476	0	0
T17	2393	2046	0	0
T18	2246	1997	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165013878	124158	0	0
T3	49265	0	0	0
T7	0	890	0	0
T17	2393	149	0	0
T18	2246	151	0	0
T19	2236	203	0	0
T20	234202	0	0	0
T21	16478	0	0	0
T36	2410	0	0	0
T41	0	116	0	0
T76	1282	98	0	0
T83	0	112	0	0
T135	1666	47	0	0
T136	0	149	0	0
T137	1645	42	0	0