Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16496	0	0
TransStop_A	2147483647	8493	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16496	0	0
T3	788260	0	0	0
T7	0	99	0	0
T16	14700	40	0	0
T17	9576	0	0	0
T18	14264	0	0	0
T19	17548	0	0	0
T20	869752	0	0	0
T21	263660	0	0	0
T25	0	14	0	0
T36	40176	36	0	0
T41	0	67	0	0
T42	0	4	0	0
T76	22300	0	0	0
T85	0	11	0	0
T88	0	38	0	0
T89	0	12	0	0
T135	33344	0	0	0
T138	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8493	0	0
T3	788260	0	0	0
T7	0	41	0	0
T16	14700	24	0	0
T17	9576	0	0	0
T18	14264	0	0	0
T19	17548	0	0	0
T20	869752	0	0	0
T21	263660	0	0	0
T25	0	12	0	0
T36	40176	21	0	0
T41	0	43	0	0
T42	0	4	0	0
T76	22300	0	0	0
T85	0	4	0	0
T88	0	18	0	0
T89	0	7	0	0
T135	33344	0	0	0
T138	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	544924763	4116	0	0
TransStop_A	544924763	2118	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924763	4116	0	0
T3	197065	0	0	0
T7	0	19	0	0
T16	3675	14	0	0
T17	2394	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T20	217438	0	0	0
T21	65915	0	0	0
T25	0	2	0	0
T36	10044	11	0	0
T41	0	18	0	0
T42	0	1	0	0
T76	5575	0	0	0
T85	0	3	0	0
T88	0	10	0	0
T89	0	2	0	0
T135	8336	0	0	0
T138	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924763	2118	0	0
T3	197065	0	0	0
T7	0	10	0	0
T16	3675	7	0	0
T17	2394	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T20	217438	0	0	0
T21	65915	0	0	0
T25	0	2	0	0
T36	10044	7	0	0
T41	0	10	0	0
T42	0	1	0	0
T76	5575	0	0	0
T85	0	1	0	0
T88	0	4	0	0
T89	0	1	0	0
T135	8336	0	0	0
T138	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	544924763	4124	0	0
TransStop_A	544924763	2124	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924763	4124	0	0
T3	197065	0	0	0
T7	0	24	0	0
T16	3675	9	0	0
T17	2394	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T20	217438	0	0	0
T21	65915	0	0	0
T25	0	5	0	0
T36	10044	8	0	0
T41	0	15	0	0
T42	0	1	0	0
T76	5575	0	0	0
T85	0	2	0	0
T88	0	9	0	0
T89	0	3	0	0
T135	8336	0	0	0
T138	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924763	2124	0	0
T3	197065	0	0	0
T7	0	6	0	0
T16	3675	5	0	0
T17	2394	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T20	217438	0	0	0
T21	65915	0	0	0
T25	0	4	0	0
T36	10044	4	0	0
T41	0	13	0	0
T42	0	1	0	0
T76	5575	0	0	0
T85	0	1	0	0
T88	0	4	0	0
T89	0	2	0	0
T135	8336	0	0	0
T138	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	544924763	4119	0	0
TransStop_A	544924763	2135	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924763	4119	0	0
T3	197065	0	0	0
T7	0	28	0	0
T16	3675	8	0	0
T17	2394	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T20	217438	0	0	0
T21	65915	0	0	0
T25	0	5	0	0
T36	10044	8	0	0
T41	0	18	0	0
T42	0	1	0	0
T76	5575	0	0	0
T85	0	3	0	0
T88	0	11	0	0
T89	0	5	0	0
T135	8336	0	0	0
T138	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924763	2135	0	0
T3	197065	0	0	0
T7	0	14	0	0
T16	3675	7	0	0
T17	2394	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T20	217438	0	0	0
T21	65915	0	0	0
T25	0	4	0	0
T36	10044	4	0	0
T41	0	11	0	0
T42	0	1	0	0
T76	5575	0	0	0
T85	0	1	0	0
T88	0	5	0	0
T89	0	3	0	0
T135	8336	0	0	0
T138	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	544924763	4137	0	0
TransStop_A	544924763	2116	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924763	4137	0	0
T3	197065	0	0	0
T7	0	28	0	0
T16	3675	9	0	0
T17	2394	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T20	217438	0	0	0
T21	65915	0	0	0
T25	0	2	0	0
T36	10044	9	0	0
T41	0	16	0	0
T42	0	1	0	0
T76	5575	0	0	0
T85	0	3	0	0
T88	0	8	0	0
T89	0	2	0	0
T135	8336	0	0	0
T138	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924763	2116	0	0
T3	197065	0	0	0
T7	0	11	0	0
T16	3675	5	0	0
T17	2394	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T20	217438	0	0	0
T21	65915	0	0	0
T25	0	2	0	0
T36	10044	6	0	0
T41	0	9	0	0
T42	0	1	0	0
T76	5575	0	0	0
T85	0	1	0	0
T88	0	5	0	0
T89	0	1	0	0
T135	8336	0	0	0
T138	0	1	0	0