Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	165013878	19339301	0	55

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165013878	19339301	0	55
T1	180814	47278	0	1
T2	215447	70429	0	1
T3	49265	6987	0	1
T5	1507	0	0	0
T7	0	915711	0	0
T8	0	18821	0	1
T9	0	35709	0	1
T10	0	22183	0	0
T11	0	3981	0	1
T12	0	60996	0	0
T13	0	0	0	1
T14	1281	0	0	0
T15	828	0	0	0
T16	3674	0	0	0
T17	2393	0	0	0
T18	2246	0	0	0
T19	2236	0	0	0
T22	0	454	0	0
T28	0	0	0	1
T139	0	0	0	1
T140	0	0	0	1