Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	165894211	5140799	0	0
clk_enables_rd_A	165894211	59218	0	0
clk_hints_rd_A	165894211	52819	0	0
extclk_ctrl_rd_A	165894211	65255	0	0
extclk_ctrl_regwen_rd_A	165894211	50322	0	0
jitter_enable_rd_A	165894211	73450	0	0
jitter_regwen_rd_A	165894211	57348	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165894211	5140799	0	0
T7	164601	57118	0	0
T27	71196	0	0	0
T32	0	132753	0	0
T39	0	125500	0	0
T40	0	40612	0	0
T41	13322	0	0	0
T77	0	73044	0	0
T78	0	29790	0	0
T79	0	90657	0	0
T80	0	65125	0	0
T81	0	39453	0	0
T82	0	122033	0	0
T83	1212	0	0	0
T84	1364	0	0	0
T85	1570	0	0	0
T86	1732	0	0	0
T87	1789	0	0	0
T88	3859	0	0	0
T89	1516	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165894211	59218	0	0
T9	169124	0	0	0
T10	158350	0	0	0
T34	0	4304	0	0
T78	0	1142	0	0
T90	39807	0	0	0
T91	64506	0	0	0
T102	0	8	0	0
T138	2293	6	0	0
T155	0	10	0	0
T156	0	2	0	0
T157	0	3	0	0
T158	0	784	0	0
T159	0	1	0	0
T160	0	5	0	0
T161	1741	0	0	0
T162	2167	0	0	0
T163	1584	0	0	0
T164	1683	0	0	0
T165	1587	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165894211	52819	0	0
T9	169124	0	0	0
T10	158350	0	0	0
T34	0	3598	0	0
T78	0	1062	0	0
T90	39807	0	0	0
T91	64506	0	0	0
T102	0	2	0	0
T138	2293	2	0	0
T155	0	6	0	0
T156	0	3	0	0
T158	0	808	0	0
T159	0	1	0	0
T161	1741	0	0	0
T162	2167	0	0	0
T163	1584	0	0	0
T164	1683	0	0	0
T165	1587	0	0	0
T166	0	9	0	0
T167	0	9	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165894211	65255	0	0
T20	234202	0	0	0
T21	16478	0	0	0
T24	3328	14	0	0
T25	364994	0	0	0
T36	2410	0	0	0
T37	892	0	0	0
T38	1191	0	0	0
T76	1282	15	0	0
T123	0	15	0	0
T135	1666	0	0	0
T137	1645	21	0	0
T155	0	84	0	0
T168	0	61	0	0
T169	0	46	0	0
T170	0	2	0	0
T171	0	2	0	0
T172	0	56	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165894211	50322	0	0
T7	164601	0	0	0
T24	3328	11	0	0
T25	364994	0	0	0
T26	10560	0	0	0
T34	0	3637	0	0
T37	892	0	0	0
T38	1191	0	0	0
T78	0	1036	0	0
T83	1212	0	0	0
T84	1364	0	0	0
T126	1630	0	0	0
T136	1686	0	0	0
T158	0	716	0	0
T173	0	38	0	0
T174	0	28	0	0
T175	0	5395	0	0
T176	0	30	0	0
T177	0	1169	0	0
T178	0	23	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165894211	73450	0	0
T9	169124	0	0	0
T10	158350	0	0	0
T78	0	2453	0	0
T90	39807	0	0	0
T91	64506	0	0	0
T102	0	120	0	0
T138	2293	124	0	0
T155	0	211	0	0
T156	0	108	0	0
T157	0	115	0	0
T158	0	953	0	0
T161	1741	0	0	0
T162	2167	0	0	0
T163	1584	0	0	0
T164	1683	0	0	0
T165	1587	0	0	0
T166	0	117	0	0
T167	0	71	0	0
T179	0	97	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165894211	57348	0	0
T34	0	3834	0	0
T78	116134	1114	0	0
T100	2625	0	0	0
T101	16436	0	0	0
T102	2090	0	0	0
T103	997	0	0	0
T104	1506	0	0	0
T105	1134	0	0	0
T106	1624	0	0	0
T107	895	0	0	0
T108	2335	0	0	0
T158	0	882	0	0
T175	0	6312	0	0
T177	0	1218	0	0
T180	0	5694	0	0
T181	0	3711	0	0
T182	0	6627	0	0
T183	0	2809	0	0
T184	0	3098	0	0