Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T25
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50024	0	0
CgEnOn_A	2147483647	40447	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50024	0	0
T1	406735	3	0	0
T2	2315868	3	0	0
T3	2033518	3	0	0
T4	23361	38	0	0
T5	14041	57	0	0
T7	0	25	0	0
T14	13520	3	0	0
T15	35460	33	0	0
T16	37736	17	0	0
T17	24779	3	0	0
T18	37274	3	0	0
T19	36198	0	0	0
T25	0	2	0	0
T36	0	11	0	0
T37	0	23	0	0
T38	0	14	0	0
T76	45979	0	0	0
T79	0	5	0	0
T107	0	5	0	0
T185	0	20	0	0
T186	0	10	0	0
T187	0	25	0	0
T188	0	20	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40447	0	0
T1	406735	0	0	0
T2	2315868	0	0	0
T3	2033518	0	0	0
T4	23361	35	0	0
T5	14041	54	0	0
T7	0	183	0	0
T14	13520	0	0	0
T15	35460	30	0	0
T16	37736	14	0	0
T17	24779	0	0	0
T18	37274	0	0	0
T19	36198	0	0	0
T25	0	2	0	0
T36	0	11	0	0
T37	0	35	0	0
T38	0	20	0	0
T41	0	96	0	0
T42	0	3	0	0
T76	45979	0	0	0
T79	0	4	0	0
T85	0	3	0	0
T107	0	5	0	0
T126	0	31	0	0
T185	0	32	0	0
T186	0	10	0	0
T187	0	25	0	0
T188	0	20	0	0
T189	0	2	0	0
T190	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T25
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	255607360	158	0	0
CgEnOn_A	255607360	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255607360	158	0	0
T2	107663	0	0	0
T3	94548	0	0	0
T5	666	6	0	0
T7	0	1	0	0
T14	608	0	0	0
T15	1611	0	0	0
T16	1718	0	0	0
T17	1170	0	0	0
T18	1830	0	0	0
T19	2266	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T76	2872	0	0	0
T79	0	1	0	0
T107	0	1	0	0
T185	0	4	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255607360	158	0	0
T2	107663	0	0	0
T3	94548	0	0	0
T5	666	6	0	0
T7	0	1	0	0
T14	608	0	0	0
T15	1611	0	0	0
T16	1718	0	0	0
T17	1170	0	0	0
T18	1830	0	0	0
T19	2266	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T76	2872	0	0	0
T79	0	1	0	0
T107	0	1	0	0
T185	0	4	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T25
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	127803126	158	0	0
CgEnOn_A	127803126	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127803126	158	0	0
T2	53832	0	0	0
T3	47274	0	0	0
T5	333	6	0	0
T7	0	1	0	0
T14	304	0	0	0
T15	806	0	0	0
T16	859	0	0	0
T17	584	0	0	0
T18	915	0	0	0
T19	1133	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T76	1435	0	0	0
T79	0	1	0	0
T107	0	1	0	0
T185	0	4	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127803126	158	0	0
T2	53832	0	0	0
T3	47274	0	0	0
T5	333	6	0	0
T7	0	1	0	0
T14	304	0	0	0
T15	806	0	0	0
T16	859	0	0	0
T17	584	0	0	0
T18	915	0	0	0
T19	1133	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T76	1435	0	0	0
T79	0	1	0	0
T107	0	1	0	0
T185	0	4	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T25
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	512817371	158	0	0
CgEnOn_A	512817371	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512817371	158	0	0
T2	215447	0	0	0
T3	189175	0	0	0
T5	1356	6	0	0
T7	0	1	0	0
T14	1267	0	0	0
T15	3316	0	0	0
T16	3528	0	0	0
T17	2298	0	0	0
T18	3423	0	0	0
T19	4211	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T76	5352	0	0	0
T79	0	1	0	0
T107	0	1	0	0
T185	0	4	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512817371	147	0	0
T2	215447	0	0	0
T3	189175	0	0	0
T5	1356	6	0	0
T14	1267	0	0	0
T15	3316	0	0	0
T16	3528	0	0	0
T17	2298	0	0	0
T18	3423	0	0	0
T19	4211	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T76	5352	0	0	0
T107	0	1	0	0
T185	0	4	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	4	0	0
T189	0	2	0	0
T190	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T25
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544924323	142	0	0
CgEnOn_A	544924323	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924323	142	0	0
T2	224432	0	0	0
T3	197064	0	0	0
T5	1337	6	0	0
T7	0	1	0	0
T14	1320	0	0	0
T15	3454	0	0	0
T16	3674	0	0	0
T17	2393	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T37	0	3	0	0
T38	0	4	0	0
T76	5575	0	0	0
T107	0	2	0	0
T185	0	5	0	0
T186	0	2	0	0
T187	0	3	0	0
T188	0	6	0	0
T189	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924323	141	0	0
T2	224432	0	0	0
T3	197064	0	0	0
T5	1337	6	0	0
T7	0	1	0	0
T14	1320	0	0	0
T15	3454	0	0	0
T16	3674	0	0	0
T17	2393	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T37	0	3	0	0
T38	0	4	0	0
T76	5575	0	0	0
T107	0	2	0	0
T185	0	5	0	0
T186	0	2	0	0
T187	0	3	0	0
T188	0	6	0	0
T189	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T25
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	127803126	158	0	0
CgEnOn_A	127803126	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127803126	158	0	0
T2	53832	0	0	0
T3	47274	0	0	0
T5	333	6	0	0
T7	0	1	0	0
T14	304	0	0	0
T15	806	0	0	0
T16	859	0	0	0
T17	584	0	0	0
T18	915	0	0	0
T19	1133	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T76	1435	0	0	0
T79	0	1	0	0
T107	0	1	0	0
T185	0	4	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127803126	158	0	0
T2	53832	0	0	0
T3	47274	0	0	0
T5	333	6	0	0
T7	0	1	0	0
T14	304	0	0	0
T15	806	0	0	0
T16	859	0	0	0
T17	584	0	0	0
T18	915	0	0	0
T19	1133	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T76	1435	0	0	0
T79	0	1	0	0
T107	0	1	0	0
T185	0	4	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T25
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544924323	142	0	0
CgEnOn_A	544924323	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924323	142	0	0
T2	224432	0	0	0
T3	197064	0	0	0
T5	1337	6	0	0
T7	0	1	0	0
T14	1320	0	0	0
T15	3454	0	0	0
T16	3674	0	0	0
T17	2393	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T37	0	3	0	0
T38	0	4	0	0
T76	5575	0	0	0
T107	0	2	0	0
T185	0	5	0	0
T186	0	2	0	0
T187	0	3	0	0
T188	0	6	0	0
T189	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924323	141	0	0
T2	224432	0	0	0
T3	197064	0	0	0
T5	1337	6	0	0
T7	0	1	0	0
T14	1320	0	0	0
T15	3454	0	0	0
T16	3674	0	0	0
T17	2393	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T37	0	3	0	0
T38	0	4	0	0
T76	5575	0	0	0
T107	0	2	0	0
T185	0	5	0	0
T186	0	2	0	0
T187	0	3	0	0
T188	0	6	0	0
T189	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T25
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	127803126	158	0	0
CgEnOn_A	127803126	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127803126	158	0	0
T2	53832	0	0	0
T3	47274	0	0	0
T5	333	6	0	0
T7	0	1	0	0
T14	304	0	0	0
T15	806	0	0	0
T16	859	0	0	0
T17	584	0	0	0
T18	915	0	0	0
T19	1133	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T76	1435	0	0	0
T79	0	1	0	0
T107	0	1	0	0
T185	0	4	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127803126	158	0	0
T2	53832	0	0	0
T3	47274	0	0	0
T5	333	6	0	0
T7	0	1	0	0
T14	304	0	0	0
T15	806	0	0	0
T16	859	0	0	0
T17	584	0	0	0
T18	915	0	0	0
T19	1133	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T76	1435	0	0	0
T79	0	1	0	0
T107	0	1	0	0
T185	0	4	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T37,T38
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	255607360	7977	0	0
CgEnOn_A	255607360	5593	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255607360	7977	0	0
T1	90340	1	0	0
T2	107663	1	0	0
T3	94548	1	0	0
T4	5179	13	0	0
T5	666	7	0	0
T14	608	1	0	0
T15	1611	10	0	0
T16	1718	1	0	0
T17	1170	1	0	0
T18	1830	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255607360	5593	0	0
T1	90340	0	0	0
T2	107663	0	0	0
T3	94548	0	0	0
T4	5179	12	0	0
T5	666	6	0	0
T7	0	49	0	0
T14	608	0	0	0
T15	1611	9	0	0
T16	1718	0	0	0
T17	1170	0	0	0
T18	1830	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	26	0	0
T42	0	1	0	0
T126	0	10	0	0
T185	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T37,T38
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	127803126	7954	0	0
CgEnOn_A	127803126	5570	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127803126	7954	0	0
T1	45170	1	0	0
T2	53832	1	0	0
T3	47274	1	0	0
T4	2589	13	0	0
T5	333	7	0	0
T14	304	1	0	0
T15	806	12	0	0
T16	859	1	0	0
T17	584	1	0	0
T18	915	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127803126	5570	0	0
T1	45170	0	0	0
T2	53832	0	0	0
T3	47274	0	0	0
T4	2589	12	0	0
T5	333	6	0	0
T7	0	55	0	0
T14	304	0	0	0
T15	806	11	0	0
T16	859	0	0	0
T17	584	0	0	0
T18	915	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	25	0	0
T42	0	1	0	0
T126	0	11	0	0
T185	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T37,T38
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	512817371	7985	0	0
CgEnOn_A	512817371	5590	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512817371	7985	0	0
T1	180814	1	0	0
T2	215447	1	0	0
T3	189175	1	0	0
T4	10396	12	0	0
T5	1356	7	0	0
T14	1267	1	0	0
T15	3316	11	0	0
T16	3528	1	0	0
T17	2298	1	0	0
T18	3423	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512817371	5590	0	0
T1	180814	0	0	0
T2	215447	0	0	0
T3	189175	0	0	0
T4	10396	11	0	0
T5	1356	6	0	0
T7	0	55	0	0
T14	1267	0	0	0
T15	3316	10	0	0
T16	3528	0	0	0
T17	2298	0	0	0
T18	3423	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	27	0	0
T42	0	1	0	0
T126	0	10	0	0
T185	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T37,T38
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	261430617	7970	0	0
CgEnOn_A	261430617	5573	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261430617	7970	0	0
T1	90411	1	0	0
T2	107728	1	0	0
T3	94592	1	0	0
T4	5197	13	0	0
T5	643	7	0	0
T14	634	1	0	0
T15	1658	12	0	0
T16	1764	1	0	0
T17	1149	1	0	0
T18	1712	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261430617	5573	0	0
T1	90411	0	0	0
T2	107728	0	0	0
T3	94592	0	0	0
T4	5197	12	0	0
T5	643	6	0	0
T7	0	57	0	0
T14	634	0	0	0
T15	1658	11	0	0
T16	1764	0	0	0
T17	1149	0	0	0
T18	1712	0	0	0
T37	0	4	0	0
T38	0	3	0	0
T41	0	26	0	0
T42	0	1	0	0
T126	0	10	0	0
T185	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T25
1	0	Covered	T16,T36,T25
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544924323	4258	0	0
CgEnOn_A	544924323	4257	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924323	4258	0	0
T2	224432	0	0	0
T3	197064	0	0	0
T5	1337	6	0	0
T7	0	20	0	0
T14	1320	0	0	0
T15	3454	0	0	0
T16	3674	14	0	0
T17	2393	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T25	0	2	0	0
T36	0	11	0	0
T37	0	3	0	0
T38	0	4	0	0
T41	0	18	0	0
T76	5575	0	0	0
T85	0	3	0	0
T88	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924323	4257	0	0
T2	224432	0	0	0
T3	197064	0	0	0
T5	1337	6	0	0
T7	0	20	0	0
T14	1320	0	0	0
T15	3454	0	0	0
T16	3674	14	0	0
T17	2393	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T25	0	2	0	0
T36	0	11	0	0
T37	0	3	0	0
T38	0	4	0	0
T41	0	18	0	0
T76	5575	0	0	0
T85	0	3	0	0
T88	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T25
1	0	Covered	T16,T36,T25
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544924323	4266	0	0
CgEnOn_A	544924323	4265	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924323	4266	0	0
T2	224432	0	0	0
T3	197064	0	0	0
T5	1337	6	0	0
T7	0	25	0	0
T14	1320	0	0	0
T15	3454	0	0	0
T16	3674	9	0	0
T17	2393	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T25	0	5	0	0
T36	0	8	0	0
T37	0	3	0	0
T38	0	4	0	0
T41	0	15	0	0
T76	5575	0	0	0
T85	0	2	0	0
T88	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924323	4265	0	0
T2	224432	0	0	0
T3	197064	0	0	0
T5	1337	6	0	0
T7	0	25	0	0
T14	1320	0	0	0
T15	3454	0	0	0
T16	3674	9	0	0
T17	2393	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T25	0	5	0	0
T36	0	8	0	0
T37	0	3	0	0
T38	0	4	0	0
T41	0	15	0	0
T76	5575	0	0	0
T85	0	2	0	0
T88	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T25
1	0	Covered	T16,T36,T25
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544924323	4261	0	0
CgEnOn_A	544924323	4260	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924323	4261	0	0
T2	224432	0	0	0
T3	197064	0	0	0
T5	1337	6	0	0
T7	0	29	0	0
T14	1320	0	0	0
T15	3454	0	0	0
T16	3674	8	0	0
T17	2393	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T25	0	5	0	0
T36	0	8	0	0
T37	0	3	0	0
T38	0	4	0	0
T41	0	18	0	0
T76	5575	0	0	0
T85	0	3	0	0
T88	0	11	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924323	4260	0	0
T2	224432	0	0	0
T3	197064	0	0	0
T5	1337	6	0	0
T7	0	29	0	0
T14	1320	0	0	0
T15	3454	0	0	0
T16	3674	8	0	0
T17	2393	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T25	0	5	0	0
T36	0	8	0	0
T37	0	3	0	0
T38	0	4	0	0
T41	0	18	0	0
T76	5575	0	0	0
T85	0	3	0	0
T88	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T24,T25
1	0	Covered	T16,T36,T25
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	544924323	4279	0	0
CgEnOn_A	544924323	4278	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924323	4279	0	0
T2	224432	0	0	0
T3	197064	0	0	0
T5	1337	6	0	0
T7	0	29	0	0
T14	1320	0	0	0
T15	3454	0	0	0
T16	3674	9	0	0
T17	2393	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T25	0	2	0	0
T36	0	9	0	0
T37	0	3	0	0
T38	0	4	0	0
T41	0	16	0	0
T76	5575	0	0	0
T85	0	3	0	0
T88	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544924323	4278	0	0
T2	224432	0	0	0
T3	197064	0	0	0
T5	1337	6	0	0
T7	0	29	0	0
T14	1320	0	0	0
T15	3454	0	0	0
T16	3674	9	0	0
T17	2393	0	0	0
T18	3566	0	0	0
T19	4387	0	0	0
T25	0	2	0	0
T36	0	9	0	0
T37	0	3	0	0
T38	0	4	0	0
T41	0	16	0	0
T76	5575	0	0	0
T85	0	3	0	0
T88	0	8	0	0