Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T15
0	1	Covered	T4,T15,T126
1	0	Covered	T4,T5,T15

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T15,T126
1	0	Covered	T5,T37,T38
1	1	Covered	T4,T5,T15

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1157660084	14412	0	0
GateOpen_A	1157660084	14412	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157660084	14412	0	0
T1	406736	0	0	0
T2	484673	0	0	0
T3	425589	0	0	0
T4	23363	20	0	0
T5	2998	24	0	0
T7	0	121	0	0
T14	2813	0	0	0
T15	7393	21	0	0
T16	7870	0	0	0
T17	5203	0	0	0
T18	7880	0	0	0
T37	0	16	0	0
T38	0	9	0	0
T41	0	74	0	0
T42	0	4	0	0
T126	0	21	0	0
T185	0	17	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157660084	14412	0	0
T1	406736	0	0	0
T2	484673	0	0	0
T3	425589	0	0	0
T4	23363	20	0	0
T5	2998	24	0	0
T7	0	121	0	0
T14	2813	0	0	0
T15	7393	21	0	0
T16	7870	0	0	0
T17	5203	0	0	0
T18	7880	0	0	0
T37	0	16	0	0
T38	0	9	0	0
T41	0	74	0	0
T42	0	4	0	0
T126	0	21	0	0
T185	0	17	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T15
0	1	Covered	T4,T15,T126
1	0	Covered	T4,T5,T15

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T15,T126
1	0	Covered	T5,T37,T38
1	1	Covered	T4,T5,T15

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	127803513	3604	0	0
GateOpen_A	127803513	3604	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127803513	3604	0	0
T1	45170	0	0	0
T2	53832	0	0	0
T3	47274	0	0	0
T4	2590	5	0	0
T5	333	6	0	0
T7	0	30	0	0
T14	304	0	0	0
T15	806	5	0	0
T16	859	0	0	0
T17	584	0	0	0
T18	915	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	16	0	0
T42	0	1	0	0
T126	0	6	0	0
T185	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127803513	3604	0	0
T1	45170	0	0	0
T2	53832	0	0	0
T3	47274	0	0	0
T4	2590	5	0	0
T5	333	6	0	0
T7	0	30	0	0
T14	304	0	0	0
T15	806	5	0	0
T16	859	0	0	0
T17	584	0	0	0
T18	915	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	16	0	0
T42	0	1	0	0
T126	0	6	0	0
T185	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T15
0	1	Covered	T4,T15,T126
1	0	Covered	T4,T5,T15

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T15,T126
1	0	Covered	T5,T37,T38
1	1	Covered	T4,T5,T15

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	255607763	3605	0	0
GateOpen_A	255607763	3605	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255607763	3605	0	0
T1	90340	0	0	0
T2	107664	0	0	0
T3	94548	0	0	0
T4	5179	5	0	0
T5	666	6	0	0
T7	0	29	0	0
T14	608	0	0	0
T15	1612	5	0	0
T16	1718	0	0	0
T17	1170	0	0	0
T18	1830	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	20	0	0
T42	0	1	0	0
T126	0	5	0	0
T185	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255607763	3605	0	0
T1	90340	0	0	0
T2	107664	0	0	0
T3	94548	0	0	0
T4	5179	5	0	0
T5	666	6	0	0
T7	0	29	0	0
T14	608	0	0	0
T15	1612	5	0	0
T16	1718	0	0	0
T17	1170	0	0	0
T18	1830	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	20	0	0
T42	0	1	0	0
T126	0	5	0	0
T185	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T15
0	1	Covered	T4,T15,T126
1	0	Covered	T4,T5,T15

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T15,T126
1	0	Covered	T5,T37,T38
1	1	Covered	T4,T5,T15

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	512817797	3593	0	0
GateOpen_A	512817797	3593	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512817797	3593	0	0
T1	180815	0	0	0
T2	215448	0	0	0
T3	189175	0	0	0
T4	10396	5	0	0
T5	1356	6	0	0
T7	0	32	0	0
T14	1267	0	0	0
T15	3316	5	0	0
T16	3528	0	0	0
T17	2299	0	0	0
T18	3423	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	20	0	0
T42	0	1	0	0
T126	0	6	0	0
T185	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512817797	3593	0	0
T1	180815	0	0	0
T2	215448	0	0	0
T3	189175	0	0	0
T4	10396	5	0	0
T5	1356	6	0	0
T7	0	32	0	0
T14	1267	0	0	0
T15	3316	5	0	0
T16	3528	0	0	0
T17	2299	0	0	0
T18	3423	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	20	0	0
T42	0	1	0	0
T126	0	6	0	0
T185	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T15
0	1	Covered	T4,T15,T126
1	0	Covered	T4,T5,T15

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T15,T126
1	0	Covered	T5,T37,T38
1	1	Covered	T4,T5,T15

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	261431011	3610	0	0
GateOpen_A	261431011	3610	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261431011	3610	0	0
T1	90411	0	0	0
T2	107729	0	0	0
T3	94592	0	0	0
T4	5198	5	0	0
T5	643	6	0	0
T7	0	30	0	0
T14	634	0	0	0
T15	1659	6	0	0
T16	1765	0	0	0
T17	1150	0	0	0
T18	1712	0	0	0
T37	0	4	0	0
T38	0	3	0	0
T41	0	18	0	0
T42	0	1	0	0
T126	0	4	0	0
T185	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261431011	3610	0	0
T1	90411	0	0	0
T2	107729	0	0	0
T3	94592	0	0	0
T4	5198	5	0	0
T5	643	6	0	0
T7	0	30	0	0
T14	634	0	0	0
T15	1659	6	0	0
T16	1765	0	0	0
T17	1150	0	0	0
T18	1712	0	0	0
T37	0	4	0	0
T38	0	3	0	0
T41	0	18	0	0
T42	0	1	0	0
T126	0	4	0	0
T185	0	5	0	0