SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
98.52 | 99.15 | 95.84 | 100.00 | 100.00 | 98.81 | 97.01 | 98.80 |
T1001 | /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3727225166 | Apr 04 02:38:41 PM PDT 24 | Apr 04 02:38:43 PM PDT 24 | 37283547 ps | ||
T1002 | /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1448465826 | Apr 04 02:39:11 PM PDT 24 | Apr 04 02:39:12 PM PDT 24 | 12160052 ps | ||
T1003 | /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2166213391 | Apr 04 02:39:05 PM PDT 24 | Apr 04 02:39:07 PM PDT 24 | 172352710 ps | ||
T1004 | /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.800889240 | Apr 04 02:39:00 PM PDT 24 | Apr 04 02:39:02 PM PDT 24 | 37015476 ps | ||
T1005 | /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2798993580 | Apr 04 02:39:02 PM PDT 24 | Apr 04 02:39:03 PM PDT 24 | 12479606 ps | ||
T1006 | /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.351842499 | Apr 04 02:39:05 PM PDT 24 | Apr 04 02:39:09 PM PDT 24 | 614640688 ps | ||
T1007 | /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2724062546 | Apr 04 02:38:56 PM PDT 24 | Apr 04 02:39:00 PM PDT 24 | 296575180 ps | ||
T1008 | /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2389225324 | Apr 04 02:39:01 PM PDT 24 | Apr 04 02:39:02 PM PDT 24 | 33981855 ps | ||
T1009 | /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.3693169069 | Apr 04 02:38:34 PM PDT 24 | Apr 04 02:38:38 PM PDT 24 | 326598660 ps | ||
T1010 | /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.2352066494 | Apr 04 02:38:39 PM PDT 24 | Apr 04 02:38:40 PM PDT 24 | 25771107 ps |
Test location | /workspace/coverage/default/8.clkmgr_frequency.1777400173 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 1970662946 ps |
CPU time | 8.57 seconds |
Started | Apr 04 03:46:39 PM PDT 24 |
Finished | Apr 04 03:46:48 PM PDT 24 |
Peak memory | 200748 kb |
Host | smart-d64ee6b9-791f-4d8b-8d77-ca3b0840a755 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777400173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.1777400173 |
Directory | /workspace/8.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.4106866453 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 36577849206 ps |
CPU time | 314.81 seconds |
Started | Apr 04 03:47:58 PM PDT 24 |
Finished | Apr 04 03:53:13 PM PDT 24 |
Peak memory | 209228 kb |
Host | smart-d1c02a71-acf3-415a-81ba-5c20843b3fa0 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4106866453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.4106866453 |
Directory | /workspace/26.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.410670083 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 236824055 ps |
CPU time | 2.15 seconds |
Started | Apr 04 02:38:50 PM PDT 24 |
Finished | Apr 04 02:38:53 PM PDT 24 |
Peak memory | 201116 kb |
Host | smart-b6ece77e-ca80-4cce-bd5a-25a007885796 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410670083 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 17.clkmgr_shadow_reg_errors.410670083 |
Directory | /workspace/17.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/default/9.clkmgr_extclk.2387995441 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 43892289 ps |
CPU time | 0.99 seconds |
Started | Apr 04 03:46:41 PM PDT 24 |
Finished | Apr 04 03:46:42 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-afbbdb63-bfc6-4d0f-8f9d-039fddc5772e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387995441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.2387995441 |
Directory | /workspace/9.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/19.clkmgr_regwen.829654556 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 398098478 ps |
CPU time | 2.71 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:30 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-dbbb28aa-0108-412b-bd6e-1a4b17e66fad |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829654556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.829654556 |
Directory | /workspace/19.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/2.clkmgr_sec_cm.114306206 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 834709556 ps |
CPU time | 4.49 seconds |
Started | Apr 04 03:46:17 PM PDT 24 |
Finished | Apr 04 03:46:21 PM PDT 24 |
Peak memory | 221436 kb |
Host | smart-dfb47412-a886-4c8f-a92a-06f93978c8b6 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114306206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr _sec_cm.114306206 |
Directory | /workspace/2.clkmgr_sec_cm/latest |
Test location | /workspace/coverage/default/4.clkmgr_stress_all.2438455193 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 3619068147 ps |
CPU time | 14.07 seconds |
Started | Apr 04 03:46:24 PM PDT 24 |
Finished | Apr 04 03:46:39 PM PDT 24 |
Peak memory | 201036 kb |
Host | smart-7b7bdc84-83be-4ef6-b380-a3d1d3e05f8e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438455193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.2438455193 |
Directory | /workspace/4.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.1420359792 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 85319393 ps |
CPU time | 1.12 seconds |
Started | Apr 04 03:46:55 PM PDT 24 |
Finished | Apr 04 03:46:56 PM PDT 24 |
Peak memory | 200584 kb |
Host | smart-3983e59c-69fe-4a0a-8bca-9025eb887c13 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420359792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.1420359792 |
Directory | /workspace/12.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/16.clkmgr_clk_status.1527574459 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 35870710 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:47:10 PM PDT 24 |
Finished | Apr 04 03:47:11 PM PDT 24 |
Peak memory | 199528 kb |
Host | smart-ed58d0a3-bc4e-4819-9344-1e71aab2c8f8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527574459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.1527574459 |
Directory | /workspace/16.clkmgr_clk_status/latest |
Test location | /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.1328726794 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 149378053 ps |
CPU time | 2.44 seconds |
Started | Apr 04 02:38:54 PM PDT 24 |
Finished | Apr 04 02:38:57 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-ea12394d-2f18-492f-b1c5-41a8d7f4dc5b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328726794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 18.clkmgr_tl_intg_err.1328726794 |
Directory | /workspace/18.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/default/13.clkmgr_alert_test.3863837549 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 18276361 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:47:09 PM PDT 24 |
Finished | Apr 04 03:47:10 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-a2e01a39-14fa-4db7-8fc6-03008bc0a092 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863837549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk mgr_alert_test.3863837549 |
Directory | /workspace/13.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.3967850701 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 98106280744 ps |
CPU time | 680.46 seconds |
Started | Apr 04 03:49:14 PM PDT 24 |
Finished | Apr 04 04:00:35 PM PDT 24 |
Peak memory | 213140 kb |
Host | smart-24c815fa-c6cc-4986-980b-ef3d36310201 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3967850701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.3967850701 |
Directory | /workspace/47.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.4054528108 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 95840335 ps |
CPU time | 1.82 seconds |
Started | Apr 04 02:39:05 PM PDT 24 |
Finished | Apr 04 02:39:07 PM PDT 24 |
Peak memory | 201132 kb |
Host | smart-5e2b8739-abc7-405f-b3f6-3466580fa8eb |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054528108 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.clkmgr_shadow_reg_errors.4054528108 |
Directory | /workspace/15.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.2504843022 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 11730739133 ps |
CPU time | 157.16 seconds |
Started | Apr 04 03:47:30 PM PDT 24 |
Finished | Apr 04 03:50:07 PM PDT 24 |
Peak memory | 209300 kb |
Host | smart-42a1fff4-ea0d-41bd-ad6d-fbd81e8d8b69 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2504843022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.2504843022 |
Directory | /workspace/21.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.3279176861 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 55330506817 ps |
CPU time | 797.42 seconds |
Started | Apr 04 03:46:53 PM PDT 24 |
Finished | Apr 04 04:00:10 PM PDT 24 |
Peak memory | 209244 kb |
Host | smart-734bcd1e-5994-47a7-b5a2-4f2b7f395393 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3279176861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.3279176861 |
Directory | /workspace/11.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.59453300 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 314803107 ps |
CPU time | 2.37 seconds |
Started | Apr 04 02:38:49 PM PDT 24 |
Finished | Apr 04 02:38:52 PM PDT 24 |
Peak memory | 201040 kb |
Host | smart-84fba1c8-73e5-434b-8573-a988aded4968 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59453300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_ test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 10.clkmgr_shadow_reg_errors.59453300 |
Directory | /workspace/10.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/default/32.clkmgr_regwen.1416919979 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 449193127 ps |
CPU time | 3.09 seconds |
Started | Apr 04 03:48:16 PM PDT 24 |
Finished | Apr 04 03:48:19 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-e483de5d-87de-4981-8126-e789e8ad06f9 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416919979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.1416919979 |
Directory | /workspace/32.clkmgr_regwen/latest |
Test location | /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2831504318 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 467469542 ps |
CPU time | 3.41 seconds |
Started | Apr 04 02:38:49 PM PDT 24 |
Finished | Apr 04 02:38:52 PM PDT 24 |
Peak memory | 200780 kb |
Host | smart-4b440962-4584-4834-b1df-6d11652abcc6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831504318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 11.clkmgr_tl_intg_err.2831504318 |
Directory | /workspace/11.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/default/10.clkmgr_stress_all.3233041710 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 9558302777 ps |
CPU time | 66.24 seconds |
Started | Apr 04 03:46:53 PM PDT 24 |
Finished | Apr 04 03:48:00 PM PDT 24 |
Peak memory | 200996 kb |
Host | smart-57286811-8ca3-4ca4-a4e4-0c09a478d267 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233041710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.3233041710 |
Directory | /workspace/10.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/11.clkmgr_stress_all.2647035319 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 137356811 ps |
CPU time | 2.08 seconds |
Started | Apr 04 03:46:56 PM PDT 24 |
Finished | Apr 04 03:46:58 PM PDT 24 |
Peak memory | 200900 kb |
Host | smart-d623e419-9647-4631-ace8-4a0388cf8d71 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647035319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.2647035319 |
Directory | /workspace/11.clkmgr_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.604317126 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 245123010 ps |
CPU time | 1.96 seconds |
Started | Apr 04 02:39:07 PM PDT 24 |
Finished | Apr 04 02:39:09 PM PDT 24 |
Peak memory | 201152 kb |
Host | smart-cf5df2d1-8186-44bb-af76-b465a1d84dfa |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604317126 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 18.clkmgr_shadow_reg_errors.604317126 |
Directory | /workspace/18.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3570068326 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 156119166 ps |
CPU time | 3.16 seconds |
Started | Apr 04 02:38:29 PM PDT 24 |
Finished | Apr 04 02:38:32 PM PDT 24 |
Peak memory | 217508 kb |
Host | smart-7e59f171-1a22-4fa2-938f-67183d4f5ba7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570068326 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.3570068326 |
Directory | /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3105504838 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 153534780 ps |
CPU time | 1.44 seconds |
Started | Apr 04 02:39:05 PM PDT 24 |
Finished | Apr 04 02:39:06 PM PDT 24 |
Peak memory | 200944 kb |
Host | smart-f7d03506-ae91-4f7d-a708-f7982c9a8442 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105504838 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 16.clkmgr_shadow_reg_errors.3105504838 |
Directory | /workspace/16.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/default/1.clkmgr_stress_all.2964625264 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 13055526511 ps |
CPU time | 88.61 seconds |
Started | Apr 04 03:46:19 PM PDT 24 |
Finished | Apr 04 03:47:48 PM PDT 24 |
Peak memory | 201048 kb |
Host | smart-aa01dcbc-5fc4-48d4-910c-fa543799c054 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964625264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.2964625264 |
Directory | /workspace/1.clkmgr_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3970645769 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 282780467 ps |
CPU time | 3.44 seconds |
Started | Apr 04 02:38:30 PM PDT 24 |
Finished | Apr 04 02:38:34 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-6db46987-c3e4-433d-9de8-b3264adc009a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970645769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 0.clkmgr_tl_intg_err.3970645769 |
Directory | /workspace/0.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1692933455 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 469711109 ps |
CPU time | 3.9 seconds |
Started | Apr 04 02:38:54 PM PDT 24 |
Finished | Apr 04 02:38:59 PM PDT 24 |
Peak memory | 200576 kb |
Host | smart-c740c77c-1e10-428f-b764-e6845ddadf60 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692933455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 12.clkmgr_tl_intg_err.1692933455 |
Directory | /workspace/12.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2676671323 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 266059596 ps |
CPU time | 1.84 seconds |
Started | Apr 04 02:38:38 PM PDT 24 |
Finished | Apr 04 02:38:40 PM PDT 24 |
Peak memory | 200440 kb |
Host | smart-0015a4ca-b985-403e-b539-6e79137c8e7e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676671323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_aliasing.2676671323 |
Directory | /workspace/0.clkmgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3672058761 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 222406620 ps |
CPU time | 3.99 seconds |
Started | Apr 04 02:38:37 PM PDT 24 |
Finished | Apr 04 02:38:41 PM PDT 24 |
Peak memory | 200708 kb |
Host | smart-b65b2ee3-30a9-4dec-aa6f-85a69056dadf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672058761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_bit_bash.3672058761 |
Directory | /workspace/0.clkmgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.3478329751 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 35419039 ps |
CPU time | 0.84 seconds |
Started | Apr 04 02:38:33 PM PDT 24 |
Finished | Apr 04 02:38:35 PM PDT 24 |
Peak memory | 200420 kb |
Host | smart-4895c3d3-0019-4ea6-82f9-a641bdbf783a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478329751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_hw_reset.3478329751 |
Directory | /workspace/0.clkmgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.3021000381 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 61340857 ps |
CPU time | 1.18 seconds |
Started | Apr 04 02:38:31 PM PDT 24 |
Finished | Apr 04 02:38:33 PM PDT 24 |
Peak memory | 200552 kb |
Host | smart-77a4f385-46f7-40ad-b065-a83c0dab7458 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021000381 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.3021000381 |
Directory | /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.486019662 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 15391298 ps |
CPU time | 0.75 seconds |
Started | Apr 04 02:38:34 PM PDT 24 |
Finished | Apr 04 02:38:35 PM PDT 24 |
Peak memory | 200444 kb |
Host | smart-82842044-adfe-417d-980f-1e36df5385ef |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486019662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.c lkmgr_csr_rw.486019662 |
Directory | /workspace/0.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.713008561 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 27794372 ps |
CPU time | 0.67 seconds |
Started | Apr 04 02:38:40 PM PDT 24 |
Finished | Apr 04 02:38:40 PM PDT 24 |
Peak memory | 198924 kb |
Host | smart-1e95f663-48a4-49c1-b588-c0110742f614 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713008561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkm gr_intr_test.713008561 |
Directory | /workspace/0.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.2405809112 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 32162408 ps |
CPU time | 1.27 seconds |
Started | Apr 04 02:38:37 PM PDT 24 |
Finished | Apr 04 02:38:38 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-bd4581d1-7ce9-4740-968b-2bbd69f1256d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405809112 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.clkmgr_same_csr_outstanding.2405809112 |
Directory | /workspace/0.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.2429258237 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 74104509 ps |
CPU time | 1.28 seconds |
Started | Apr 04 02:38:30 PM PDT 24 |
Finished | Apr 04 02:38:32 PM PDT 24 |
Peak memory | 200884 kb |
Host | smart-de4917f5-7c68-41e0-b729-bfc059e1fdf5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429258237 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.clkmgr_shadow_reg_errors.2429258237 |
Directory | /workspace/0.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.3693169069 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 326598660 ps |
CPU time | 2.76 seconds |
Started | Apr 04 02:38:34 PM PDT 24 |
Finished | Apr 04 02:38:38 PM PDT 24 |
Peak memory | 200740 kb |
Host | smart-f98163b1-e9b9-4778-bf72-503a80f7ec58 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693169069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk mgr_tl_errors.3693169069 |
Directory | /workspace/0.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.2680915461 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 144770965 ps |
CPU time | 1.47 seconds |
Started | Apr 04 02:38:47 PM PDT 24 |
Finished | Apr 04 02:38:49 PM PDT 24 |
Peak memory | 200432 kb |
Host | smart-40ddc5c7-7981-43ee-b51c-73a9daf86b17 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680915461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_aliasing.2680915461 |
Directory | /workspace/1.clkmgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.2371263441 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 212521030 ps |
CPU time | 3.94 seconds |
Started | Apr 04 02:38:39 PM PDT 24 |
Finished | Apr 04 02:38:43 PM PDT 24 |
Peak memory | 200708 kb |
Host | smart-4250f7f6-9d91-4765-aa5c-87b49651ac60 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371263441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_bit_bash.2371263441 |
Directory | /workspace/1.clkmgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.136737385 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 26709545 ps |
CPU time | 0.78 seconds |
Started | Apr 04 02:38:42 PM PDT 24 |
Finished | Apr 04 02:38:43 PM PDT 24 |
Peak memory | 200244 kb |
Host | smart-9fb65f0b-b420-4b64-a4f3-965d78491a38 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136737385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 1.clkmgr_csr_hw_reset.136737385 |
Directory | /workspace/1.clkmgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.774665930 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 39270713 ps |
CPU time | 1.28 seconds |
Started | Apr 04 02:38:37 PM PDT 24 |
Finished | Apr 04 02:38:39 PM PDT 24 |
Peak memory | 200500 kb |
Host | smart-bf09d322-6ce4-4191-a9be-6f40e88ff57d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774665930 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.774665930 |
Directory | /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.1344833264 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 26741226 ps |
CPU time | 0.79 seconds |
Started | Apr 04 02:38:38 PM PDT 24 |
Finished | Apr 04 02:38:39 PM PDT 24 |
Peak memory | 200448 kb |
Host | smart-1cda7f26-6654-4882-9d81-cac884780252 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344833264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. clkmgr_csr_rw.1344833264 |
Directory | /workspace/1.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3129234418 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 27005972 ps |
CPU time | 0.75 seconds |
Started | Apr 04 02:38:29 PM PDT 24 |
Finished | Apr 04 02:38:30 PM PDT 24 |
Peak memory | 199032 kb |
Host | smart-0b0fd290-b3d6-421d-8dc9-49789c7f94fa |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129234418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk mgr_intr_test.3129234418 |
Directory | /workspace/1.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3395740861 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 531995457 ps |
CPU time | 2.4 seconds |
Started | Apr 04 02:38:33 PM PDT 24 |
Finished | Apr 04 02:38:36 PM PDT 24 |
Peak memory | 200688 kb |
Host | smart-805a91d7-c41b-42de-a97c-5c8a14e4403d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395740861 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.clkmgr_same_csr_outstanding.3395740861 |
Directory | /workspace/1.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.174846782 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 337316314 ps |
CPU time | 2.48 seconds |
Started | Apr 04 02:38:32 PM PDT 24 |
Finished | Apr 04 02:38:35 PM PDT 24 |
Peak memory | 201124 kb |
Host | smart-43a9b762-3b70-499c-a2a0-2b5b80ab8f3d |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174846782 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.clkmgr_shadow_reg_errors.174846782 |
Directory | /workspace/1.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.4228041427 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 214272895 ps |
CPU time | 2.6 seconds |
Started | Apr 04 02:38:38 PM PDT 24 |
Finished | Apr 04 02:38:41 PM PDT 24 |
Peak memory | 209324 kb |
Host | smart-3d815d0b-1d50-46d3-aca8-ce815cf99fc0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228041427 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.4228041427 |
Directory | /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1081371209 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 104179165 ps |
CPU time | 2.93 seconds |
Started | Apr 04 02:38:37 PM PDT 24 |
Finished | Apr 04 02:38:40 PM PDT 24 |
Peak memory | 200704 kb |
Host | smart-6d0b3fd8-b275-4bd4-9f26-21962f75d997 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081371209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk mgr_tl_errors.1081371209 |
Directory | /workspace/1.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1550856502 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 140794819 ps |
CPU time | 2.78 seconds |
Started | Apr 04 02:38:37 PM PDT 24 |
Finished | Apr 04 02:38:40 PM PDT 24 |
Peak memory | 200696 kb |
Host | smart-7b696cf2-1e01-4d2a-9ea4-9e7e3dc667d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550856502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 1.clkmgr_tl_intg_err.1550856502 |
Directory | /workspace/1.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3432130354 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 35864466 ps |
CPU time | 1.76 seconds |
Started | Apr 04 02:38:58 PM PDT 24 |
Finished | Apr 04 02:39:00 PM PDT 24 |
Peak memory | 200764 kb |
Host | smart-fc1f552f-7533-49e0-aa47-8cb2e01ee150 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432130354 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.3432130354 |
Directory | /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.2819576608 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 20503248 ps |
CPU time | 0.81 seconds |
Started | Apr 04 02:38:50 PM PDT 24 |
Finished | Apr 04 02:38:51 PM PDT 24 |
Peak memory | 200352 kb |
Host | smart-ca9dbe69-cecd-4dc1-8eca-9a16d528319e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819576608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .clkmgr_csr_rw.2819576608 |
Directory | /workspace/10.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.546243809 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 38705286 ps |
CPU time | 0.78 seconds |
Started | Apr 04 02:38:52 PM PDT 24 |
Finished | Apr 04 02:38:53 PM PDT 24 |
Peak memory | 199016 kb |
Host | smart-c55c49a1-3021-49d4-973e-4173d737e863 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546243809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clk mgr_intr_test.546243809 |
Directory | /workspace/10.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2600165586 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 323312356 ps |
CPU time | 1.79 seconds |
Started | Apr 04 02:39:00 PM PDT 24 |
Finished | Apr 04 02:39:02 PM PDT 24 |
Peak memory | 200384 kb |
Host | smart-9dd92db4-3135-44f4-91cb-8da3d13645c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600165586 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.clkmgr_same_csr_outstanding.2600165586 |
Directory | /workspace/10.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3139397676 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 250461489 ps |
CPU time | 2.14 seconds |
Started | Apr 04 02:38:50 PM PDT 24 |
Finished | Apr 04 02:38:53 PM PDT 24 |
Peak memory | 201132 kb |
Host | smart-1f584295-d8cd-445a-8471-64ee3d5245a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139397676 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.3139397676 |
Directory | /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1412743733 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 67635712 ps |
CPU time | 2.23 seconds |
Started | Apr 04 02:38:52 PM PDT 24 |
Finished | Apr 04 02:38:54 PM PDT 24 |
Peak memory | 200752 kb |
Host | smart-2d8e32d2-470c-420f-989d-ee0d2339156e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412743733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl kmgr_tl_errors.1412743733 |
Directory | /workspace/10.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2716019631 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 415218439 ps |
CPU time | 2.45 seconds |
Started | Apr 04 02:38:59 PM PDT 24 |
Finished | Apr 04 02:39:02 PM PDT 24 |
Peak memory | 200700 kb |
Host | smart-ce94fe38-a77d-4603-8d6a-9a9da12e9b77 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716019631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 10.clkmgr_tl_intg_err.2716019631 |
Directory | /workspace/10.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1446628149 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 23587574 ps |
CPU time | 1.25 seconds |
Started | Apr 04 02:38:48 PM PDT 24 |
Finished | Apr 04 02:38:49 PM PDT 24 |
Peak memory | 200548 kb |
Host | smart-389f67d6-b06a-46ab-abde-6dd02eebe00c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446628149 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.1446628149 |
Directory | /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.724405840 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 35788317 ps |
CPU time | 0.88 seconds |
Started | Apr 04 02:38:51 PM PDT 24 |
Finished | Apr 04 02:38:52 PM PDT 24 |
Peak memory | 200432 kb |
Host | smart-79a7ee29-1a2b-40f7-b38f-1d2d0c56459a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724405840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. clkmgr_csr_rw.724405840 |
Directory | /workspace/11.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.1954290277 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 20419762 ps |
CPU time | 0.67 seconds |
Started | Apr 04 02:38:54 PM PDT 24 |
Finished | Apr 04 02:38:55 PM PDT 24 |
Peak memory | 198972 kb |
Host | smart-2aee26fa-7f77-419e-9773-e67d8690af69 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954290277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl kmgr_intr_test.1954290277 |
Directory | /workspace/11.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2952100528 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 52517675 ps |
CPU time | 0.95 seconds |
Started | Apr 04 02:39:05 PM PDT 24 |
Finished | Apr 04 02:39:06 PM PDT 24 |
Peak memory | 200492 kb |
Host | smart-f65ade8f-6d28-4e13-8e06-8e4613ae356e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952100528 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.clkmgr_same_csr_outstanding.2952100528 |
Directory | /workspace/11.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2813086627 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 91916091 ps |
CPU time | 1.35 seconds |
Started | Apr 04 02:38:53 PM PDT 24 |
Finished | Apr 04 02:38:54 PM PDT 24 |
Peak memory | 200904 kb |
Host | smart-4b6a80a3-91db-4a97-8af8-6567849c66bc |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813086627 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 11.clkmgr_shadow_reg_errors.2813086627 |
Directory | /workspace/11.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.1117035707 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 78893444 ps |
CPU time | 1.88 seconds |
Started | Apr 04 02:38:53 PM PDT 24 |
Finished | Apr 04 02:38:55 PM PDT 24 |
Peak memory | 209328 kb |
Host | smart-d5960aed-6172-4409-a9e8-7ce46acb4067 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117035707 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.1117035707 |
Directory | /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1661192307 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 115370029 ps |
CPU time | 3.06 seconds |
Started | Apr 04 02:38:54 PM PDT 24 |
Finished | Apr 04 02:38:57 PM PDT 24 |
Peak memory | 200700 kb |
Host | smart-9f7b7137-10c4-414d-a9f6-33fb8ca479d4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661192307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl kmgr_tl_errors.1661192307 |
Directory | /workspace/11.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3498134189 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 44016763 ps |
CPU time | 1.57 seconds |
Started | Apr 04 02:38:52 PM PDT 24 |
Finished | Apr 04 02:38:54 PM PDT 24 |
Peak memory | 200768 kb |
Host | smart-fb2e043b-fdfd-4565-a240-935196029bcc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498134189 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.3498134189 |
Directory | /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2724578221 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 24422678 ps |
CPU time | 0.87 seconds |
Started | Apr 04 02:38:56 PM PDT 24 |
Finished | Apr 04 02:38:57 PM PDT 24 |
Peak memory | 200456 kb |
Host | smart-7feed873-93ee-4294-ba2c-73f252463beb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724578221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .clkmgr_csr_rw.2724578221 |
Directory | /workspace/12.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.2444858637 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 21866909 ps |
CPU time | 0.74 seconds |
Started | Apr 04 02:38:49 PM PDT 24 |
Finished | Apr 04 02:38:50 PM PDT 24 |
Peak memory | 198980 kb |
Host | smart-143d5d78-d734-4090-80f5-e9cb20919012 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444858637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_intr_test.2444858637 |
Directory | /workspace/12.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3509078214 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 862863540 ps |
CPU time | 3.16 seconds |
Started | Apr 04 02:38:56 PM PDT 24 |
Finished | Apr 04 02:39:00 PM PDT 24 |
Peak memory | 200684 kb |
Host | smart-fe4e1549-baad-4b53-b5de-7872adc47d90 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509078214 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 12.clkmgr_same_csr_outstanding.3509078214 |
Directory | /workspace/12.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.4121906620 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 927546611 ps |
CPU time | 3.71 seconds |
Started | Apr 04 02:38:49 PM PDT 24 |
Finished | Apr 04 02:38:53 PM PDT 24 |
Peak memory | 201172 kb |
Host | smart-9e48b6da-7d50-4417-87a4-a6247052f2f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121906620 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 12.clkmgr_shadow_reg_errors.4121906620 |
Directory | /workspace/12.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3870249091 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 254771104 ps |
CPU time | 2.25 seconds |
Started | Apr 04 02:39:03 PM PDT 24 |
Finished | Apr 04 02:39:05 PM PDT 24 |
Peak memory | 201276 kb |
Host | smart-43eaf2a6-200c-4148-9f4a-396a407b2726 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870249091 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.3870249091 |
Directory | /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3827169448 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 34076651 ps |
CPU time | 1.31 seconds |
Started | Apr 04 02:38:53 PM PDT 24 |
Finished | Apr 04 02:38:55 PM PDT 24 |
Peak memory | 200504 kb |
Host | smart-c56a2eb5-7ad7-4718-95c0-d021e949eb2a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827169448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_tl_errors.3827169448 |
Directory | /workspace/12.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1020241356 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 26059453 ps |
CPU time | 0.95 seconds |
Started | Apr 04 02:38:55 PM PDT 24 |
Finished | Apr 04 02:38:56 PM PDT 24 |
Peak memory | 200564 kb |
Host | smart-4757afe9-3ced-4e96-80e2-cc314d1ae6fb |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020241356 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.1020241356 |
Directory | /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.1269385885 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 18130458 ps |
CPU time | 0.8 seconds |
Started | Apr 04 02:38:52 PM PDT 24 |
Finished | Apr 04 02:38:53 PM PDT 24 |
Peak memory | 200444 kb |
Host | smart-5bb43148-f1a3-4cb9-b0c1-0c088ccc9c66 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269385885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .clkmgr_csr_rw.1269385885 |
Directory | /workspace/13.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.478373309 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 29254127 ps |
CPU time | 0.67 seconds |
Started | Apr 04 02:38:49 PM PDT 24 |
Finished | Apr 04 02:38:50 PM PDT 24 |
Peak memory | 199016 kb |
Host | smart-273fe517-16f7-4925-b216-eb6c88262a2e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478373309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clk mgr_intr_test.478373309 |
Directory | /workspace/13.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2765367325 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 40051321 ps |
CPU time | 1.16 seconds |
Started | Apr 04 02:38:58 PM PDT 24 |
Finished | Apr 04 02:38:59 PM PDT 24 |
Peak memory | 200444 kb |
Host | smart-46086aa6-fa5f-41fb-8a64-c09d0b1a5d9b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765367325 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.clkmgr_same_csr_outstanding.2765367325 |
Directory | /workspace/13.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1162866512 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 54824556 ps |
CPU time | 1.17 seconds |
Started | Apr 04 02:38:53 PM PDT 24 |
Finished | Apr 04 02:38:55 PM PDT 24 |
Peak memory | 200928 kb |
Host | smart-4bcafdda-b374-4b99-abbb-09a2394b1e4a |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162866512 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.clkmgr_shadow_reg_errors.1162866512 |
Directory | /workspace/13.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1291188764 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 565581546 ps |
CPU time | 4.3 seconds |
Started | Apr 04 02:38:54 PM PDT 24 |
Finished | Apr 04 02:38:59 PM PDT 24 |
Peak memory | 217444 kb |
Host | smart-2791477a-1f8b-4478-8ff0-53b590ce1dde |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291188764 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.1291188764 |
Directory | /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.2003042913 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 305240662 ps |
CPU time | 2.76 seconds |
Started | Apr 04 02:38:56 PM PDT 24 |
Finished | Apr 04 02:38:59 PM PDT 24 |
Peak memory | 200740 kb |
Host | smart-ee364fc2-a028-4c60-8532-9bd66d00b19d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003042913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl kmgr_tl_errors.2003042913 |
Directory | /workspace/13.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.2007362148 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 104022658 ps |
CPU time | 1.71 seconds |
Started | Apr 04 02:38:50 PM PDT 24 |
Finished | Apr 04 02:38:52 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-444f7772-fd57-4950-916d-5a43e178b600 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007362148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 13.clkmgr_tl_intg_err.2007362148 |
Directory | /workspace/13.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.381623222 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 113495261 ps |
CPU time | 2.04 seconds |
Started | Apr 04 02:38:57 PM PDT 24 |
Finished | Apr 04 02:38:59 PM PDT 24 |
Peak memory | 200788 kb |
Host | smart-52cf320f-862d-42f1-ad57-01d1059b20b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381623222 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.381623222 |
Directory | /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1826694072 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 17552330 ps |
CPU time | 0.8 seconds |
Started | Apr 04 02:38:53 PM PDT 24 |
Finished | Apr 04 02:38:54 PM PDT 24 |
Peak memory | 200356 kb |
Host | smart-61305774-3aee-4b5e-8989-e486e871531c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826694072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .clkmgr_csr_rw.1826694072 |
Directory | /workspace/14.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.3265581634 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 13041674 ps |
CPU time | 0.7 seconds |
Started | Apr 04 02:38:58 PM PDT 24 |
Finished | Apr 04 02:38:59 PM PDT 24 |
Peak memory | 198868 kb |
Host | smart-409a72e7-a56c-496a-9d15-29beaf98974a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265581634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl kmgr_intr_test.3265581634 |
Directory | /workspace/14.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2313852849 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 103475766 ps |
CPU time | 1.56 seconds |
Started | Apr 04 02:38:54 PM PDT 24 |
Finished | Apr 04 02:38:56 PM PDT 24 |
Peak memory | 200552 kb |
Host | smart-f0e88847-cfe0-4b09-a44f-94ba0fd35dde |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313852849 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.clkmgr_same_csr_outstanding.2313852849 |
Directory | /workspace/14.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2166213391 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 172352710 ps |
CPU time | 2.06 seconds |
Started | Apr 04 02:39:05 PM PDT 24 |
Finished | Apr 04 02:39:07 PM PDT 24 |
Peak memory | 201148 kb |
Host | smart-13f431d5-c254-4e82-8de5-a72c58d82b2d |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166213391 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 14.clkmgr_shadow_reg_errors.2166213391 |
Directory | /workspace/14.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.2622850623 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 100028635 ps |
CPU time | 2.54 seconds |
Started | Apr 04 02:38:50 PM PDT 24 |
Finished | Apr 04 02:38:53 PM PDT 24 |
Peak memory | 201420 kb |
Host | smart-e42e44b3-5b5a-4757-b2ef-7dc7a3a3d733 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622850623 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.2622850623 |
Directory | /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2724062546 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 296575180 ps |
CPU time | 3.64 seconds |
Started | Apr 04 02:38:56 PM PDT 24 |
Finished | Apr 04 02:39:00 PM PDT 24 |
Peak memory | 200744 kb |
Host | smart-92c70cd1-86a7-4794-a829-57163bb50437 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724062546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl kmgr_tl_errors.2724062546 |
Directory | /workspace/14.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.264173282 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 244844523 ps |
CPU time | 2.81 seconds |
Started | Apr 04 02:38:55 PM PDT 24 |
Finished | Apr 04 02:38:58 PM PDT 24 |
Peak memory | 200716 kb |
Host | smart-6b2e8b47-add4-4125-9b62-cc8bcf0b3320 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264173282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 14.clkmgr_tl_intg_err.264173282 |
Directory | /workspace/14.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.441911170 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 48448787 ps |
CPU time | 1.21 seconds |
Started | Apr 04 02:38:53 PM PDT 24 |
Finished | Apr 04 02:38:55 PM PDT 24 |
Peak memory | 200548 kb |
Host | smart-916a7c4d-e367-4157-b80b-55270f3caf84 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441911170 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.441911170 |
Directory | /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.933581702 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 13827969 ps |
CPU time | 0.73 seconds |
Started | Apr 04 02:38:54 PM PDT 24 |
Finished | Apr 04 02:38:54 PM PDT 24 |
Peak memory | 200404 kb |
Host | smart-96bd774e-3c5c-495e-a7cf-6b7352f2f8d2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933581702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. clkmgr_csr_rw.933581702 |
Directory | /workspace/15.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2719347698 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 76027657 ps |
CPU time | 0.77 seconds |
Started | Apr 04 02:39:02 PM PDT 24 |
Finished | Apr 04 02:39:03 PM PDT 24 |
Peak memory | 198936 kb |
Host | smart-8519e135-7fd5-4309-bb38-5036fa49727f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719347698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl kmgr_intr_test.2719347698 |
Directory | /workspace/15.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.281851486 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 30658743 ps |
CPU time | 0.93 seconds |
Started | Apr 04 02:38:51 PM PDT 24 |
Finished | Apr 04 02:38:52 PM PDT 24 |
Peak memory | 200496 kb |
Host | smart-b5c19178-8945-471d-ae7c-e1fca554f7c3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281851486 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 15.clkmgr_same_csr_outstanding.281851486 |
Directory | /workspace/15.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.985526708 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 65008835 ps |
CPU time | 1.69 seconds |
Started | Apr 04 02:38:52 PM PDT 24 |
Finished | Apr 04 02:38:54 PM PDT 24 |
Peak memory | 210376 kb |
Host | smart-c99cb353-ac38-46bd-b9f8-9b7723ce0308 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985526708 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.985526708 |
Directory | /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.1329788458 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 295634415 ps |
CPU time | 3 seconds |
Started | Apr 04 02:38:58 PM PDT 24 |
Finished | Apr 04 02:39:01 PM PDT 24 |
Peak memory | 200588 kb |
Host | smart-e01fa32d-d548-4bc3-b925-4cc25d428406 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329788458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl kmgr_tl_errors.1329788458 |
Directory | /workspace/15.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1167474484 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 180604495 ps |
CPU time | 3.06 seconds |
Started | Apr 04 02:38:54 PM PDT 24 |
Finished | Apr 04 02:38:57 PM PDT 24 |
Peak memory | 200556 kb |
Host | smart-23df5f54-448b-416e-b7fa-b8036c221e30 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167474484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 15.clkmgr_tl_intg_err.1167474484 |
Directory | /workspace/15.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.778456479 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 55317972 ps |
CPU time | 0.95 seconds |
Started | Apr 04 02:38:58 PM PDT 24 |
Finished | Apr 04 02:38:59 PM PDT 24 |
Peak memory | 200520 kb |
Host | smart-b6347dd0-6658-47ab-8d30-b14b8f7faf64 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778456479 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.778456479 |
Directory | /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.337856504 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 28156799 ps |
CPU time | 0.79 seconds |
Started | Apr 04 02:38:53 PM PDT 24 |
Finished | Apr 04 02:38:54 PM PDT 24 |
Peak memory | 200436 kb |
Host | smart-0360881e-2744-4c76-a1a1-4e160ca219a9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337856504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. clkmgr_csr_rw.337856504 |
Directory | /workspace/16.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.3560044478 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 39277510 ps |
CPU time | 0.71 seconds |
Started | Apr 04 02:38:54 PM PDT 24 |
Finished | Apr 04 02:38:55 PM PDT 24 |
Peak memory | 198820 kb |
Host | smart-02fffce6-e23f-47db-b538-18b17a85d956 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560044478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl kmgr_intr_test.3560044478 |
Directory | /workspace/16.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.730994692 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 56526345 ps |
CPU time | 1.16 seconds |
Started | Apr 04 02:38:58 PM PDT 24 |
Finished | Apr 04 02:38:59 PM PDT 24 |
Peak memory | 200492 kb |
Host | smart-d63bc3ed-d475-4c50-9091-f07926242a91 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730994692 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 16.clkmgr_same_csr_outstanding.730994692 |
Directory | /workspace/16.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.4291567578 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 117778588 ps |
CPU time | 2.73 seconds |
Started | Apr 04 02:38:54 PM PDT 24 |
Finished | Apr 04 02:38:57 PM PDT 24 |
Peak memory | 201304 kb |
Host | smart-c7864376-1db1-4f4a-9625-f44ce9bac6ab |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291567578 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.4291567578 |
Directory | /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3773662602 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 120436769 ps |
CPU time | 2.06 seconds |
Started | Apr 04 02:38:58 PM PDT 24 |
Finished | Apr 04 02:39:00 PM PDT 24 |
Peak memory | 200592 kb |
Host | smart-c6936679-ed49-4bfa-9d8b-d4334e52cf8b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773662602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl kmgr_tl_errors.3773662602 |
Directory | /workspace/16.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2930834834 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 235746608 ps |
CPU time | 2.79 seconds |
Started | Apr 04 02:38:54 PM PDT 24 |
Finished | Apr 04 02:38:58 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-42948fb2-84f1-4631-8449-fb8bcac97a96 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930834834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 16.clkmgr_tl_intg_err.2930834834 |
Directory | /workspace/16.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.595083778 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 41961666 ps |
CPU time | 0.98 seconds |
Started | Apr 04 02:38:53 PM PDT 24 |
Finished | Apr 04 02:38:54 PM PDT 24 |
Peak memory | 200464 kb |
Host | smart-c4c2ff4c-42b3-4a71-aa73-659eb63eb02b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595083778 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.595083778 |
Directory | /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.1318031174 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 15918498 ps |
CPU time | 0.78 seconds |
Started | Apr 04 02:39:05 PM PDT 24 |
Finished | Apr 04 02:39:06 PM PDT 24 |
Peak memory | 200456 kb |
Host | smart-49abbe73-9ff3-48fe-a172-d895c405d779 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318031174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .clkmgr_csr_rw.1318031174 |
Directory | /workspace/17.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.869342042 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 12717085 ps |
CPU time | 0.66 seconds |
Started | Apr 04 02:38:52 PM PDT 24 |
Finished | Apr 04 02:38:52 PM PDT 24 |
Peak memory | 198960 kb |
Host | smart-8647c764-fbf7-4c6f-88a0-0b178992fc75 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869342042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clk mgr_intr_test.869342042 |
Directory | /workspace/17.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.585980574 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 222480412 ps |
CPU time | 1.37 seconds |
Started | Apr 04 02:38:53 PM PDT 24 |
Finished | Apr 04 02:38:54 PM PDT 24 |
Peak memory | 200484 kb |
Host | smart-e9d529b6-ed10-4985-82c3-ebdb43e12a3b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585980574 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 17.clkmgr_same_csr_outstanding.585980574 |
Directory | /workspace/17.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.3018377706 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 164023619 ps |
CPU time | 2.12 seconds |
Started | Apr 04 02:38:58 PM PDT 24 |
Finished | Apr 04 02:39:00 PM PDT 24 |
Peak memory | 201288 kb |
Host | smart-827efcde-028b-43da-942d-030d7e591fa8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018377706 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.3018377706 |
Directory | /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.547613024 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 49161781 ps |
CPU time | 2.07 seconds |
Started | Apr 04 02:39:07 PM PDT 24 |
Finished | Apr 04 02:39:10 PM PDT 24 |
Peak memory | 200756 kb |
Host | smart-286c505c-5975-45f9-b6ec-ce8b69e40cd3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547613024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clk mgr_tl_errors.547613024 |
Directory | /workspace/17.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1384993639 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 210338100 ps |
CPU time | 2.58 seconds |
Started | Apr 04 02:39:05 PM PDT 24 |
Finished | Apr 04 02:39:07 PM PDT 24 |
Peak memory | 200720 kb |
Host | smart-8690eedc-ecde-4321-9d8c-9160ea5b4428 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384993639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 17.clkmgr_tl_intg_err.1384993639 |
Directory | /workspace/17.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.2881566528 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 33748308 ps |
CPU time | 1.46 seconds |
Started | Apr 04 02:38:58 PM PDT 24 |
Finished | Apr 04 02:39:00 PM PDT 24 |
Peak memory | 200780 kb |
Host | smart-d41f3a1c-ca00-4349-a1e7-8d7cc19ed0d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881566528 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.2881566528 |
Directory | /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.1618040442 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 17917261 ps |
CPU time | 0.78 seconds |
Started | Apr 04 02:39:05 PM PDT 24 |
Finished | Apr 04 02:39:06 PM PDT 24 |
Peak memory | 200452 kb |
Host | smart-2327a8f4-74c7-4815-bd3d-5f56548612ea |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618040442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .clkmgr_csr_rw.1618040442 |
Directory | /workspace/18.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.3229666466 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 37083452 ps |
CPU time | 0.76 seconds |
Started | Apr 04 02:39:03 PM PDT 24 |
Finished | Apr 04 02:39:04 PM PDT 24 |
Peak memory | 198956 kb |
Host | smart-254bf407-9dee-4668-bcf5-674ba18cc17f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229666466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl kmgr_intr_test.3229666466 |
Directory | /workspace/18.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3018149616 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 176397483 ps |
CPU time | 1.77 seconds |
Started | Apr 04 02:38:55 PM PDT 24 |
Finished | Apr 04 02:38:57 PM PDT 24 |
Peak memory | 200696 kb |
Host | smart-201e871f-1396-4034-ba34-613a98057242 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018149616 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 18.clkmgr_same_csr_outstanding.3018149616 |
Directory | /workspace/18.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.351842499 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 614640688 ps |
CPU time | 4.36 seconds |
Started | Apr 04 02:39:05 PM PDT 24 |
Finished | Apr 04 02:39:09 PM PDT 24 |
Peak memory | 209344 kb |
Host | smart-490e64e9-4f0c-403c-a17a-cc07055de2c7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351842499 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.351842499 |
Directory | /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.1036958140 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 244951274 ps |
CPU time | 3.52 seconds |
Started | Apr 04 02:39:00 PM PDT 24 |
Finished | Apr 04 02:39:04 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-e68f1d3d-f9ac-4317-ba30-653e15d1f721 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036958140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl kmgr_tl_errors.1036958140 |
Directory | /workspace/18.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3654987281 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 17847792 ps |
CPU time | 0.87 seconds |
Started | Apr 04 02:38:57 PM PDT 24 |
Finished | Apr 04 02:38:58 PM PDT 24 |
Peak memory | 200548 kb |
Host | smart-00ac4af8-e5ae-4b22-af58-705a6df32218 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654987281 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3654987281 |
Directory | /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.3493499772 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 18302501 ps |
CPU time | 0.77 seconds |
Started | Apr 04 02:38:58 PM PDT 24 |
Finished | Apr 04 02:38:59 PM PDT 24 |
Peak memory | 200412 kb |
Host | smart-1c1f6b71-8430-4f54-baf5-6d059f58d727 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493499772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .clkmgr_csr_rw.3493499772 |
Directory | /workspace/19.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2308475343 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 53767070 ps |
CPU time | 0.73 seconds |
Started | Apr 04 02:39:01 PM PDT 24 |
Finished | Apr 04 02:39:02 PM PDT 24 |
Peak memory | 199020 kb |
Host | smart-57449e41-4b12-4930-9118-5595715760f9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308475343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl kmgr_intr_test.2308475343 |
Directory | /workspace/19.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1207741958 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 31148107 ps |
CPU time | 1.02 seconds |
Started | Apr 04 02:38:56 PM PDT 24 |
Finished | Apr 04 02:38:57 PM PDT 24 |
Peak memory | 200452 kb |
Host | smart-b7804436-5df8-4bb3-af7e-ffb7c1cd278b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207741958 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.clkmgr_same_csr_outstanding.1207741958 |
Directory | /workspace/19.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2705037432 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 166430371 ps |
CPU time | 1.46 seconds |
Started | Apr 04 02:39:04 PM PDT 24 |
Finished | Apr 04 02:39:05 PM PDT 24 |
Peak memory | 200928 kb |
Host | smart-602bee77-ce5e-4991-b4e9-1c51b893dc82 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705037432 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 19.clkmgr_shadow_reg_errors.2705037432 |
Directory | /workspace/19.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2561725362 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 123269590 ps |
CPU time | 1.81 seconds |
Started | Apr 04 02:38:54 PM PDT 24 |
Finished | Apr 04 02:38:56 PM PDT 24 |
Peak memory | 217408 kb |
Host | smart-98a09b25-30d5-46b7-8cc8-417d7a50e227 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561725362 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.2561725362 |
Directory | /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1475011184 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 119760661 ps |
CPU time | 2.03 seconds |
Started | Apr 04 02:38:54 PM PDT 24 |
Finished | Apr 04 02:38:56 PM PDT 24 |
Peak memory | 200688 kb |
Host | smart-06ad5dea-46ea-402e-ab01-6e470eeafbb8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475011184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl kmgr_tl_errors.1475011184 |
Directory | /workspace/19.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.2846133075 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 220883671 ps |
CPU time | 1.8 seconds |
Started | Apr 04 02:38:53 PM PDT 24 |
Finished | Apr 04 02:38:55 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-16049a86-0faf-47cb-ab65-088cb50c1bf2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846133075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 19.clkmgr_tl_intg_err.2846133075 |
Directory | /workspace/19.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.542312840 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 197939040 ps |
CPU time | 1.99 seconds |
Started | Apr 04 02:38:49 PM PDT 24 |
Finished | Apr 04 02:38:51 PM PDT 24 |
Peak memory | 200680 kb |
Host | smart-7a336e91-4701-43bd-8ba4-2e1df4e05a99 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542312840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.clkmgr_csr_aliasing.542312840 |
Directory | /workspace/2.clkmgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2971738582 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 835648290 ps |
CPU time | 7.64 seconds |
Started | Apr 04 02:38:38 PM PDT 24 |
Finished | Apr 04 02:38:46 PM PDT 24 |
Peak memory | 200708 kb |
Host | smart-151acc0d-8bf4-44e8-8e64-bbc8e79f303e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971738582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_bit_bash.2971738582 |
Directory | /workspace/2.clkmgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.456804830 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 17174780 ps |
CPU time | 0.8 seconds |
Started | Apr 04 02:38:38 PM PDT 24 |
Finished | Apr 04 02:38:39 PM PDT 24 |
Peak memory | 200456 kb |
Host | smart-eecddc9e-08a9-40b5-9961-6b99c2ec4bd5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456804830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.clkmgr_csr_hw_reset.456804830 |
Directory | /workspace/2.clkmgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.809179143 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 47662635 ps |
CPU time | 1.56 seconds |
Started | Apr 04 02:38:37 PM PDT 24 |
Finished | Apr 04 02:38:39 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-e99d8533-cbc2-4381-86a6-464785e39549 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809179143 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.809179143 |
Directory | /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2853444713 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 20689535 ps |
CPU time | 0.74 seconds |
Started | Apr 04 02:38:36 PM PDT 24 |
Finished | Apr 04 02:38:37 PM PDT 24 |
Peak memory | 200308 kb |
Host | smart-4d1dead0-b781-4aec-b661-5347df290efb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853444713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. clkmgr_csr_rw.2853444713 |
Directory | /workspace/2.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.3202828687 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 11789448 ps |
CPU time | 0.69 seconds |
Started | Apr 04 02:38:37 PM PDT 24 |
Finished | Apr 04 02:38:38 PM PDT 24 |
Peak memory | 199008 kb |
Host | smart-313ff00d-5d97-4d53-a92f-ab86ebd5144e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202828687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk mgr_intr_test.3202828687 |
Directory | /workspace/2.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.2352066494 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 25771107 ps |
CPU time | 0.9 seconds |
Started | Apr 04 02:38:39 PM PDT 24 |
Finished | Apr 04 02:38:40 PM PDT 24 |
Peak memory | 200404 kb |
Host | smart-a086099a-c32a-44fd-a8ee-32ae1253f12e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352066494 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.clkmgr_same_csr_outstanding.2352066494 |
Directory | /workspace/2.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.4143706525 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 66191244 ps |
CPU time | 1.31 seconds |
Started | Apr 04 02:38:36 PM PDT 24 |
Finished | Apr 04 02:38:37 PM PDT 24 |
Peak memory | 200836 kb |
Host | smart-01e9dac5-ce59-4fb7-9c8a-e08777078a18 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143706525 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.clkmgr_shadow_reg_errors.4143706525 |
Directory | /workspace/2.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3106797652 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 159714974 ps |
CPU time | 1.97 seconds |
Started | Apr 04 02:38:36 PM PDT 24 |
Finished | Apr 04 02:38:39 PM PDT 24 |
Peak memory | 217476 kb |
Host | smart-a8772d2d-1f15-493e-a733-512e5ed97b49 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106797652 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.3106797652 |
Directory | /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.4084532684 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 415114244 ps |
CPU time | 3.48 seconds |
Started | Apr 04 02:38:29 PM PDT 24 |
Finished | Apr 04 02:38:33 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-4879d193-72b6-4002-9a3c-3f1ee5496665 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084532684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk mgr_tl_errors.4084532684 |
Directory | /workspace/2.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.111978908 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 145323319 ps |
CPU time | 2.1 seconds |
Started | Apr 04 02:38:30 PM PDT 24 |
Finished | Apr 04 02:38:33 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-8d548f69-5bfa-499b-a015-9718a20269f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111978908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 2.clkmgr_tl_intg_err.111978908 |
Directory | /workspace/2.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.79239577 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 19382084 ps |
CPU time | 0.66 seconds |
Started | Apr 04 02:39:02 PM PDT 24 |
Finished | Apr 04 02:39:03 PM PDT 24 |
Peak memory | 198916 kb |
Host | smart-2d30f3fc-9bb9-4d21-9a13-0aa434bba855 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79239577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ =clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clkm gr_intr_test.79239577 |
Directory | /workspace/20.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.2350900177 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 11336441 ps |
CPU time | 0.67 seconds |
Started | Apr 04 02:39:03 PM PDT 24 |
Finished | Apr 04 02:39:04 PM PDT 24 |
Peak memory | 198928 kb |
Host | smart-67da5cc4-f05c-4b44-ae93-13a6ade03bad |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350900177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl kmgr_intr_test.2350900177 |
Directory | /workspace/21.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.2022892093 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 31887814 ps |
CPU time | 0.72 seconds |
Started | Apr 04 02:39:04 PM PDT 24 |
Finished | Apr 04 02:39:05 PM PDT 24 |
Peak memory | 198968 kb |
Host | smart-5cf26dc3-3c99-431e-99e4-6207ea2324c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022892093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl kmgr_intr_test.2022892093 |
Directory | /workspace/22.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3953851305 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 11776880 ps |
CPU time | 0.68 seconds |
Started | Apr 04 02:39:03 PM PDT 24 |
Finished | Apr 04 02:39:04 PM PDT 24 |
Peak memory | 199024 kb |
Host | smart-18c7851e-0358-417e-8a5b-129a5bd5e3fa |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953851305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl kmgr_intr_test.3953851305 |
Directory | /workspace/23.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2798993580 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 12479606 ps |
CPU time | 0.68 seconds |
Started | Apr 04 02:39:02 PM PDT 24 |
Finished | Apr 04 02:39:03 PM PDT 24 |
Peak memory | 198944 kb |
Host | smart-c986a254-31d0-49d5-9732-e705e36840b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798993580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl kmgr_intr_test.2798993580 |
Directory | /workspace/24.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2285420958 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 13750660 ps |
CPU time | 0.7 seconds |
Started | Apr 04 02:39:03 PM PDT 24 |
Finished | Apr 04 02:39:04 PM PDT 24 |
Peak memory | 198968 kb |
Host | smart-0f0a1b96-8d8d-41fa-9979-4a272bef3323 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285420958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl kmgr_intr_test.2285420958 |
Directory | /workspace/25.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.499714863 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 26925173 ps |
CPU time | 0.75 seconds |
Started | Apr 04 02:39:03 PM PDT 24 |
Finished | Apr 04 02:39:04 PM PDT 24 |
Peak memory | 198932 kb |
Host | smart-b5808e4c-025f-4064-80aa-c1235a909825 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499714863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.clk mgr_intr_test.499714863 |
Directory | /workspace/26.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1448465826 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 12160052 ps |
CPU time | 0.71 seconds |
Started | Apr 04 02:39:11 PM PDT 24 |
Finished | Apr 04 02:39:12 PM PDT 24 |
Peak memory | 198988 kb |
Host | smart-f1b2174a-8aa9-4110-b79f-1b6eaad36e12 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448465826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl kmgr_intr_test.1448465826 |
Directory | /workspace/27.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.4217260882 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 12527890 ps |
CPU time | 0.65 seconds |
Started | Apr 04 02:39:01 PM PDT 24 |
Finished | Apr 04 02:39:02 PM PDT 24 |
Peak memory | 198952 kb |
Host | smart-84b9749b-fcab-45bd-b079-0e95494010bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217260882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl kmgr_intr_test.4217260882 |
Directory | /workspace/28.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2860636755 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 13387387 ps |
CPU time | 0.66 seconds |
Started | Apr 04 02:39:01 PM PDT 24 |
Finished | Apr 04 02:39:02 PM PDT 24 |
Peak memory | 198904 kb |
Host | smart-19f1e2e0-2469-46f9-a08d-8889a3f26b6b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860636755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl kmgr_intr_test.2860636755 |
Directory | /workspace/29.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3718133914 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 78866871 ps |
CPU time | 1.81 seconds |
Started | Apr 04 02:38:40 PM PDT 24 |
Finished | Apr 04 02:38:41 PM PDT 24 |
Peak memory | 200764 kb |
Host | smart-ddc26ad1-5686-4e3e-9b98-570568b50253 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718133914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_aliasing.3718133914 |
Directory | /workspace/3.clkmgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.1628476596 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 265637966 ps |
CPU time | 4.48 seconds |
Started | Apr 04 02:38:48 PM PDT 24 |
Finished | Apr 04 02:38:52 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-ceabf8b3-e198-4a0d-8448-1d22cd4890d0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628476596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_bit_bash.1628476596 |
Directory | /workspace/3.clkmgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1301915717 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 20726450 ps |
CPU time | 0.78 seconds |
Started | Apr 04 02:38:41 PM PDT 24 |
Finished | Apr 04 02:38:42 PM PDT 24 |
Peak memory | 200436 kb |
Host | smart-31303fb1-7b25-4dc0-a4fd-f103e7f41707 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301915717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_hw_reset.1301915717 |
Directory | /workspace/3.clkmgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.2981075786 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 69293977 ps |
CPU time | 1.25 seconds |
Started | Apr 04 02:38:44 PM PDT 24 |
Finished | Apr 04 02:38:46 PM PDT 24 |
Peak memory | 200404 kb |
Host | smart-25a5fc96-75b3-42fe-b15d-dddfac4720cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981075786 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.2981075786 |
Directory | /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1366392544 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 13226368 ps |
CPU time | 0.71 seconds |
Started | Apr 04 02:38:47 PM PDT 24 |
Finished | Apr 04 02:38:48 PM PDT 24 |
Peak memory | 200452 kb |
Host | smart-216d39f0-3e28-49ce-b93c-295ff93b4a97 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366392544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. clkmgr_csr_rw.1366392544 |
Directory | /workspace/3.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.3710016647 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 13543058 ps |
CPU time | 0.69 seconds |
Started | Apr 04 02:38:43 PM PDT 24 |
Finished | Apr 04 02:38:44 PM PDT 24 |
Peak memory | 199008 kb |
Host | smart-d2bbee94-cf1a-41a9-b878-ad81b221a1e9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710016647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_intr_test.3710016647 |
Directory | /workspace/3.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1131017904 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 148740113 ps |
CPU time | 1.27 seconds |
Started | Apr 04 02:38:44 PM PDT 24 |
Finished | Apr 04 02:38:45 PM PDT 24 |
Peak memory | 200360 kb |
Host | smart-51338646-8e9e-4f4a-bc8c-8a3b735a6384 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131017904 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.clkmgr_same_csr_outstanding.1131017904 |
Directory | /workspace/3.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.4165971018 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 70605477 ps |
CPU time | 1.39 seconds |
Started | Apr 04 02:38:42 PM PDT 24 |
Finished | Apr 04 02:38:43 PM PDT 24 |
Peak memory | 200924 kb |
Host | smart-cd273e3f-1964-422b-8bf2-07664945ba4c |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165971018 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.clkmgr_shadow_reg_errors.4165971018 |
Directory | /workspace/3.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1309980680 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 227922728 ps |
CPU time | 2.15 seconds |
Started | Apr 04 02:38:38 PM PDT 24 |
Finished | Apr 04 02:38:40 PM PDT 24 |
Peak memory | 201328 kb |
Host | smart-0c6359c1-3fea-4909-b727-09763c7ca2e9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309980680 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.1309980680 |
Directory | /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.3448227829 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 68672643 ps |
CPU time | 1.86 seconds |
Started | Apr 04 02:38:41 PM PDT 24 |
Finished | Apr 04 02:38:43 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-f04d318f-ec4b-4ad5-8a69-c554fe168014 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448227829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_tl_errors.3448227829 |
Directory | /workspace/3.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.801700719 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 220781780 ps |
CPU time | 2.09 seconds |
Started | Apr 04 02:38:39 PM PDT 24 |
Finished | Apr 04 02:38:41 PM PDT 24 |
Peak memory | 200564 kb |
Host | smart-4c0e236c-63b8-434c-b229-e9b49847c396 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801700719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 3.clkmgr_tl_intg_err.801700719 |
Directory | /workspace/3.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.800889240 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 37015476 ps |
CPU time | 0.7 seconds |
Started | Apr 04 02:39:00 PM PDT 24 |
Finished | Apr 04 02:39:02 PM PDT 24 |
Peak memory | 199020 kb |
Host | smart-58b05654-d68f-4c6c-8cb0-27e1ea720e32 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800889240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clk mgr_intr_test.800889240 |
Directory | /workspace/30.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.4023400175 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 101540225 ps |
CPU time | 0.83 seconds |
Started | Apr 04 02:39:01 PM PDT 24 |
Finished | Apr 04 02:39:02 PM PDT 24 |
Peak memory | 199000 kb |
Host | smart-863ed26c-2838-4fd4-a27e-44ff62df45fe |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023400175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl kmgr_intr_test.4023400175 |
Directory | /workspace/31.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.2554248884 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 23886841 ps |
CPU time | 0.68 seconds |
Started | Apr 04 02:39:03 PM PDT 24 |
Finished | Apr 04 02:39:04 PM PDT 24 |
Peak memory | 198988 kb |
Host | smart-5f73b195-4dde-47e5-8943-c37687a045a5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554248884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl kmgr_intr_test.2554248884 |
Directory | /workspace/32.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.2612172426 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 38200614 ps |
CPU time | 0.74 seconds |
Started | Apr 04 02:39:07 PM PDT 24 |
Finished | Apr 04 02:39:08 PM PDT 24 |
Peak memory | 198964 kb |
Host | smart-36bc02ce-6cbd-411d-8111-5a5437cfd5b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612172426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl kmgr_intr_test.2612172426 |
Directory | /workspace/33.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.814821264 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 36603170 ps |
CPU time | 0.76 seconds |
Started | Apr 04 02:39:09 PM PDT 24 |
Finished | Apr 04 02:39:10 PM PDT 24 |
Peak memory | 198948 kb |
Host | smart-58435e2f-f037-468c-b294-2c50ab1cd9f5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814821264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clk mgr_intr_test.814821264 |
Directory | /workspace/34.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.1461918910 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 15490687 ps |
CPU time | 0.72 seconds |
Started | Apr 04 02:39:09 PM PDT 24 |
Finished | Apr 04 02:39:10 PM PDT 24 |
Peak memory | 198964 kb |
Host | smart-3c183168-603e-4749-85ad-ffbd790539bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461918910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl kmgr_intr_test.1461918910 |
Directory | /workspace/35.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.2764299839 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 16135495 ps |
CPU time | 0.62 seconds |
Started | Apr 04 02:39:03 PM PDT 24 |
Finished | Apr 04 02:39:04 PM PDT 24 |
Peak memory | 198960 kb |
Host | smart-2dab1529-d6ab-47d0-9643-67f29abba536 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764299839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl kmgr_intr_test.2764299839 |
Directory | /workspace/36.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.1068798286 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 20754573 ps |
CPU time | 0.72 seconds |
Started | Apr 04 02:39:04 PM PDT 24 |
Finished | Apr 04 02:39:05 PM PDT 24 |
Peak memory | 198972 kb |
Host | smart-304bdf62-2ef8-48ac-8d96-ca381eb83f7d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068798286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl kmgr_intr_test.1068798286 |
Directory | /workspace/37.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.3395097546 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 92604743 ps |
CPU time | 0.87 seconds |
Started | Apr 04 02:39:07 PM PDT 24 |
Finished | Apr 04 02:39:08 PM PDT 24 |
Peak memory | 198964 kb |
Host | smart-c147f5bd-7632-4fa1-aab6-5116de5924c7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395097546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl kmgr_intr_test.3395097546 |
Directory | /workspace/38.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.2642852527 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 14316446 ps |
CPU time | 0.72 seconds |
Started | Apr 04 02:39:03 PM PDT 24 |
Finished | Apr 04 02:39:04 PM PDT 24 |
Peak memory | 198968 kb |
Host | smart-ba6e7d8b-a0df-485d-9584-c67159f30963 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642852527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl kmgr_intr_test.2642852527 |
Directory | /workspace/39.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.391061329 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 60983080 ps |
CPU time | 1.14 seconds |
Started | Apr 04 02:38:42 PM PDT 24 |
Finished | Apr 04 02:38:43 PM PDT 24 |
Peak memory | 200472 kb |
Host | smart-7c0224ec-3bef-48b8-8853-cbd0b47f1d35 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391061329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.clkmgr_csr_aliasing.391061329 |
Directory | /workspace/4.clkmgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.3999758330 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 2099807398 ps |
CPU time | 10.52 seconds |
Started | Apr 04 02:38:43 PM PDT 24 |
Finished | Apr 04 02:38:54 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-b53de3f6-ead1-441f-a55b-616b1a602496 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999758330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_bit_bash.3999758330 |
Directory | /workspace/4.clkmgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.2730746382 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 43691863 ps |
CPU time | 0.91 seconds |
Started | Apr 04 02:38:44 PM PDT 24 |
Finished | Apr 04 02:38:45 PM PDT 24 |
Peak memory | 200404 kb |
Host | smart-14488a1b-4ccb-4d4f-97df-d63596306539 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730746382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_hw_reset.2730746382 |
Directory | /workspace/4.clkmgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.2331707784 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 18476119 ps |
CPU time | 0.88 seconds |
Started | Apr 04 02:38:40 PM PDT 24 |
Finished | Apr 04 02:38:41 PM PDT 24 |
Peak memory | 200468 kb |
Host | smart-2a8e09cb-ece8-4ef2-8b13-9281fce30085 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331707784 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.2331707784 |
Directory | /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.1184750011 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 46878705 ps |
CPU time | 0.83 seconds |
Started | Apr 04 02:38:43 PM PDT 24 |
Finished | Apr 04 02:38:44 PM PDT 24 |
Peak memory | 200384 kb |
Host | smart-563c1381-280e-4932-a776-1ffcdba5baaa |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184750011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. clkmgr_csr_rw.1184750011 |
Directory | /workspace/4.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.3129369706 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 13836508 ps |
CPU time | 0.66 seconds |
Started | Apr 04 02:38:41 PM PDT 24 |
Finished | Apr 04 02:38:42 PM PDT 24 |
Peak memory | 198988 kb |
Host | smart-7ea39b2f-f9c9-4e0c-abdb-f29d99e83cdb |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129369706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_intr_test.3129369706 |
Directory | /workspace/4.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.346488579 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 326548954 ps |
CPU time | 2.04 seconds |
Started | Apr 04 02:38:49 PM PDT 24 |
Finished | Apr 04 02:38:52 PM PDT 24 |
Peak memory | 200592 kb |
Host | smart-ef1e6af7-1206-43cf-a805-b95ee94400c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346488579 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.clkmgr_same_csr_outstanding.346488579 |
Directory | /workspace/4.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.1200271509 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 113285482 ps |
CPU time | 1.46 seconds |
Started | Apr 04 02:38:39 PM PDT 24 |
Finished | Apr 04 02:38:41 PM PDT 24 |
Peak memory | 200832 kb |
Host | smart-a69008da-40c4-4e6a-aaba-3681e14814d6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200271509 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 4.clkmgr_shadow_reg_errors.1200271509 |
Directory | /workspace/4.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3405201675 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 317697097 ps |
CPU time | 2.22 seconds |
Started | Apr 04 02:38:50 PM PDT 24 |
Finished | Apr 04 02:38:52 PM PDT 24 |
Peak memory | 217416 kb |
Host | smart-a4a97385-999e-4feb-a024-9d06406dc804 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405201675 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.3405201675 |
Directory | /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1693066164 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 97446519 ps |
CPU time | 2.93 seconds |
Started | Apr 04 02:38:42 PM PDT 24 |
Finished | Apr 04 02:38:45 PM PDT 24 |
Peak memory | 200764 kb |
Host | smart-64620638-babc-46d5-a945-c3f647658aca |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693066164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_tl_errors.1693066164 |
Directory | /workspace/4.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2463198020 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 129203092 ps |
CPU time | 2.7 seconds |
Started | Apr 04 02:38:49 PM PDT 24 |
Finished | Apr 04 02:38:52 PM PDT 24 |
Peak memory | 200728 kb |
Host | smart-e8efde2d-0d2d-4940-bc4d-0d98cffacef3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463198020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 4.clkmgr_tl_intg_err.2463198020 |
Directory | /workspace/4.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.1493240861 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 33942586 ps |
CPU time | 0.67 seconds |
Started | Apr 04 02:39:01 PM PDT 24 |
Finished | Apr 04 02:39:02 PM PDT 24 |
Peak memory | 198940 kb |
Host | smart-006d0af4-0362-4aaf-b890-42d34efdbbd7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493240861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl kmgr_intr_test.1493240861 |
Directory | /workspace/40.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2389225324 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 33981855 ps |
CPU time | 0.72 seconds |
Started | Apr 04 02:39:01 PM PDT 24 |
Finished | Apr 04 02:39:02 PM PDT 24 |
Peak memory | 198928 kb |
Host | smart-f0533f5d-31d4-4636-8103-6108b31cbe3d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389225324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl kmgr_intr_test.2389225324 |
Directory | /workspace/41.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.3737192279 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 37605964 ps |
CPU time | 0.71 seconds |
Started | Apr 04 02:39:02 PM PDT 24 |
Finished | Apr 04 02:39:03 PM PDT 24 |
Peak memory | 199044 kb |
Host | smart-81839728-26c7-43e9-bd83-2644ed8a3d3f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737192279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl kmgr_intr_test.3737192279 |
Directory | /workspace/42.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.4060873975 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 10908519 ps |
CPU time | 0.66 seconds |
Started | Apr 04 02:39:02 PM PDT 24 |
Finished | Apr 04 02:39:03 PM PDT 24 |
Peak memory | 198864 kb |
Host | smart-91acffef-c312-49a8-92b7-f534f4b1f496 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060873975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl kmgr_intr_test.4060873975 |
Directory | /workspace/43.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.2004348356 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 13794746 ps |
CPU time | 0.7 seconds |
Started | Apr 04 02:39:11 PM PDT 24 |
Finished | Apr 04 02:39:12 PM PDT 24 |
Peak memory | 198988 kb |
Host | smart-f136bc5e-257f-4deb-a4d3-40b26d90dcfd |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004348356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl kmgr_intr_test.2004348356 |
Directory | /workspace/44.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.793226745 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 12767095 ps |
CPU time | 0.69 seconds |
Started | Apr 04 02:39:07 PM PDT 24 |
Finished | Apr 04 02:39:08 PM PDT 24 |
Peak memory | 198948 kb |
Host | smart-86c61efb-f316-4f40-bd1a-c10dac18b1a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793226745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.clk mgr_intr_test.793226745 |
Directory | /workspace/45.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1622668486 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 19752732 ps |
CPU time | 0.74 seconds |
Started | Apr 04 02:39:05 PM PDT 24 |
Finished | Apr 04 02:39:06 PM PDT 24 |
Peak memory | 198972 kb |
Host | smart-ad2ea141-a697-46ec-91fe-fdb8fa22e5eb |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622668486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl kmgr_intr_test.1622668486 |
Directory | /workspace/46.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3925900419 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 55958097 ps |
CPU time | 0.8 seconds |
Started | Apr 04 02:39:11 PM PDT 24 |
Finished | Apr 04 02:39:12 PM PDT 24 |
Peak memory | 198988 kb |
Host | smart-fe1778c9-0ef4-4ca2-814d-c469c5c55df5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925900419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl kmgr_intr_test.3925900419 |
Directory | /workspace/47.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2043884551 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 13875297 ps |
CPU time | 0.71 seconds |
Started | Apr 04 02:39:07 PM PDT 24 |
Finished | Apr 04 02:39:08 PM PDT 24 |
Peak memory | 198968 kb |
Host | smart-0dd8e8a4-81f3-47b1-9b29-60d9e7647efa |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043884551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl kmgr_intr_test.2043884551 |
Directory | /workspace/48.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.4113528794 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 11401855 ps |
CPU time | 0.69 seconds |
Started | Apr 04 02:39:05 PM PDT 24 |
Finished | Apr 04 02:39:06 PM PDT 24 |
Peak memory | 198968 kb |
Host | smart-f87f65c0-c2b3-4448-b8b0-936bc4dc6bb5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113528794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl kmgr_intr_test.4113528794 |
Directory | /workspace/49.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.52480100 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 27066441 ps |
CPU time | 1.03 seconds |
Started | Apr 04 02:38:42 PM PDT 24 |
Finished | Apr 04 02:38:44 PM PDT 24 |
Peak memory | 200564 kb |
Host | smart-2b4f9bd6-5e41-4938-bf96-cf1a8205087b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52480100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.52480100 |
Directory | /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2852383674 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 35601831 ps |
CPU time | 0.85 seconds |
Started | Apr 04 02:38:44 PM PDT 24 |
Finished | Apr 04 02:38:45 PM PDT 24 |
Peak memory | 200412 kb |
Host | smart-eed512af-af88-4528-a55e-97ebad4a5992 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852383674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. clkmgr_csr_rw.2852383674 |
Directory | /workspace/5.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.3364059163 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 38321734 ps |
CPU time | 0.74 seconds |
Started | Apr 04 02:38:45 PM PDT 24 |
Finished | Apr 04 02:38:46 PM PDT 24 |
Peak memory | 199016 kb |
Host | smart-8be0727d-848f-452e-beba-40ac66b769bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364059163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk mgr_intr_test.3364059163 |
Directory | /workspace/5.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.217239513 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 406161616 ps |
CPU time | 2.27 seconds |
Started | Apr 04 02:38:39 PM PDT 24 |
Finished | Apr 04 02:38:42 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-1c58d5c9-352f-4b71-af06-a3d7db8413aa |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217239513 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 5.clkmgr_same_csr_outstanding.217239513 |
Directory | /workspace/5.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.841421287 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 130104978 ps |
CPU time | 1.78 seconds |
Started | Apr 04 02:38:45 PM PDT 24 |
Finished | Apr 04 02:38:46 PM PDT 24 |
Peak memory | 201064 kb |
Host | smart-86e17b07-1b3c-4fb1-8a0e-cab51929ea62 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841421287 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 5.clkmgr_shadow_reg_errors.841421287 |
Directory | /workspace/5.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.558081753 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 99689586 ps |
CPU time | 2.48 seconds |
Started | Apr 04 02:38:50 PM PDT 24 |
Finished | Apr 04 02:38:53 PM PDT 24 |
Peak memory | 201164 kb |
Host | smart-46e6d3c9-5a2e-4776-8d74-7baaa1c8aa4b |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558081753 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.558081753 |
Directory | /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3727225166 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 37283547 ps |
CPU time | 1.41 seconds |
Started | Apr 04 02:38:41 PM PDT 24 |
Finished | Apr 04 02:38:43 PM PDT 24 |
Peak memory | 200588 kb |
Host | smart-9b042a3a-853e-47a4-89cc-405dec9f68eb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727225166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk mgr_tl_errors.3727225166 |
Directory | /workspace/5.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.890464134 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 245927934 ps |
CPU time | 2.6 seconds |
Started | Apr 04 02:38:37 PM PDT 24 |
Finished | Apr 04 02:38:40 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-78b53049-9b54-4b07-9fc7-6ae5df71f7b0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890464134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 5.clkmgr_tl_intg_err.890464134 |
Directory | /workspace/5.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.1382218384 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 208604262 ps |
CPU time | 1.52 seconds |
Started | Apr 04 02:38:45 PM PDT 24 |
Finished | Apr 04 02:38:47 PM PDT 24 |
Peak memory | 200568 kb |
Host | smart-6ea65526-6f86-4e6a-a0e6-50dbb817809f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382218384 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.1382218384 |
Directory | /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.2619426150 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 15825896 ps |
CPU time | 0.83 seconds |
Started | Apr 04 02:38:45 PM PDT 24 |
Finished | Apr 04 02:38:45 PM PDT 24 |
Peak memory | 200344 kb |
Host | smart-051ada96-3bfd-4aef-afbb-3eae90975736 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619426150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. clkmgr_csr_rw.2619426150 |
Directory | /workspace/6.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.2728537187 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 13092424 ps |
CPU time | 0.67 seconds |
Started | Apr 04 02:38:44 PM PDT 24 |
Finished | Apr 04 02:38:45 PM PDT 24 |
Peak memory | 198852 kb |
Host | smart-9f0fa2d2-a16d-4035-8a2d-422c4f3f267e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728537187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk mgr_intr_test.2728537187 |
Directory | /workspace/6.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.986212695 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 39790285 ps |
CPU time | 1.05 seconds |
Started | Apr 04 02:38:42 PM PDT 24 |
Finished | Apr 04 02:38:44 PM PDT 24 |
Peak memory | 200456 kb |
Host | smart-1c9b6272-3387-4fd6-aa1f-1c48e2ad23f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986212695 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 6.clkmgr_same_csr_outstanding.986212695 |
Directory | /workspace/6.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.3845272994 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 81393213 ps |
CPU time | 1.43 seconds |
Started | Apr 04 02:38:42 PM PDT 24 |
Finished | Apr 04 02:38:43 PM PDT 24 |
Peak memory | 200952 kb |
Host | smart-70092303-2386-4bc7-8eb1-a562041baa4d |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845272994 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 6.clkmgr_shadow_reg_errors.3845272994 |
Directory | /workspace/6.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.938755375 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 185186327 ps |
CPU time | 3.39 seconds |
Started | Apr 04 02:38:43 PM PDT 24 |
Finished | Apr 04 02:38:47 PM PDT 24 |
Peak memory | 217480 kb |
Host | smart-6448dfc2-968d-4a19-b4f0-81e53c54172a |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938755375 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.938755375 |
Directory | /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.1719981388 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 47803349 ps |
CPU time | 1.6 seconds |
Started | Apr 04 02:38:40 PM PDT 24 |
Finished | Apr 04 02:38:41 PM PDT 24 |
Peak memory | 200764 kb |
Host | smart-05aa28c2-08ab-45f7-8a34-c40735497d1f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719981388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk mgr_tl_errors.1719981388 |
Directory | /workspace/6.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1497095645 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 437106069 ps |
CPU time | 3.57 seconds |
Started | Apr 04 02:38:48 PM PDT 24 |
Finished | Apr 04 02:38:52 PM PDT 24 |
Peak memory | 200680 kb |
Host | smart-be58abb4-0c3d-44e6-b546-c138d1cc6dd6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497095645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 6.clkmgr_tl_intg_err.1497095645 |
Directory | /workspace/6.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.3809086104 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 33976093 ps |
CPU time | 1.46 seconds |
Started | Apr 04 02:38:47 PM PDT 24 |
Finished | Apr 04 02:38:49 PM PDT 24 |
Peak memory | 200716 kb |
Host | smart-5b25349a-91a6-42fc-b57c-f987d4d0f6b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809086104 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.3809086104 |
Directory | /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3201643111 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 20633230 ps |
CPU time | 0.86 seconds |
Started | Apr 04 02:38:43 PM PDT 24 |
Finished | Apr 04 02:38:44 PM PDT 24 |
Peak memory | 200436 kb |
Host | smart-6c9165d1-aa16-46d7-b123-a7ddaf548cc8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201643111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. clkmgr_csr_rw.3201643111 |
Directory | /workspace/7.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3244984270 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 11917170 ps |
CPU time | 0.69 seconds |
Started | Apr 04 02:38:53 PM PDT 24 |
Finished | Apr 04 02:38:53 PM PDT 24 |
Peak memory | 199048 kb |
Host | smart-82abd4bf-e861-49af-8bb0-7a9fe3fe7aef |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244984270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk mgr_intr_test.3244984270 |
Directory | /workspace/7.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.4021075142 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 38083391 ps |
CPU time | 1.09 seconds |
Started | Apr 04 02:38:41 PM PDT 24 |
Finished | Apr 04 02:38:42 PM PDT 24 |
Peak memory | 200492 kb |
Host | smart-172cf0b4-29a3-41e9-9233-b6efec4845cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021075142 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.clkmgr_same_csr_outstanding.4021075142 |
Directory | /workspace/7.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.1717551452 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 124604249 ps |
CPU time | 2 seconds |
Started | Apr 04 02:38:44 PM PDT 24 |
Finished | Apr 04 02:38:46 PM PDT 24 |
Peak memory | 201108 kb |
Host | smart-05f62715-13a1-4230-82bc-e5c60248a6d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717551452 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.clkmgr_shadow_reg_errors.1717551452 |
Directory | /workspace/7.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3583258675 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 89703249 ps |
CPU time | 2.26 seconds |
Started | Apr 04 02:38:47 PM PDT 24 |
Finished | Apr 04 02:38:50 PM PDT 24 |
Peak memory | 217432 kb |
Host | smart-4094e95b-254c-4f05-94a2-851328527c37 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583258675 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.3583258675 |
Directory | /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.2001508273 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 81249298 ps |
CPU time | 1.98 seconds |
Started | Apr 04 02:38:50 PM PDT 24 |
Finished | Apr 04 02:38:52 PM PDT 24 |
Peak memory | 200788 kb |
Host | smart-968ac712-9a4d-42e8-9dd2-30aaea9d5e72 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001508273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk mgr_tl_errors.2001508273 |
Directory | /workspace/7.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.4195065642 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 70831308 ps |
CPU time | 1.75 seconds |
Started | Apr 04 02:38:41 PM PDT 24 |
Finished | Apr 04 02:38:43 PM PDT 24 |
Peak memory | 200568 kb |
Host | smart-51d67248-4cab-4d3d-a6da-eccb96d66693 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195065642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 7.clkmgr_tl_intg_err.4195065642 |
Directory | /workspace/7.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1594216353 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 94928559 ps |
CPU time | 1.17 seconds |
Started | Apr 04 02:38:48 PM PDT 24 |
Finished | Apr 04 02:38:49 PM PDT 24 |
Peak memory | 200484 kb |
Host | smart-b883a422-5bd4-4623-a6aa-25059c37ba4e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594216353 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.1594216353 |
Directory | /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3951653678 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 51650395 ps |
CPU time | 0.93 seconds |
Started | Apr 04 02:38:41 PM PDT 24 |
Finished | Apr 04 02:38:42 PM PDT 24 |
Peak memory | 200444 kb |
Host | smart-81e56970-6fc3-401d-bcf9-e8de6135b4b7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951653678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. clkmgr_csr_rw.3951653678 |
Directory | /workspace/8.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.2792415389 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 13865231 ps |
CPU time | 0.7 seconds |
Started | Apr 04 02:38:38 PM PDT 24 |
Finished | Apr 04 02:38:39 PM PDT 24 |
Peak memory | 199016 kb |
Host | smart-ac5b3743-d7f9-4070-b989-9c409c24d50d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792415389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk mgr_intr_test.2792415389 |
Directory | /workspace/8.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3804759099 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 29578904 ps |
CPU time | 1.03 seconds |
Started | Apr 04 02:38:40 PM PDT 24 |
Finished | Apr 04 02:38:41 PM PDT 24 |
Peak memory | 200460 kb |
Host | smart-22c96960-8533-4fce-b5f1-a55992fa67d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804759099 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.clkmgr_same_csr_outstanding.3804759099 |
Directory | /workspace/8.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.4055116399 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 271400665 ps |
CPU time | 2.41 seconds |
Started | Apr 04 02:38:52 PM PDT 24 |
Finished | Apr 04 02:38:55 PM PDT 24 |
Peak memory | 201064 kb |
Host | smart-e19628d7-7a62-4187-970f-e766ab5bfe3a |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055116399 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 8.clkmgr_shadow_reg_errors.4055116399 |
Directory | /workspace/8.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3765619407 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 411367412 ps |
CPU time | 3.48 seconds |
Started | Apr 04 02:38:42 PM PDT 24 |
Finished | Apr 04 02:38:45 PM PDT 24 |
Peak memory | 209360 kb |
Host | smart-b0c194e1-c0a7-4e1b-9b9c-521e70838974 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765619407 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.3765619407 |
Directory | /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.3952627056 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 75558407 ps |
CPU time | 2.59 seconds |
Started | Apr 04 02:38:40 PM PDT 24 |
Finished | Apr 04 02:38:43 PM PDT 24 |
Peak memory | 200720 kb |
Host | smart-2add8d6a-ea12-4916-8126-b8c21972f931 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952627056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk mgr_tl_errors.3952627056 |
Directory | /workspace/8.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.918609156 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 126313224 ps |
CPU time | 2.42 seconds |
Started | Apr 04 02:38:51 PM PDT 24 |
Finished | Apr 04 02:38:53 PM PDT 24 |
Peak memory | 200684 kb |
Host | smart-2f81f59e-35c6-4f9e-ba28-72cb8ee25fec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918609156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.clkmgr_tl_intg_err.918609156 |
Directory | /workspace/8.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.569204867 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 355148329 ps |
CPU time | 2.23 seconds |
Started | Apr 04 02:38:50 PM PDT 24 |
Finished | Apr 04 02:38:53 PM PDT 24 |
Peak memory | 200700 kb |
Host | smart-16e482b3-d182-40c4-9f58-46f353d3bc3d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569204867 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.569204867 |
Directory | /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3512062194 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 21915366 ps |
CPU time | 0.81 seconds |
Started | Apr 04 02:38:48 PM PDT 24 |
Finished | Apr 04 02:38:49 PM PDT 24 |
Peak memory | 200452 kb |
Host | smart-2effbda2-8d41-49b1-b9de-875c19f8860c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512062194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. clkmgr_csr_rw.3512062194 |
Directory | /workspace/9.clkmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1599053515 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 17597333 ps |
CPU time | 0.7 seconds |
Started | Apr 04 02:38:42 PM PDT 24 |
Finished | Apr 04 02:38:44 PM PDT 24 |
Peak memory | 198808 kb |
Host | smart-111c8004-53eb-4147-b126-b70a04d842dd |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599053515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk mgr_intr_test.1599053515 |
Directory | /workspace/9.clkmgr_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.64035708 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 170167964 ps |
CPU time | 1.65 seconds |
Started | Apr 04 02:38:40 PM PDT 24 |
Finished | Apr 04 02:38:42 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-30640ec1-b309-4c58-929f-c6c3a177df17 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64035708 -assert nopostproc +UVM_TESTNAME=clkmgr_ba se_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.clkmgr_same_csr_outstanding.64035708 |
Directory | /workspace/9.clkmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3340444504 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 405067455 ps |
CPU time | 3.03 seconds |
Started | Apr 04 02:38:41 PM PDT 24 |
Finished | Apr 04 02:38:44 PM PDT 24 |
Peak memory | 201156 kb |
Host | smart-177062f9-cfc9-40eb-b560-8c0b03fda760 |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340444504 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.clkmgr_shadow_reg_errors.3340444504 |
Directory | /workspace/9.clkmgr_shadow_reg_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.4211642658 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 181790048 ps |
CPU time | 3.01 seconds |
Started | Apr 04 02:38:51 PM PDT 24 |
Finished | Apr 04 02:38:54 PM PDT 24 |
Peak memory | 201208 kb |
Host | smart-edf29fdb-f1c9-4faf-88a3-80a886e078ff |
User | root |
Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211642658 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.4211642658 |
Directory | /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.429393169 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 526459372 ps |
CPU time | 3.66 seconds |
Started | Apr 04 02:38:44 PM PDT 24 |
Finished | Apr 04 02:38:48 PM PDT 24 |
Peak memory | 200720 kb |
Host | smart-be93ac27-d124-4813-9b30-4a1436e46c71 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429393169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkm gr_tl_errors.429393169 |
Directory | /workspace/9.clkmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.1546013836 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 99356608 ps |
CPU time | 2.42 seconds |
Started | Apr 04 02:38:47 PM PDT 24 |
Finished | Apr 04 02:38:50 PM PDT 24 |
Peak memory | 200688 kb |
Host | smart-47d48738-4943-46d0-8001-13c890d4d530 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546013836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 9.clkmgr_tl_intg_err.1546013836 |
Directory | /workspace/9.clkmgr_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.clkmgr_alert_test.3315939247 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 12488810 ps |
CPU time | 0.68 seconds |
Started | Apr 04 03:46:07 PM PDT 24 |
Finished | Apr 04 03:46:08 PM PDT 24 |
Peak memory | 200428 kb |
Host | smart-421d8e99-66f7-4015-a20f-8b04af8dd157 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315939247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm gr_alert_test.3315939247 |
Directory | /workspace/0.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.3316470817 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 31304924 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:46:13 PM PDT 24 |
Finished | Apr 04 03:46:14 PM PDT 24 |
Peak memory | 200596 kb |
Host | smart-626be4b6-ec64-4326-8dee-da03bbd40204 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316470817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.3316470817 |
Directory | /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/0.clkmgr_clk_status.4068232871 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 73168630 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:46:14 PM PDT 24 |
Finished | Apr 04 03:46:16 PM PDT 24 |
Peak memory | 200400 kb |
Host | smart-61968ab7-558c-453c-b2a6-461e1eb10e61 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068232871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.4068232871 |
Directory | /workspace/0.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/0.clkmgr_div_intersig_mubi.2820738994 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 76692450 ps |
CPU time | 1 seconds |
Started | Apr 04 03:46:13 PM PDT 24 |
Finished | Apr 04 03:46:14 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-b686dba9-6590-465d-8aeb-8c787f62777e |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820738994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.2820738994 |
Directory | /workspace/0.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/0.clkmgr_extclk.1798834785 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 74411731 ps |
CPU time | 1.02 seconds |
Started | Apr 04 03:46:14 PM PDT 24 |
Finished | Apr 04 03:46:15 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-62b7225e-e533-43f4-9688-8094c7e208eb |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798834785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.1798834785 |
Directory | /workspace/0.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/0.clkmgr_frequency.2134877265 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 1159440265 ps |
CPU time | 8.76 seconds |
Started | Apr 04 03:46:16 PM PDT 24 |
Finished | Apr 04 03:46:25 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-0af4134c-0ec6-4eb2-a983-6ae455322145 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134877265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.2134877265 |
Directory | /workspace/0.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/0.clkmgr_frequency_timeout.1541228831 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 1936276515 ps |
CPU time | 13.36 seconds |
Started | Apr 04 03:46:12 PM PDT 24 |
Finished | Apr 04 03:46:26 PM PDT 24 |
Peak memory | 200700 kb |
Host | smart-928e9021-dc1b-414f-bbd8-908c274f477a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541228831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti meout.1541228831 |
Directory | /workspace/0.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.2127351348 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 25080021 ps |
CPU time | 0.91 seconds |
Started | Apr 04 03:46:15 PM PDT 24 |
Finished | Apr 04 03:46:16 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-3bf4b4fc-bcfd-49da-b0e5-891004f6e416 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127351348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.2127351348 |
Directory | /workspace/0.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.3171755919 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 33416329 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:46:12 PM PDT 24 |
Finished | Apr 04 03:46:13 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-61507492-2848-4fb7-99ff-72bf78015618 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171755919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.clkmgr_lc_clk_byp_req_intersig_mubi.3171755919 |
Directory | /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.3957823451 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 15219739 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:46:19 PM PDT 24 |
Finished | Apr 04 03:46:20 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-5d98684b-d26d-4763-9baf-7800229c35c4 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957823451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.clkmgr_lc_ctrl_intersig_mubi.3957823451 |
Directory | /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/0.clkmgr_peri.2967412314 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 48924042 ps |
CPU time | 0.91 seconds |
Started | Apr 04 03:46:15 PM PDT 24 |
Finished | Apr 04 03:46:16 PM PDT 24 |
Peak memory | 200404 kb |
Host | smart-c05cfc09-e56e-4f1e-a732-fcdfb6a03800 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967412314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.2967412314 |
Directory | /workspace/0.clkmgr_peri/latest |
Test location | /workspace/coverage/default/0.clkmgr_regwen.1365079104 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 808956086 ps |
CPU time | 4.68 seconds |
Started | Apr 04 03:46:11 PM PDT 24 |
Finished | Apr 04 03:46:16 PM PDT 24 |
Peak memory | 200792 kb |
Host | smart-90e695af-f610-418d-9e91-2a32a088ba73 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365079104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.1365079104 |
Directory | /workspace/0.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/0.clkmgr_sec_cm.216431996 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 589437661 ps |
CPU time | 3.63 seconds |
Started | Apr 04 03:46:17 PM PDT 24 |
Finished | Apr 04 03:46:21 PM PDT 24 |
Peak memory | 217388 kb |
Host | smart-98804402-3a30-4f7a-bbf2-417dccf108f9 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216431996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr _sec_cm.216431996 |
Directory | /workspace/0.clkmgr_sec_cm/latest |
Test location | /workspace/coverage/default/0.clkmgr_smoke.1390530305 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 17463631 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:46:12 PM PDT 24 |
Finished | Apr 04 03:46:13 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-332700bf-89c9-40f1-bad8-0922f8fe97d3 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390530305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.1390530305 |
Directory | /workspace/0.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/0.clkmgr_stress_all.2805719134 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 2072022129 ps |
CPU time | 11.91 seconds |
Started | Apr 04 03:46:13 PM PDT 24 |
Finished | Apr 04 03:46:25 PM PDT 24 |
Peak memory | 200876 kb |
Host | smart-deab30ed-bb07-4a27-952e-7f6257a84268 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805719134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.2805719134 |
Directory | /workspace/0.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.2948349336 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 69977403265 ps |
CPU time | 407.85 seconds |
Started | Apr 04 03:46:15 PM PDT 24 |
Finished | Apr 04 03:53:03 PM PDT 24 |
Peak memory | 209324 kb |
Host | smart-d5d8aca3-17e8-4d75-bdea-0c97f2072dd2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2948349336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.2948349336 |
Directory | /workspace/0.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.clkmgr_trans.4050102118 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 96172151 ps |
CPU time | 1.1 seconds |
Started | Apr 04 03:46:11 PM PDT 24 |
Finished | Apr 04 03:46:12 PM PDT 24 |
Peak memory | 200572 kb |
Host | smart-47a608fb-b3cd-47bf-bd72-c3668a63c4ca |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050102118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.4050102118 |
Directory | /workspace/0.clkmgr_trans/latest |
Test location | /workspace/coverage/default/1.clkmgr_alert_test.1811718532 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 13768599 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:46:14 PM PDT 24 |
Finished | Apr 04 03:46:15 PM PDT 24 |
Peak memory | 200484 kb |
Host | smart-d1b4133d-4003-4335-bb56-33e7e8b4f4b9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811718532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm gr_alert_test.1811718532 |
Directory | /workspace/1.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.2124869364 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 24150222 ps |
CPU time | 0.92 seconds |
Started | Apr 04 03:46:13 PM PDT 24 |
Finished | Apr 04 03:46:14 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-3f5b9cae-d86e-4426-8112-cce2c0c20e18 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124869364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.2124869364 |
Directory | /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/1.clkmgr_clk_status.4221740884 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 14213973 ps |
CPU time | 0.7 seconds |
Started | Apr 04 03:46:14 PM PDT 24 |
Finished | Apr 04 03:46:14 PM PDT 24 |
Peak memory | 200352 kb |
Host | smart-a3e8e676-580c-4fd8-b9d5-5392d29d8d89 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221740884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.4221740884 |
Directory | /workspace/1.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/1.clkmgr_div_intersig_mubi.527962212 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 99291074 ps |
CPU time | 1.13 seconds |
Started | Apr 04 03:46:15 PM PDT 24 |
Finished | Apr 04 03:46:17 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-e7d361aa-88d9-4355-87cd-82fc9202746f |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527962212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .clkmgr_div_intersig_mubi.527962212 |
Directory | /workspace/1.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/1.clkmgr_extclk.3922662184 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 34259266 ps |
CPU time | 0.96 seconds |
Started | Apr 04 03:46:15 PM PDT 24 |
Finished | Apr 04 03:46:16 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-902d1c95-97b6-40a6-89c2-a71d88ee6ed7 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922662184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.3922662184 |
Directory | /workspace/1.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/1.clkmgr_frequency.4291476216 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 928005489 ps |
CPU time | 4.46 seconds |
Started | Apr 04 03:46:11 PM PDT 24 |
Finished | Apr 04 03:46:15 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-d7298438-6474-4f5c-a7da-a986ba697809 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291476216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.4291476216 |
Directory | /workspace/1.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/1.clkmgr_frequency_timeout.3311901224 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 501085943 ps |
CPU time | 4.12 seconds |
Started | Apr 04 03:46:13 PM PDT 24 |
Finished | Apr 04 03:46:17 PM PDT 24 |
Peak memory | 200712 kb |
Host | smart-0dd5c792-71be-452a-8270-0fd5ba48d5d6 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311901224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti meout.3311901224 |
Directory | /workspace/1.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.1635709867 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 113332133 ps |
CPU time | 1.24 seconds |
Started | Apr 04 03:46:11 PM PDT 24 |
Finished | Apr 04 03:46:13 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-0aa62c73-c0e0-491c-a63b-5eb48bf14eb6 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635709867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.1635709867 |
Directory | /workspace/1.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.3099778126 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 18488677 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:46:14 PM PDT 24 |
Finished | Apr 04 03:46:15 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-6a06288e-0740-4021-b848-363fdda17bce |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099778126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_clk_byp_req_intersig_mubi.3099778126 |
Directory | /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.3216564544 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 28121418 ps |
CPU time | 0.91 seconds |
Started | Apr 04 03:46:19 PM PDT 24 |
Finished | Apr 04 03:46:20 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-5c8605e6-e444-4618-9698-2436bfb5a774 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216564544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_ctrl_intersig_mubi.3216564544 |
Directory | /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/1.clkmgr_peri.2847074367 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 16058482 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:46:14 PM PDT 24 |
Finished | Apr 04 03:46:15 PM PDT 24 |
Peak memory | 200360 kb |
Host | smart-0802a709-fabe-4359-8cf8-3ebd2a6e02f9 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847074367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.2847074367 |
Directory | /workspace/1.clkmgr_peri/latest |
Test location | /workspace/coverage/default/1.clkmgr_regwen.1806148490 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 1243025158 ps |
CPU time | 5.54 seconds |
Started | Apr 04 03:46:15 PM PDT 24 |
Finished | Apr 04 03:46:21 PM PDT 24 |
Peak memory | 200740 kb |
Host | smart-272f2ef0-dbb1-48f8-8882-85ee3110bd42 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806148490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.1806148490 |
Directory | /workspace/1.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/1.clkmgr_sec_cm.3421294272 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 608654550 ps |
CPU time | 3.73 seconds |
Started | Apr 04 03:46:15 PM PDT 24 |
Finished | Apr 04 03:46:19 PM PDT 24 |
Peak memory | 217376 kb |
Host | smart-8713caad-dde6-4b0c-a401-16049e8fb632 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421294272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg r_sec_cm.3421294272 |
Directory | /workspace/1.clkmgr_sec_cm/latest |
Test location | /workspace/coverage/default/1.clkmgr_smoke.1323983467 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 28266765 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:46:13 PM PDT 24 |
Finished | Apr 04 03:46:14 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-4b90ad89-6528-4cbb-a2ae-426feafb9c7c |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323983467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.1323983467 |
Directory | /workspace/1.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.4112502626 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 121879839275 ps |
CPU time | 737.41 seconds |
Started | Apr 04 03:46:16 PM PDT 24 |
Finished | Apr 04 03:58:34 PM PDT 24 |
Peak memory | 212700 kb |
Host | smart-cb18083e-e702-48eb-83ff-27927af386a9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4112502626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.4112502626 |
Directory | /workspace/1.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.clkmgr_trans.2693380299 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 53618390 ps |
CPU time | 1 seconds |
Started | Apr 04 03:46:14 PM PDT 24 |
Finished | Apr 04 03:46:15 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-f108d01b-d895-49c7-af8a-bf353ebe45a1 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693380299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.2693380299 |
Directory | /workspace/1.clkmgr_trans/latest |
Test location | /workspace/coverage/default/10.clkmgr_alert_test.703654403 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 21659149 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:46:54 PM PDT 24 |
Finished | Apr 04 03:46:55 PM PDT 24 |
Peak memory | 200532 kb |
Host | smart-54412503-45c5-4ae6-9abc-69b71c996b62 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703654403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkm gr_alert_test.703654403 |
Directory | /workspace/10.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1953087703 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 29735170 ps |
CPU time | 0.95 seconds |
Started | Apr 04 03:46:54 PM PDT 24 |
Finished | Apr 04 03:46:55 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-4eac5b2e-5148-4467-b5b2-82ce559ab71d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953087703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.1953087703 |
Directory | /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/10.clkmgr_clk_status.3843198492 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 44693826 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:46:53 PM PDT 24 |
Finished | Apr 04 03:46:54 PM PDT 24 |
Peak memory | 199516 kb |
Host | smart-fd69fb2a-fc1f-4c77-8398-fc90c951543a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843198492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.3843198492 |
Directory | /workspace/10.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/10.clkmgr_div_intersig_mubi.1481563720 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 86109489 ps |
CPU time | 0.98 seconds |
Started | Apr 04 03:46:52 PM PDT 24 |
Finished | Apr 04 03:46:53 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-e23ed42c-0e35-44d9-a728-1eae5031ae77 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481563720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_div_intersig_mubi.1481563720 |
Directory | /workspace/10.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/10.clkmgr_extclk.3117372252 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 48427758 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:46:58 PM PDT 24 |
Finished | Apr 04 03:46:58 PM PDT 24 |
Peak memory | 200612 kb |
Host | smart-12732266-f2f5-4aff-a0b6-2ce8fd3713cf |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117372252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.3117372252 |
Directory | /workspace/10.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/10.clkmgr_frequency.2957564048 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 2398507553 ps |
CPU time | 10.74 seconds |
Started | Apr 04 03:46:56 PM PDT 24 |
Finished | Apr 04 03:47:07 PM PDT 24 |
Peak memory | 200924 kb |
Host | smart-d02ef2f4-8be0-4775-94ef-36a8b6c6b2b8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957564048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.2957564048 |
Directory | /workspace/10.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/10.clkmgr_frequency_timeout.2795176261 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 499335058 ps |
CPU time | 4.02 seconds |
Started | Apr 04 03:46:52 PM PDT 24 |
Finished | Apr 04 03:46:56 PM PDT 24 |
Peak memory | 200712 kb |
Host | smart-eafb924b-a3cb-448a-92fd-d844af381d90 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795176261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t imeout.2795176261 |
Directory | /workspace/10.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.2655567087 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 63930450 ps |
CPU time | 1.13 seconds |
Started | Apr 04 03:46:53 PM PDT 24 |
Finished | Apr 04 03:46:54 PM PDT 24 |
Peak memory | 200580 kb |
Host | smart-bdad02c3-dd17-47b1-84a1-2f963ffcd5b9 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655567087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.2655567087 |
Directory | /workspace/10.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.2487875225 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 24732815 ps |
CPU time | 0.88 seconds |
Started | Apr 04 03:46:56 PM PDT 24 |
Finished | Apr 04 03:46:57 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-0d2a3712-162b-40ce-a89e-40c333e5145c |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487875225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_clk_byp_req_intersig_mubi.2487875225 |
Directory | /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.2065140344 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 347744288 ps |
CPU time | 1.81 seconds |
Started | Apr 04 03:46:54 PM PDT 24 |
Finished | Apr 04 03:46:56 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-1f1f2a02-882a-4c8a-b35b-0b771ae54af9 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065140344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_ctrl_intersig_mubi.2065140344 |
Directory | /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/10.clkmgr_peri.1921369714 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 14442667 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:46:55 PM PDT 24 |
Finished | Apr 04 03:46:55 PM PDT 24 |
Peak memory | 200312 kb |
Host | smart-dbe41bc7-337f-4afa-96c8-5bba1dc831da |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921369714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.1921369714 |
Directory | /workspace/10.clkmgr_peri/latest |
Test location | /workspace/coverage/default/10.clkmgr_regwen.2511554741 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 348472023 ps |
CPU time | 1.95 seconds |
Started | Apr 04 03:46:57 PM PDT 24 |
Finished | Apr 04 03:46:59 PM PDT 24 |
Peak memory | 200596 kb |
Host | smart-f90b7486-fa48-4ea8-a63b-74dffad323c7 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511554741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.2511554741 |
Directory | /workspace/10.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/10.clkmgr_smoke.2297532108 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 237470776 ps |
CPU time | 1.46 seconds |
Started | Apr 04 03:46:58 PM PDT 24 |
Finished | Apr 04 03:46:59 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-5b542e4f-185f-4948-a215-cbeb709118c9 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297532108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.2297532108 |
Directory | /workspace/10.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.1755948925 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 23371363840 ps |
CPU time | 338.42 seconds |
Started | Apr 04 03:46:53 PM PDT 24 |
Finished | Apr 04 03:52:31 PM PDT 24 |
Peak memory | 216536 kb |
Host | smart-f5f58517-39fc-4aa9-93f5-507b1e0ad7c8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1755948925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.1755948925 |
Directory | /workspace/10.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.clkmgr_trans.2490813350 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 33998681 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:46:50 PM PDT 24 |
Finished | Apr 04 03:46:51 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-a5d5e0bc-59f3-43de-ad59-e9c7adba6426 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490813350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2490813350 |
Directory | /workspace/10.clkmgr_trans/latest |
Test location | /workspace/coverage/default/11.clkmgr_alert_test.2313237384 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 25665981 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:46:55 PM PDT 24 |
Finished | Apr 04 03:46:55 PM PDT 24 |
Peak memory | 200376 kb |
Host | smart-aaf7d16a-0f50-4a9f-b23f-9d089f667774 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313237384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk mgr_alert_test.2313237384 |
Directory | /workspace/11.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.786594289 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 17161968 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:46:53 PM PDT 24 |
Finished | Apr 04 03:46:54 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-6a7fde83-41e5-40be-8d79-40cd8172674d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786594289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.786594289 |
Directory | /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/11.clkmgr_clk_status.3020006305 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 12071803 ps |
CPU time | 0.69 seconds |
Started | Apr 04 03:46:56 PM PDT 24 |
Finished | Apr 04 03:46:57 PM PDT 24 |
Peak memory | 199592 kb |
Host | smart-af21b629-6226-4238-b70b-00ecf31672ca |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020006305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.3020006305 |
Directory | /workspace/11.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/11.clkmgr_div_intersig_mubi.3613295610 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 17276636 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:46:56 PM PDT 24 |
Finished | Apr 04 03:46:57 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-0eb51940-93fc-4600-9018-c23373a5e8a5 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613295610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.3613295610 |
Directory | /workspace/11.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/11.clkmgr_extclk.2052096321 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 47437010 ps |
CPU time | 0.98 seconds |
Started | Apr 04 03:46:53 PM PDT 24 |
Finished | Apr 04 03:46:54 PM PDT 24 |
Peak memory | 200700 kb |
Host | smart-f720c564-fa86-4638-a7d1-e851ef9a3653 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052096321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.2052096321 |
Directory | /workspace/11.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/11.clkmgr_frequency.1170717795 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 1761798758 ps |
CPU time | 13.84 seconds |
Started | Apr 04 03:46:57 PM PDT 24 |
Finished | Apr 04 03:47:11 PM PDT 24 |
Peak memory | 200764 kb |
Host | smart-f50e819c-b65c-46a2-a1e5-b463391db6b9 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170717795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.1170717795 |
Directory | /workspace/11.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/11.clkmgr_frequency_timeout.3212384414 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 1223681542 ps |
CPU time | 6.68 seconds |
Started | Apr 04 03:46:57 PM PDT 24 |
Finished | Apr 04 03:47:03 PM PDT 24 |
Peak memory | 200700 kb |
Host | smart-d9f531e7-b03c-4e6a-8ceb-4a7f987b8838 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212384414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t imeout.3212384414 |
Directory | /workspace/11.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.843008787 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 28095784 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:46:53 PM PDT 24 |
Finished | Apr 04 03:46:54 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-b9dd81a2-6349-4ef1-8a9a-d13d326659d3 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843008787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.clkmgr_idle_intersig_mubi.843008787 |
Directory | /workspace/11.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1782659854 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 30985851 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:46:55 PM PDT 24 |
Finished | Apr 04 03:46:56 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-300d96fc-a6e2-4262-9c83-e8d85b67c05f |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782659854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 11.clkmgr_lc_clk_byp_req_intersig_mubi.1782659854 |
Directory | /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.255421598 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 16106807 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:46:51 PM PDT 24 |
Finished | Apr 04 03:46:52 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-ca94eb3f-4e2b-4757-9aab-9c9edc9c4c00 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255421598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.clkmgr_lc_ctrl_intersig_mubi.255421598 |
Directory | /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/11.clkmgr_peri.2565936183 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 20610456 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:46:52 PM PDT 24 |
Finished | Apr 04 03:46:53 PM PDT 24 |
Peak memory | 200380 kb |
Host | smart-4a46f30a-8bad-4197-88fb-b1ee17d14a10 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565936183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.2565936183 |
Directory | /workspace/11.clkmgr_peri/latest |
Test location | /workspace/coverage/default/11.clkmgr_regwen.1703420867 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 723627679 ps |
CPU time | 3.16 seconds |
Started | Apr 04 03:46:51 PM PDT 24 |
Finished | Apr 04 03:46:55 PM PDT 24 |
Peak memory | 200788 kb |
Host | smart-dc7ea001-a818-4a8e-ade6-8fb76515f26e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703420867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.1703420867 |
Directory | /workspace/11.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/11.clkmgr_smoke.1327071167 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 16422967 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:46:52 PM PDT 24 |
Finished | Apr 04 03:46:53 PM PDT 24 |
Peak memory | 200688 kb |
Host | smart-de6f4f3a-8d6a-45e9-8408-68f7923ce875 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327071167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.1327071167 |
Directory | /workspace/11.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/11.clkmgr_trans.1159794404 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 72715501 ps |
CPU time | 1 seconds |
Started | Apr 04 03:46:56 PM PDT 24 |
Finished | Apr 04 03:46:57 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-cc20335d-bcdb-4a53-8f02-56a525facb3d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159794404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.1159794404 |
Directory | /workspace/11.clkmgr_trans/latest |
Test location | /workspace/coverage/default/12.clkmgr_alert_test.171038575 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 43766920 ps |
CPU time | 0.91 seconds |
Started | Apr 04 03:46:54 PM PDT 24 |
Finished | Apr 04 03:46:55 PM PDT 24 |
Peak memory | 200496 kb |
Host | smart-5118a692-f8e8-4bbc-b9ee-c130acd5b3b3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171038575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkm gr_alert_test.171038575 |
Directory | /workspace/12.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.639108300 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 55776298 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:46:56 PM PDT 24 |
Finished | Apr 04 03:46:57 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-fa2b2462-5b4b-4308-9bcb-50ae180f0fa9 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639108300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.639108300 |
Directory | /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/12.clkmgr_clk_status.308320094 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 16475381 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:46:56 PM PDT 24 |
Finished | Apr 04 03:46:57 PM PDT 24 |
Peak memory | 200332 kb |
Host | smart-b430a9a1-f74d-48fa-b902-65a10c05ff7a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308320094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.308320094 |
Directory | /workspace/12.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/12.clkmgr_div_intersig_mubi.2377439003 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 30340648 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:46:54 PM PDT 24 |
Finished | Apr 04 03:46:55 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-00a430ab-923a-4483-b4f5-1366caf52f24 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377439003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.2377439003 |
Directory | /workspace/12.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/12.clkmgr_extclk.1494967142 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 51295665 ps |
CPU time | 0.98 seconds |
Started | Apr 04 03:46:51 PM PDT 24 |
Finished | Apr 04 03:46:53 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-20adb705-f60c-4617-9272-708abb3e9774 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494967142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.1494967142 |
Directory | /workspace/12.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/12.clkmgr_frequency.3149309843 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 1407484726 ps |
CPU time | 7.95 seconds |
Started | Apr 04 03:46:55 PM PDT 24 |
Finished | Apr 04 03:47:03 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-b1134e18-f771-46a3-aa60-bd7cb580f651 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149309843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.3149309843 |
Directory | /workspace/12.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/12.clkmgr_frequency_timeout.2075055295 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 2422750633 ps |
CPU time | 15.37 seconds |
Started | Apr 04 03:46:54 PM PDT 24 |
Finished | Apr 04 03:47:10 PM PDT 24 |
Peak memory | 200992 kb |
Host | smart-439d33ff-902a-4503-9e23-1d4771adda54 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075055295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t imeout.2075055295 |
Directory | /workspace/12.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.4204389830 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 17688866 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:46:55 PM PDT 24 |
Finished | Apr 04 03:46:55 PM PDT 24 |
Peak memory | 200524 kb |
Host | smart-f87c174f-2431-4926-8d96-64550f153279 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204389830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_clk_byp_req_intersig_mubi.4204389830 |
Directory | /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.2231052418 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 21194648 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:46:54 PM PDT 24 |
Finished | Apr 04 03:46:55 PM PDT 24 |
Peak memory | 200576 kb |
Host | smart-d887f49b-4fe6-4806-adf3-675e4bac7383 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231052418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_ctrl_intersig_mubi.2231052418 |
Directory | /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/12.clkmgr_peri.964649766 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 35521391 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:46:55 PM PDT 24 |
Finished | Apr 04 03:46:56 PM PDT 24 |
Peak memory | 200436 kb |
Host | smart-08516624-1e6f-45fb-a1bc-f67a055a8056 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964649766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.964649766 |
Directory | /workspace/12.clkmgr_peri/latest |
Test location | /workspace/coverage/default/12.clkmgr_regwen.563713349 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 811694653 ps |
CPU time | 4.83 seconds |
Started | Apr 04 03:46:57 PM PDT 24 |
Finished | Apr 04 03:47:02 PM PDT 24 |
Peak memory | 200748 kb |
Host | smart-96f00a44-a820-451f-9c48-1cee08e236da |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563713349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.563713349 |
Directory | /workspace/12.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/12.clkmgr_smoke.801255738 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 24406998 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:46:53 PM PDT 24 |
Finished | Apr 04 03:46:54 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-33c87989-cad1-4a0c-a8ba-ff4ebda7f0c5 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801255738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.801255738 |
Directory | /workspace/12.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/12.clkmgr_stress_all.3429830973 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 6992166467 ps |
CPU time | 49.84 seconds |
Started | Apr 04 03:46:53 PM PDT 24 |
Finished | Apr 04 03:47:43 PM PDT 24 |
Peak memory | 200916 kb |
Host | smart-eb633eba-d110-4872-b7b1-0c7ad08129db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429830973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.3429830973 |
Directory | /workspace/12.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.3777808478 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 15680560981 ps |
CPU time | 262.81 seconds |
Started | Apr 04 03:46:53 PM PDT 24 |
Finished | Apr 04 03:51:16 PM PDT 24 |
Peak memory | 209256 kb |
Host | smart-915e7b86-6f12-44ff-87bb-ee1b440bf909 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3777808478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.3777808478 |
Directory | /workspace/12.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/12.clkmgr_trans.1228831776 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 25756240 ps |
CPU time | 0.85 seconds |
Started | Apr 04 03:46:51 PM PDT 24 |
Finished | Apr 04 03:46:52 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-0b190e10-5311-4fad-8815-d3c7b6cac8bf |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228831776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.1228831776 |
Directory | /workspace/12.clkmgr_trans/latest |
Test location | /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.1024165540 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 30462602 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:47:12 PM PDT 24 |
Finished | Apr 04 03:47:13 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-0c586813-33d9-4dce-8e46-a82d3fcae660 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024165540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.1024165540 |
Directory | /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/13.clkmgr_clk_status.3651456684 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 28910043 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:47:18 PM PDT 24 |
Finished | Apr 04 03:47:19 PM PDT 24 |
Peak memory | 200292 kb |
Host | smart-e0ed252b-3c56-437b-aff0-fb16232acec9 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651456684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.3651456684 |
Directory | /workspace/13.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/13.clkmgr_div_intersig_mubi.1622321144 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 91645825 ps |
CPU time | 1.17 seconds |
Started | Apr 04 03:47:10 PM PDT 24 |
Finished | Apr 04 03:47:11 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-9cdc97b3-7be3-4fc1-9f57-4f9c9e69f302 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622321144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_div_intersig_mubi.1622321144 |
Directory | /workspace/13.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/13.clkmgr_extclk.3427566931 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 41532745 ps |
CPU time | 0.93 seconds |
Started | Apr 04 03:46:56 PM PDT 24 |
Finished | Apr 04 03:46:57 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-5e3ed4d4-bd2d-418c-8a3e-690f3b2033dd |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427566931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.3427566931 |
Directory | /workspace/13.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/13.clkmgr_frequency.4152808521 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 612014156 ps |
CPU time | 3.1 seconds |
Started | Apr 04 03:46:54 PM PDT 24 |
Finished | Apr 04 03:46:58 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-b345f45c-bf2d-48f6-9d96-574da7677994 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152808521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.4152808521 |
Directory | /workspace/13.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/13.clkmgr_frequency_timeout.503173396 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 1815174577 ps |
CPU time | 13.84 seconds |
Started | Apr 04 03:46:54 PM PDT 24 |
Finished | Apr 04 03:47:08 PM PDT 24 |
Peak memory | 200724 kb |
Host | smart-96914222-09cc-4be1-b59e-5b5b0f1b8306 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503173396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_ti meout.503173396 |
Directory | /workspace/13.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.225559533 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 12446063 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:47:10 PM PDT 24 |
Finished | Apr 04 03:47:11 PM PDT 24 |
Peak memory | 200580 kb |
Host | smart-9342196a-4e87-480d-ab4e-e0683a7e4f68 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225559533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.clkmgr_idle_intersig_mubi.225559533 |
Directory | /workspace/13.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.2854646862 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 18343473 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:47:13 PM PDT 24 |
Finished | Apr 04 03:47:13 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-0e84c26a-695f-4c08-81f6-b6d60dd1ddf4 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854646862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.clkmgr_lc_clk_byp_req_intersig_mubi.2854646862 |
Directory | /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.2370458385 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 47511642 ps |
CPU time | 0.85 seconds |
Started | Apr 04 03:47:08 PM PDT 24 |
Finished | Apr 04 03:47:09 PM PDT 24 |
Peak memory | 200688 kb |
Host | smart-2a908683-28e2-490f-b17c-db383580d0b4 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370458385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.clkmgr_lc_ctrl_intersig_mubi.2370458385 |
Directory | /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/13.clkmgr_peri.614635204 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 40830533 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:47:13 PM PDT 24 |
Finished | Apr 04 03:47:14 PM PDT 24 |
Peak memory | 200372 kb |
Host | smart-6e884da2-2795-474e-89f1-41e8f31261ab |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614635204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.614635204 |
Directory | /workspace/13.clkmgr_peri/latest |
Test location | /workspace/coverage/default/13.clkmgr_regwen.1657038168 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 684881395 ps |
CPU time | 2.91 seconds |
Started | Apr 04 03:47:18 PM PDT 24 |
Finished | Apr 04 03:47:21 PM PDT 24 |
Peak memory | 200744 kb |
Host | smart-af9a5010-f565-40f0-a9ff-8ab80f0396dc |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657038168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.1657038168 |
Directory | /workspace/13.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/13.clkmgr_smoke.3841781126 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 69454722 ps |
CPU time | 1 seconds |
Started | Apr 04 03:46:54 PM PDT 24 |
Finished | Apr 04 03:46:55 PM PDT 24 |
Peak memory | 200576 kb |
Host | smart-4c50a5d5-8991-4d9b-9655-4e10a5e0c465 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841781126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.3841781126 |
Directory | /workspace/13.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/13.clkmgr_stress_all.2978818898 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 4744158923 ps |
CPU time | 25.45 seconds |
Started | Apr 04 03:47:17 PM PDT 24 |
Finished | Apr 04 03:47:42 PM PDT 24 |
Peak memory | 200980 kb |
Host | smart-828e894b-016a-4eec-9408-a203e8aae2cb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978818898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.2978818898 |
Directory | /workspace/13.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.3739682123 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 42499753771 ps |
CPU time | 740.83 seconds |
Started | Apr 04 03:47:13 PM PDT 24 |
Finished | Apr 04 03:59:34 PM PDT 24 |
Peak memory | 212576 kb |
Host | smart-7656244c-b400-4e44-92dc-2b5456b4e104 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3739682123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.3739682123 |
Directory | /workspace/13.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.clkmgr_trans.3288678053 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 19036966 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:47:08 PM PDT 24 |
Finished | Apr 04 03:47:09 PM PDT 24 |
Peak memory | 200484 kb |
Host | smart-5e4abf35-52ca-45ff-8d23-935f72c3f819 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288678053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.3288678053 |
Directory | /workspace/13.clkmgr_trans/latest |
Test location | /workspace/coverage/default/14.clkmgr_alert_test.1490169490 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 35331447 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:47:18 PM PDT 24 |
Finished | Apr 04 03:47:19 PM PDT 24 |
Peak memory | 200480 kb |
Host | smart-195ffc06-0beb-4e6d-bbd8-75c1464dfe17 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490169490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk mgr_alert_test.1490169490 |
Directory | /workspace/14.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.895706926 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 29297843 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:47:12 PM PDT 24 |
Finished | Apr 04 03:47:13 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-b2ab8de4-7714-497f-8d3a-c94b246f856e |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895706926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.895706926 |
Directory | /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/14.clkmgr_clk_status.2889766939 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 16250537 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:47:22 PM PDT 24 |
Finished | Apr 04 03:47:23 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-860dd90e-cd55-4ad9-b08c-ad0af7274fd5 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889766939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.2889766939 |
Directory | /workspace/14.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/14.clkmgr_div_intersig_mubi.850646086 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 73418736 ps |
CPU time | 1.03 seconds |
Started | Apr 04 03:47:18 PM PDT 24 |
Finished | Apr 04 03:47:19 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-90fc1d88-f5ac-498a-ad9d-c8a21a7ba0cd |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850646086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.clkmgr_div_intersig_mubi.850646086 |
Directory | /workspace/14.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/14.clkmgr_extclk.3767436865 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 74006490 ps |
CPU time | 0.99 seconds |
Started | Apr 04 03:47:08 PM PDT 24 |
Finished | Apr 04 03:47:09 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-3d1bd60e-ddf7-4b4a-b975-324abd6a88cb |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767436865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.3767436865 |
Directory | /workspace/14.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/14.clkmgr_frequency.99446171 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 572198589 ps |
CPU time | 2.91 seconds |
Started | Apr 04 03:47:09 PM PDT 24 |
Finished | Apr 04 03:47:12 PM PDT 24 |
Peak memory | 200572 kb |
Host | smart-a3f4a07b-067a-4b37-97c7-c63ee309413b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99446171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.99446171 |
Directory | /workspace/14.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/14.clkmgr_frequency_timeout.3648257359 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 723565484 ps |
CPU time | 2.74 seconds |
Started | Apr 04 03:47:13 PM PDT 24 |
Finished | Apr 04 03:47:16 PM PDT 24 |
Peak memory | 200708 kb |
Host | smart-89bc9b72-4657-48e8-8194-d8893978241f |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648257359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t imeout.3648257359 |
Directory | /workspace/14.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.3089774441 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 121000164 ps |
CPU time | 1.29 seconds |
Started | Apr 04 03:47:11 PM PDT 24 |
Finished | Apr 04 03:47:13 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-69d27571-3823-408e-9966-b668711f1748 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089774441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.3089774441 |
Directory | /workspace/14.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.1681750865 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 18132241 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:47:11 PM PDT 24 |
Finished | Apr 04 03:47:12 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-c55ab96e-c8f9-4265-8224-902375632e3f |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681750865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.clkmgr_lc_clk_byp_req_intersig_mubi.1681750865 |
Directory | /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.1598314479 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 17077718 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:47:22 PM PDT 24 |
Finished | Apr 04 03:47:23 PM PDT 24 |
Peak memory | 199776 kb |
Host | smart-57ec02a3-1bca-4830-95c0-387499d13c5a |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598314479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.clkmgr_lc_ctrl_intersig_mubi.1598314479 |
Directory | /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/14.clkmgr_peri.868745047 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 20813393 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:47:09 PM PDT 24 |
Finished | Apr 04 03:47:10 PM PDT 24 |
Peak memory | 200380 kb |
Host | smart-9fa6acca-f172-4d00-9d71-abd95944e1b0 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868745047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.868745047 |
Directory | /workspace/14.clkmgr_peri/latest |
Test location | /workspace/coverage/default/14.clkmgr_regwen.2368094261 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 946366804 ps |
CPU time | 3.83 seconds |
Started | Apr 04 03:47:18 PM PDT 24 |
Finished | Apr 04 03:47:22 PM PDT 24 |
Peak memory | 200804 kb |
Host | smart-7e052a8f-725d-4450-bc8b-b43fa381e79a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368094261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.2368094261 |
Directory | /workspace/14.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/14.clkmgr_smoke.2600890090 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 17288284 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:47:09 PM PDT 24 |
Finished | Apr 04 03:47:10 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-1847699c-092d-4757-b1dd-7c7e98e3fc3e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600890090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.2600890090 |
Directory | /workspace/14.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/14.clkmgr_stress_all.2119167837 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 35678134 ps |
CPU time | 0.97 seconds |
Started | Apr 04 03:47:21 PM PDT 24 |
Finished | Apr 04 03:47:23 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-1fd0a925-2fff-46d8-8f2c-0536be681fb6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119167837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.2119167837 |
Directory | /workspace/14.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.1123315245 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 72459205536 ps |
CPU time | 423.35 seconds |
Started | Apr 04 03:47:18 PM PDT 24 |
Finished | Apr 04 03:54:22 PM PDT 24 |
Peak memory | 210164 kb |
Host | smart-6ac072a8-1037-4858-b205-4a1eece4fd2c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1123315245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.1123315245 |
Directory | /workspace/14.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.clkmgr_trans.88782522 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 58370900 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:47:17 PM PDT 24 |
Finished | Apr 04 03:47:18 PM PDT 24 |
Peak memory | 200524 kb |
Host | smart-9be2f436-8784-4ed6-9c51-fc2784b4616e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88782522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.88782522 |
Directory | /workspace/14.clkmgr_trans/latest |
Test location | /workspace/coverage/default/15.clkmgr_alert_test.2571121943 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 16533354 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:47:13 PM PDT 24 |
Finished | Apr 04 03:47:14 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-b8fdfb31-9bba-49ac-995a-79100f883cde |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571121943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk mgr_alert_test.2571121943 |
Directory | /workspace/15.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.1831343600 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 59269991 ps |
CPU time | 0.99 seconds |
Started | Apr 04 03:47:21 PM PDT 24 |
Finished | Apr 04 03:47:23 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-59df6154-2da4-4b87-83fe-2330b2f1e837 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831343600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.1831343600 |
Directory | /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/15.clkmgr_clk_status.2522810537 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 31437542 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:47:19 PM PDT 24 |
Finished | Apr 04 03:47:21 PM PDT 24 |
Peak memory | 199544 kb |
Host | smart-da45b258-cc62-4835-8440-385202094de0 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522810537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.2522810537 |
Directory | /workspace/15.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/15.clkmgr_div_intersig_mubi.410333724 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 16265541 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:47:14 PM PDT 24 |
Finished | Apr 04 03:47:15 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-45381802-682f-4f8a-8904-9c5ea07ebec8 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410333724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.clkmgr_div_intersig_mubi.410333724 |
Directory | /workspace/15.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/15.clkmgr_extclk.4077885880 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 16677311 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:47:18 PM PDT 24 |
Finished | Apr 04 03:47:19 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-35bb8fb4-0989-4a5f-8a84-4ad9a28fa1b8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077885880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.4077885880 |
Directory | /workspace/15.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/15.clkmgr_frequency.4028083665 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 440139108 ps |
CPU time | 3.44 seconds |
Started | Apr 04 03:47:13 PM PDT 24 |
Finished | Apr 04 03:47:16 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-fca2a025-6f16-4cb0-a504-e6febd12efa9 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028083665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.4028083665 |
Directory | /workspace/15.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/15.clkmgr_frequency_timeout.1161770540 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 991710224 ps |
CPU time | 4.36 seconds |
Started | Apr 04 03:47:11 PM PDT 24 |
Finished | Apr 04 03:47:16 PM PDT 24 |
Peak memory | 200712 kb |
Host | smart-5748519d-56d1-4102-967f-1effe58ec8e7 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161770540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t imeout.1161770540 |
Directory | /workspace/15.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.2785252047 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 50077377 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:47:22 PM PDT 24 |
Finished | Apr 04 03:47:23 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-bb2fc350-2748-4c7c-826f-170babb502a6 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785252047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_idle_intersig_mubi.2785252047 |
Directory | /workspace/15.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.3302392687 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 22215660 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:47:12 PM PDT 24 |
Finished | Apr 04 03:47:13 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-cf4a8688-5036-46da-8f97-e252b640fc0c |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302392687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_clk_byp_req_intersig_mubi.3302392687 |
Directory | /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.3506582222 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 23657369 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:47:20 PM PDT 24 |
Finished | Apr 04 03:47:21 PM PDT 24 |
Peak memory | 200552 kb |
Host | smart-321c5a5b-915e-46da-a21b-1903dd395c4d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506582222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_ctrl_intersig_mubi.3506582222 |
Directory | /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/15.clkmgr_peri.4161518063 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 42329264 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:47:11 PM PDT 24 |
Finished | Apr 04 03:47:12 PM PDT 24 |
Peak memory | 200368 kb |
Host | smart-26f70e67-7b3c-40c8-945b-6873da9ccc64 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161518063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.4161518063 |
Directory | /workspace/15.clkmgr_peri/latest |
Test location | /workspace/coverage/default/15.clkmgr_regwen.968367080 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 831659981 ps |
CPU time | 4.06 seconds |
Started | Apr 04 03:47:11 PM PDT 24 |
Finished | Apr 04 03:47:15 PM PDT 24 |
Peak memory | 200748 kb |
Host | smart-e7ac9705-cbf5-49de-8a28-cd1b8455f317 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968367080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.968367080 |
Directory | /workspace/15.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/15.clkmgr_smoke.2892180228 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 77706928 ps |
CPU time | 1.07 seconds |
Started | Apr 04 03:47:18 PM PDT 24 |
Finished | Apr 04 03:47:20 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-92979cf8-c9cc-478b-a925-5509b17f76ab |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892180228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.2892180228 |
Directory | /workspace/15.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/15.clkmgr_stress_all.3726599982 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 13841941051 ps |
CPU time | 101.67 seconds |
Started | Apr 04 03:47:10 PM PDT 24 |
Finished | Apr 04 03:48:52 PM PDT 24 |
Peak memory | 200980 kb |
Host | smart-c9800ab3-cc59-427f-b853-362b6b55546a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726599982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.3726599982 |
Directory | /workspace/15.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.899834209 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 34252277470 ps |
CPU time | 227.58 seconds |
Started | Apr 04 03:47:13 PM PDT 24 |
Finished | Apr 04 03:51:01 PM PDT 24 |
Peak memory | 209292 kb |
Host | smart-06690d02-7c91-4c31-a1b5-cd6fc5005f1d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=899834209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.899834209 |
Directory | /workspace/15.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.clkmgr_trans.2724310632 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 161516669 ps |
CPU time | 1.11 seconds |
Started | Apr 04 03:47:17 PM PDT 24 |
Finished | Apr 04 03:47:19 PM PDT 24 |
Peak memory | 200536 kb |
Host | smart-776abbf5-c909-40d3-bf33-f6d06d13b683 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724310632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.2724310632 |
Directory | /workspace/15.clkmgr_trans/latest |
Test location | /workspace/coverage/default/16.clkmgr_alert_test.3002675808 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 15674931 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:47:13 PM PDT 24 |
Finished | Apr 04 03:47:14 PM PDT 24 |
Peak memory | 200524 kb |
Host | smart-fec9e399-2fa8-4835-9725-493d3c14620e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002675808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk mgr_alert_test.3002675808 |
Directory | /workspace/16.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.2244750425 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 28549486 ps |
CPU time | 0.94 seconds |
Started | Apr 04 03:47:18 PM PDT 24 |
Finished | Apr 04 03:47:19 PM PDT 24 |
Peak memory | 200716 kb |
Host | smart-6f1f8a93-7c6c-4734-a123-0c89f3a052b9 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244750425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.2244750425 |
Directory | /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/16.clkmgr_div_intersig_mubi.3451239504 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 28322267 ps |
CPU time | 0.9 seconds |
Started | Apr 04 03:47:08 PM PDT 24 |
Finished | Apr 04 03:47:09 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-d579f078-14df-45e8-8b25-4856e72050e1 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451239504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.3451239504 |
Directory | /workspace/16.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/16.clkmgr_extclk.1697978850 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 31308781 ps |
CPU time | 0.9 seconds |
Started | Apr 04 03:47:15 PM PDT 24 |
Finished | Apr 04 03:47:16 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-ce38ee5f-932e-4d70-8953-b75126679d55 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697978850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.1697978850 |
Directory | /workspace/16.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/16.clkmgr_frequency.1008772549 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 2247224019 ps |
CPU time | 10.14 seconds |
Started | Apr 04 03:47:20 PM PDT 24 |
Finished | Apr 04 03:47:32 PM PDT 24 |
Peak memory | 200864 kb |
Host | smart-2b5530be-f9ca-4bf6-803b-862517a2185f |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008772549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.1008772549 |
Directory | /workspace/16.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/16.clkmgr_frequency_timeout.1356643795 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 140114187 ps |
CPU time | 1.31 seconds |
Started | Apr 04 03:47:07 PM PDT 24 |
Finished | Apr 04 03:47:08 PM PDT 24 |
Peak memory | 200712 kb |
Host | smart-5cf3a683-c514-482d-85e2-a0edaea70f52 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356643795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t imeout.1356643795 |
Directory | /workspace/16.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.1580599209 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 30908540 ps |
CPU time | 0.97 seconds |
Started | Apr 04 03:47:19 PM PDT 24 |
Finished | Apr 04 03:47:21 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-cd573030-9dfe-4e12-af2f-c892fb92c43c |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580599209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.1580599209 |
Directory | /workspace/16.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.1827718450 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 14855751 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:47:11 PM PDT 24 |
Finished | Apr 04 03:47:12 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-012300ba-b52f-4820-9e93-e99904db5348 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827718450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.clkmgr_lc_clk_byp_req_intersig_mubi.1827718450 |
Directory | /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.1028755852 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 32519201 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:47:20 PM PDT 24 |
Finished | Apr 04 03:47:22 PM PDT 24 |
Peak memory | 200552 kb |
Host | smart-0f58a603-858a-489f-8892-9a797f6b9a24 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028755852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.clkmgr_lc_ctrl_intersig_mubi.1028755852 |
Directory | /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/16.clkmgr_peri.1967780914 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 16586968 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:47:16 PM PDT 24 |
Finished | Apr 04 03:47:17 PM PDT 24 |
Peak memory | 200436 kb |
Host | smart-d7dfa646-e574-4688-b198-df39b11ed947 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967780914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.1967780914 |
Directory | /workspace/16.clkmgr_peri/latest |
Test location | /workspace/coverage/default/16.clkmgr_regwen.3213976985 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 221923125 ps |
CPU time | 1.31 seconds |
Started | Apr 04 03:47:19 PM PDT 24 |
Finished | Apr 04 03:47:20 PM PDT 24 |
Peak memory | 200552 kb |
Host | smart-0f4c2cc5-bbd7-44c1-b1ed-810f30bc4a54 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213976985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.3213976985 |
Directory | /workspace/16.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/16.clkmgr_smoke.4013459518 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 16410834 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:47:12 PM PDT 24 |
Finished | Apr 04 03:47:13 PM PDT 24 |
Peak memory | 200684 kb |
Host | smart-76f6c62d-8e0c-4004-8b8e-e4a6e24a4bd5 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013459518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.4013459518 |
Directory | /workspace/16.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/16.clkmgr_stress_all.2605507728 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 9528352876 ps |
CPU time | 47.58 seconds |
Started | Apr 04 03:47:13 PM PDT 24 |
Finished | Apr 04 03:48:00 PM PDT 24 |
Peak memory | 201032 kb |
Host | smart-ce1753f0-93df-42c7-91ed-6468a5f2e2e8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605507728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.2605507728 |
Directory | /workspace/16.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.2915597814 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 106279149271 ps |
CPU time | 1134.2 seconds |
Started | Apr 04 03:47:15 PM PDT 24 |
Finished | Apr 04 04:06:10 PM PDT 24 |
Peak memory | 217452 kb |
Host | smart-6a0458af-78b0-455e-af7d-2aa53aef1721 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2915597814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.2915597814 |
Directory | /workspace/16.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.clkmgr_trans.1716237630 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 30346717 ps |
CPU time | 0.95 seconds |
Started | Apr 04 03:47:10 PM PDT 24 |
Finished | Apr 04 03:47:11 PM PDT 24 |
Peak memory | 200612 kb |
Host | smart-5ef75aeb-66d9-4a85-9fac-2ca8371dea15 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716237630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.1716237630 |
Directory | /workspace/16.clkmgr_trans/latest |
Test location | /workspace/coverage/default/17.clkmgr_alert_test.4067300307 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 40834724 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:28 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-b7c62ff4-00aa-4bb5-86f0-95ca5e8945bc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067300307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk mgr_alert_test.4067300307 |
Directory | /workspace/17.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.257067651 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 14452172 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:47:21 PM PDT 24 |
Finished | Apr 04 03:47:22 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-12957a11-82ab-4f46-b31b-78256c9fc827 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257067651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.257067651 |
Directory | /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/17.clkmgr_clk_status.761389709 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 22736286 ps |
CPU time | 0.71 seconds |
Started | Apr 04 03:47:28 PM PDT 24 |
Finished | Apr 04 03:47:29 PM PDT 24 |
Peak memory | 199608 kb |
Host | smart-71f01665-1fc6-42e8-a891-b68ac595519f |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761389709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.761389709 |
Directory | /workspace/17.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/17.clkmgr_div_intersig_mubi.2931804633 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 35089432 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:28 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-94f7604f-0d48-4a62-b994-49533ef1893e |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931804633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.2931804633 |
Directory | /workspace/17.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/17.clkmgr_extclk.2416244194 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 16724652 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:47:13 PM PDT 24 |
Finished | Apr 04 03:47:14 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-7c0f697a-a96d-4659-82e2-9be22b761479 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416244194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.2416244194 |
Directory | /workspace/17.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/17.clkmgr_frequency.3220383088 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 1883566307 ps |
CPU time | 13.88 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:41 PM PDT 24 |
Peak memory | 200816 kb |
Host | smart-5db28aef-d654-49bf-a280-73f3591b7f42 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220383088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.3220383088 |
Directory | /workspace/17.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/17.clkmgr_frequency_timeout.476221797 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 976324678 ps |
CPU time | 6.22 seconds |
Started | Apr 04 03:47:31 PM PDT 24 |
Finished | Apr 04 03:47:37 PM PDT 24 |
Peak memory | 200760 kb |
Host | smart-9dbfe14d-368f-4065-9b09-8d646823f29d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476221797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_ti meout.476221797 |
Directory | /workspace/17.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.392515225 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 67252220 ps |
CPU time | 0.93 seconds |
Started | Apr 04 03:47:23 PM PDT 24 |
Finished | Apr 04 03:47:24 PM PDT 24 |
Peak memory | 200504 kb |
Host | smart-a5e9b86c-1d36-4497-bd39-c113c157fb1b |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392515225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.clkmgr_idle_intersig_mubi.392515225 |
Directory | /workspace/17.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.2481247354 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 18374102 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:47:30 PM PDT 24 |
Finished | Apr 04 03:47:31 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-874b9d2c-37a0-46a8-809d-5917e4d6ee87 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481247354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 17.clkmgr_lc_clk_byp_req_intersig_mubi.2481247354 |
Directory | /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.770711970 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 20465092 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:47:25 PM PDT 24 |
Finished | Apr 04 03:47:26 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-6cbc331e-ddea-45e0-9f06-c79ef962fda6 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770711970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.clkmgr_lc_ctrl_intersig_mubi.770711970 |
Directory | /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/17.clkmgr_peri.2316086678 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 16828854 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:47:25 PM PDT 24 |
Finished | Apr 04 03:47:26 PM PDT 24 |
Peak memory | 200344 kb |
Host | smart-7e9a7112-5d02-45ae-b688-a8a9c9d6b9a3 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316086678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.2316086678 |
Directory | /workspace/17.clkmgr_peri/latest |
Test location | /workspace/coverage/default/17.clkmgr_regwen.2598024401 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 888724554 ps |
CPU time | 3.61 seconds |
Started | Apr 04 03:47:29 PM PDT 24 |
Finished | Apr 04 03:47:33 PM PDT 24 |
Peak memory | 200784 kb |
Host | smart-b078f521-61cf-4ef1-8ded-208842353c06 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598024401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.2598024401 |
Directory | /workspace/17.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/17.clkmgr_smoke.1654240557 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 65881814 ps |
CPU time | 0.99 seconds |
Started | Apr 04 03:47:13 PM PDT 24 |
Finished | Apr 04 03:47:14 PM PDT 24 |
Peak memory | 200680 kb |
Host | smart-d71e5c53-25bf-440c-ad79-5fc02e693155 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654240557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.1654240557 |
Directory | /workspace/17.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/17.clkmgr_stress_all.1273373367 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 2989530290 ps |
CPU time | 15.3 seconds |
Started | Apr 04 03:47:22 PM PDT 24 |
Finished | Apr 04 03:47:37 PM PDT 24 |
Peak memory | 200984 kb |
Host | smart-3f5b6ace-edaa-4012-ac64-2bb18252f55d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273373367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.1273373367 |
Directory | /workspace/17.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.365486015 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 134836011802 ps |
CPU time | 858.81 seconds |
Started | Apr 04 03:47:30 PM PDT 24 |
Finished | Apr 04 04:01:49 PM PDT 24 |
Peak memory | 209300 kb |
Host | smart-53583d91-a338-475d-ae01-f5feccdd9fc2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=365486015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.365486015 |
Directory | /workspace/17.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.clkmgr_trans.2401547722 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 82740410 ps |
CPU time | 1.04 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:33 PM PDT 24 |
Peak memory | 200544 kb |
Host | smart-6742dc13-cc3f-4ff8-9dff-8809971dd156 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401547722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.2401547722 |
Directory | /workspace/17.clkmgr_trans/latest |
Test location | /workspace/coverage/default/18.clkmgr_alert_test.1242557478 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 92332126 ps |
CPU time | 1.05 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:28 PM PDT 24 |
Peak memory | 200524 kb |
Host | smart-47719f38-25a7-42ba-b26f-86f82bea6cd4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242557478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk mgr_alert_test.1242557478 |
Directory | /workspace/18.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.3813670944 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 252757331 ps |
CPU time | 1.45 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:34 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-459d5548-c80f-47b8-ae61-b73e85d72078 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813670944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.3813670944 |
Directory | /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/18.clkmgr_clk_status.1772601342 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 21495000 ps |
CPU time | 0.71 seconds |
Started | Apr 04 03:47:24 PM PDT 24 |
Finished | Apr 04 03:47:25 PM PDT 24 |
Peak memory | 199580 kb |
Host | smart-c6bfd835-0e4a-4256-ad17-16d36fa406fe |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772601342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.1772601342 |
Directory | /workspace/18.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/18.clkmgr_div_intersig_mubi.2391735827 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 20443166 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:47:26 PM PDT 24 |
Finished | Apr 04 03:47:27 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-39d91639-ea9e-4be5-b5c6-bffa3ddef077 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391735827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_div_intersig_mubi.2391735827 |
Directory | /workspace/18.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/18.clkmgr_extclk.1765163991 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 40954154 ps |
CPU time | 0.92 seconds |
Started | Apr 04 03:47:25 PM PDT 24 |
Finished | Apr 04 03:47:26 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-a5e61d0f-b63e-4627-a379-be5982979669 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765163991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.1765163991 |
Directory | /workspace/18.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/18.clkmgr_frequency.1267436847 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 2238066896 ps |
CPU time | 16.85 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:44 PM PDT 24 |
Peak memory | 200848 kb |
Host | smart-e2fd9e43-ebc4-4aa5-b467-de41cc3d987b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267436847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.1267436847 |
Directory | /workspace/18.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/18.clkmgr_frequency_timeout.1181037686 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 2303777957 ps |
CPU time | 12.4 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:45 PM PDT 24 |
Peak memory | 200932 kb |
Host | smart-140167ab-957e-4b84-87fe-e8dbe3ea53fb |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181037686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t imeout.1181037686 |
Directory | /workspace/18.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.206084606 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 91709978 ps |
CPU time | 1.1 seconds |
Started | Apr 04 03:47:30 PM PDT 24 |
Finished | Apr 04 03:47:31 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-b76c570f-cc8a-424b-950f-ee21c5df20b6 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206084606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.clkmgr_idle_intersig_mubi.206084606 |
Directory | /workspace/18.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.144482226 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 59746285 ps |
CPU time | 0.94 seconds |
Started | Apr 04 03:47:22 PM PDT 24 |
Finished | Apr 04 03:47:23 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-7883a090-f240-4d6c-86b2-0bac35debc3d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144482226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.clkmgr_lc_clk_byp_req_intersig_mubi.144482226 |
Directory | /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.1501621034 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 45860257 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:47:28 PM PDT 24 |
Finished | Apr 04 03:47:29 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-6704615d-ef35-43d0-8c21-d71747b1fd12 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501621034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 18.clkmgr_lc_ctrl_intersig_mubi.1501621034 |
Directory | /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/18.clkmgr_peri.1992426215 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 31230571 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:33 PM PDT 24 |
Peak memory | 200348 kb |
Host | smart-f58dbc41-c77e-4582-86a9-a25abd24abd6 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992426215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.1992426215 |
Directory | /workspace/18.clkmgr_peri/latest |
Test location | /workspace/coverage/default/18.clkmgr_regwen.2873651545 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 1228920467 ps |
CPU time | 4.79 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:32 PM PDT 24 |
Peak memory | 200768 kb |
Host | smart-e7782490-0393-4ddc-a299-efd60a0b2be4 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873651545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.2873651545 |
Directory | /workspace/18.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/18.clkmgr_smoke.2114134945 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 16481760 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:47:21 PM PDT 24 |
Finished | Apr 04 03:47:22 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-a6999325-a354-4e6f-a79b-decdf1df1b02 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114134945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.2114134945 |
Directory | /workspace/18.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/18.clkmgr_stress_all.969851102 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 8200868166 ps |
CPU time | 25.21 seconds |
Started | Apr 04 03:47:25 PM PDT 24 |
Finished | Apr 04 03:47:51 PM PDT 24 |
Peak memory | 200996 kb |
Host | smart-2f13e518-7105-4037-978c-2ce05d469150 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969851102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.969851102 |
Directory | /workspace/18.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.708920167 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 149970816188 ps |
CPU time | 1147.04 seconds |
Started | Apr 04 03:47:30 PM PDT 24 |
Finished | Apr 04 04:06:37 PM PDT 24 |
Peak memory | 209324 kb |
Host | smart-1d027a8c-0a0e-4076-b4f5-607e8512b68f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=708920167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.708920167 |
Directory | /workspace/18.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.clkmgr_trans.1725705615 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 184676694 ps |
CPU time | 1.38 seconds |
Started | Apr 04 03:47:35 PM PDT 24 |
Finished | Apr 04 03:47:36 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-d95538de-5fd4-4997-b4ef-a053ac3854c5 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725705615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.1725705615 |
Directory | /workspace/18.clkmgr_trans/latest |
Test location | /workspace/coverage/default/19.clkmgr_alert_test.3743295796 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 20510747 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:28 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-9a4b8dd9-d8f3-4565-b051-e877dad70985 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743295796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk mgr_alert_test.3743295796 |
Directory | /workspace/19.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.4238903458 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 42013463 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:47:23 PM PDT 24 |
Finished | Apr 04 03:47:25 PM PDT 24 |
Peak memory | 200584 kb |
Host | smart-2b3a8011-33d5-46fa-830f-1ead71486d8b |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238903458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.4238903458 |
Directory | /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/19.clkmgr_clk_status.400683367 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 12927957 ps |
CPU time | 0.7 seconds |
Started | Apr 04 03:47:28 PM PDT 24 |
Finished | Apr 04 03:47:29 PM PDT 24 |
Peak memory | 199584 kb |
Host | smart-62ac661d-4988-4d2c-8733-68e46325c29b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400683367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.400683367 |
Directory | /workspace/19.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/19.clkmgr_div_intersig_mubi.273695723 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 26535019 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:28 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-bbc07778-6752-49ed-aa8b-c23aabf46532 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273695723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.clkmgr_div_intersig_mubi.273695723 |
Directory | /workspace/19.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/19.clkmgr_extclk.2558447818 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 47584496 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:47:28 PM PDT 24 |
Finished | Apr 04 03:47:29 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-2f5070d9-7bff-44fe-835c-0d3482e476cb |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558447818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2558447818 |
Directory | /workspace/19.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/19.clkmgr_frequency.2102073558 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 2005279095 ps |
CPU time | 11.33 seconds |
Started | Apr 04 03:47:25 PM PDT 24 |
Finished | Apr 04 03:47:37 PM PDT 24 |
Peak memory | 200780 kb |
Host | smart-bd4cd78f-69df-4e64-8a89-9f8004dfd0fa |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102073558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.2102073558 |
Directory | /workspace/19.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/19.clkmgr_frequency_timeout.2413654130 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 2142269754 ps |
CPU time | 8.88 seconds |
Started | Apr 04 03:47:22 PM PDT 24 |
Finished | Apr 04 03:47:31 PM PDT 24 |
Peak memory | 200864 kb |
Host | smart-244caebf-3616-4a96-9551-5ca9cbf1b207 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413654130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t imeout.2413654130 |
Directory | /workspace/19.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.3556183569 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 24019557 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:47:25 PM PDT 24 |
Finished | Apr 04 03:47:26 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-1ba251e3-9d6b-4ab8-be1c-f0091eeb9b6d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556183569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.3556183569 |
Directory | /workspace/19.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.3074059512 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 19796771 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:47:28 PM PDT 24 |
Finished | Apr 04 03:47:29 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-2beea889-77f7-42ee-a622-4c804a8d49a2 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074059512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.clkmgr_lc_clk_byp_req_intersig_mubi.3074059512 |
Directory | /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.1601233408 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 24796765 ps |
CPU time | 0.88 seconds |
Started | Apr 04 03:47:22 PM PDT 24 |
Finished | Apr 04 03:47:24 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-4864b836-a942-4100-9d88-a35bcd51d2c6 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601233408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.clkmgr_lc_ctrl_intersig_mubi.1601233408 |
Directory | /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/19.clkmgr_peri.3005382987 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 33352656 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:47:21 PM PDT 24 |
Finished | Apr 04 03:47:22 PM PDT 24 |
Peak memory | 200336 kb |
Host | smart-0d6ff035-15e5-4d6a-8e2c-7690855139a2 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005382987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.3005382987 |
Directory | /workspace/19.clkmgr_peri/latest |
Test location | /workspace/coverage/default/19.clkmgr_smoke.154697062 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 23221647 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:47:29 PM PDT 24 |
Finished | Apr 04 03:47:30 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-5feeff94-96b8-4b3a-939e-d7915269a96d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154697062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.154697062 |
Directory | /workspace/19.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/19.clkmgr_stress_all.3000032601 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 3861288258 ps |
CPU time | 16.62 seconds |
Started | Apr 04 03:47:28 PM PDT 24 |
Finished | Apr 04 03:47:45 PM PDT 24 |
Peak memory | 201004 kb |
Host | smart-6fce696e-01c0-40d8-a41a-03e0da34a98d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000032601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.3000032601 |
Directory | /workspace/19.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.2712948010 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 166702144282 ps |
CPU time | 1050.08 seconds |
Started | Apr 04 03:47:22 PM PDT 24 |
Finished | Apr 04 04:04:52 PM PDT 24 |
Peak memory | 216576 kb |
Host | smart-7995f8c4-265a-41a7-9eaf-35b44674c614 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2712948010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.2712948010 |
Directory | /workspace/19.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.clkmgr_trans.146798252 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 44579895 ps |
CPU time | 0.91 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:28 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-eea4a653-e043-4bfc-8a35-f17fa9ca4c0e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146798252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.146798252 |
Directory | /workspace/19.clkmgr_trans/latest |
Test location | /workspace/coverage/default/2.clkmgr_alert_test.609638584 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 20298399 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:46:28 PM PDT 24 |
Finished | Apr 04 03:46:29 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-42bb89f1-fa28-4637-bfe1-6804ae7894b3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609638584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg r_alert_test.609638584 |
Directory | /workspace/2.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.815749130 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 20573879 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:46:10 PM PDT 24 |
Finished | Apr 04 03:46:11 PM PDT 24 |
Peak memory | 200680 kb |
Host | smart-948d7684-e781-4332-8a90-74194c1c54ff |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815749130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.815749130 |
Directory | /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/2.clkmgr_clk_status.4073109299 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 45575260 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:46:14 PM PDT 24 |
Finished | Apr 04 03:46:15 PM PDT 24 |
Peak memory | 199600 kb |
Host | smart-80189bed-eb8d-404f-b803-4c2d170a441b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073109299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.4073109299 |
Directory | /workspace/2.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/2.clkmgr_div_intersig_mubi.3544887585 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 70521479 ps |
CPU time | 1.01 seconds |
Started | Apr 04 03:46:14 PM PDT 24 |
Finished | Apr 04 03:46:16 PM PDT 24 |
Peak memory | 200232 kb |
Host | smart-3fc10b96-1b7b-45f3-8f46-9ebd51619cc9 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544887585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.3544887585 |
Directory | /workspace/2.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/2.clkmgr_extclk.2864528451 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 37746908 ps |
CPU time | 0.92 seconds |
Started | Apr 04 03:46:15 PM PDT 24 |
Finished | Apr 04 03:46:16 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-e0851ed7-17de-4ffc-987f-76d694d63e6b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864528451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.2864528451 |
Directory | /workspace/2.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/2.clkmgr_frequency.2922140557 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 2000557032 ps |
CPU time | 10.61 seconds |
Started | Apr 04 03:46:13 PM PDT 24 |
Finished | Apr 04 03:46:24 PM PDT 24 |
Peak memory | 200856 kb |
Host | smart-955e9313-88e2-4f6a-a4fd-a5b1821ac46a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922140557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.2922140557 |
Directory | /workspace/2.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/2.clkmgr_frequency_timeout.821561451 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 1343868007 ps |
CPU time | 6.99 seconds |
Started | Apr 04 03:46:17 PM PDT 24 |
Finished | Apr 04 03:46:24 PM PDT 24 |
Peak memory | 200712 kb |
Host | smart-5f3d049c-cc0a-4a71-b254-f35140bcd484 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821561451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_tim eout.821561451 |
Directory | /workspace/2.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.2385461160 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 34902036 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:46:13 PM PDT 24 |
Finished | Apr 04 03:46:14 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-673d7f13-2914-488a-92c8-a8f660f04d38 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385461160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.2385461160 |
Directory | /workspace/2.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.2833057597 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 57252227 ps |
CPU time | 0.98 seconds |
Started | Apr 04 03:46:16 PM PDT 24 |
Finished | Apr 04 03:46:17 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-e2d0622b-e4f8-4cb5-a1f3-9b5db21362c5 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833057597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_clk_byp_req_intersig_mubi.2833057597 |
Directory | /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.2880968982 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 64789338 ps |
CPU time | 0.97 seconds |
Started | Apr 04 03:46:14 PM PDT 24 |
Finished | Apr 04 03:46:15 PM PDT 24 |
Peak memory | 200612 kb |
Host | smart-e681e17e-a7c4-45e7-9b9d-7454feba7f93 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880968982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_ctrl_intersig_mubi.2880968982 |
Directory | /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/2.clkmgr_peri.3588680026 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 40722998 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:46:12 PM PDT 24 |
Finished | Apr 04 03:46:13 PM PDT 24 |
Peak memory | 200356 kb |
Host | smart-bccdeb2b-bb08-4907-a577-479e5e872327 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588680026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.3588680026 |
Directory | /workspace/2.clkmgr_peri/latest |
Test location | /workspace/coverage/default/2.clkmgr_regwen.2687039915 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 1498161651 ps |
CPU time | 5.37 seconds |
Started | Apr 04 03:46:12 PM PDT 24 |
Finished | Apr 04 03:46:17 PM PDT 24 |
Peak memory | 200816 kb |
Host | smart-1992f215-7f7d-4b58-a10e-2d37c10d804f |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687039915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.2687039915 |
Directory | /workspace/2.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/2.clkmgr_smoke.954895920 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 18769745 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:46:15 PM PDT 24 |
Finished | Apr 04 03:46:16 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-ce17da5a-196f-4839-a3eb-e62e279a8a11 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954895920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.954895920 |
Directory | /workspace/2.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/2.clkmgr_stress_all.1243257495 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 7033034785 ps |
CPU time | 49.09 seconds |
Started | Apr 04 03:46:18 PM PDT 24 |
Finished | Apr 04 03:47:07 PM PDT 24 |
Peak memory | 201040 kb |
Host | smart-5eae873c-f193-4b4e-a739-baff64ef63fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243257495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.1243257495 |
Directory | /workspace/2.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.647030896 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 21729139884 ps |
CPU time | 337.8 seconds |
Started | Apr 04 03:46:16 PM PDT 24 |
Finished | Apr 04 03:51:54 PM PDT 24 |
Peak memory | 209228 kb |
Host | smart-8d0c864f-afb1-4321-b54b-acce013b8f94 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=647030896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.647030896 |
Directory | /workspace/2.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.clkmgr_trans.3090643126 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 47568609 ps |
CPU time | 1 seconds |
Started | Apr 04 03:46:14 PM PDT 24 |
Finished | Apr 04 03:46:16 PM PDT 24 |
Peak memory | 200392 kb |
Host | smart-9584c1d8-5826-4d1a-8bc2-b0cc32f9c862 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090643126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.3090643126 |
Directory | /workspace/2.clkmgr_trans/latest |
Test location | /workspace/coverage/default/20.clkmgr_alert_test.3190411069 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 137674876 ps |
CPU time | 1.06 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:29 PM PDT 24 |
Peak memory | 200460 kb |
Host | smart-63387d85-7ba5-46b5-a750-6921d72c02ce |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190411069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk mgr_alert_test.3190411069 |
Directory | /workspace/20.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.759311554 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 348769357 ps |
CPU time | 1.71 seconds |
Started | Apr 04 03:47:29 PM PDT 24 |
Finished | Apr 04 03:47:31 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-4037f628-ecbd-4e52-a89d-6a950cd74be6 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759311554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.759311554 |
Directory | /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/20.clkmgr_clk_status.3045765271 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 26994626 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:47:28 PM PDT 24 |
Finished | Apr 04 03:47:29 PM PDT 24 |
Peak memory | 199572 kb |
Host | smart-1ad49615-5c64-4744-933f-deff8eef89ee |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045765271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.3045765271 |
Directory | /workspace/20.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/20.clkmgr_div_intersig_mubi.2630472526 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 21232790 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:28 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-b72062a1-c9e2-4ddb-ba8a-80bcb3e3f202 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630472526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.2630472526 |
Directory | /workspace/20.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/20.clkmgr_extclk.3817583241 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 36462533 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:33 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-bbae962f-d1ff-4410-a2bd-7ab9e4bdebb6 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817583241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.3817583241 |
Directory | /workspace/20.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/20.clkmgr_frequency.586630694 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 678145070 ps |
CPU time | 5.55 seconds |
Started | Apr 04 03:47:25 PM PDT 24 |
Finished | Apr 04 03:47:30 PM PDT 24 |
Peak memory | 200596 kb |
Host | smart-f1634236-2665-42b6-8566-ce0ac28b179c |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586630694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.586630694 |
Directory | /workspace/20.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/20.clkmgr_frequency_timeout.114183458 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 1465201217 ps |
CPU time | 6.99 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:39 PM PDT 24 |
Peak memory | 200704 kb |
Host | smart-fb47b769-9812-47e0-a6a3-ba600aad1ae5 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114183458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_ti meout.114183458 |
Directory | /workspace/20.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.1508440729 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 16658441 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:47:30 PM PDT 24 |
Finished | Apr 04 03:47:31 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-d5a21f5e-0dc5-4b08-8d61-e220e68cdd39 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508440729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.1508440729 |
Directory | /workspace/20.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.2669864908 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 23454915 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:47:28 PM PDT 24 |
Finished | Apr 04 03:47:29 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-bed97744-5ab9-46a1-aded-a22f8702ad8f |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669864908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_clk_byp_req_intersig_mubi.2669864908 |
Directory | /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.3800569996 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 27575610 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:47:28 PM PDT 24 |
Finished | Apr 04 03:47:29 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-bccb8ed8-cb5e-4ec3-b6b1-75498de60e35 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800569996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_ctrl_intersig_mubi.3800569996 |
Directory | /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/20.clkmgr_peri.4252626981 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 16654703 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:28 PM PDT 24 |
Peak memory | 200352 kb |
Host | smart-ec197642-39f5-4274-999c-1e6c13f5f2a9 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252626981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.4252626981 |
Directory | /workspace/20.clkmgr_peri/latest |
Test location | /workspace/coverage/default/20.clkmgr_regwen.4069593612 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 1308082336 ps |
CPU time | 4.77 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:33 PM PDT 24 |
Peak memory | 200784 kb |
Host | smart-8243cb5f-c201-4be5-8f57-c15240bd595e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069593612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.4069593612 |
Directory | /workspace/20.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/20.clkmgr_smoke.4100351195 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 61986275 ps |
CPU time | 0.92 seconds |
Started | Apr 04 03:47:26 PM PDT 24 |
Finished | Apr 04 03:47:28 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-690357b5-3a85-4b21-bfc2-5357493d76bd |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100351195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.4100351195 |
Directory | /workspace/20.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/20.clkmgr_stress_all.3149340774 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 2857472282 ps |
CPU time | 21.01 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:53 PM PDT 24 |
Peak memory | 201044 kb |
Host | smart-f14166b3-187e-4697-bce8-01606c404db5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149340774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.3149340774 |
Directory | /workspace/20.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.1300928764 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 17668553872 ps |
CPU time | 330.28 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:52:58 PM PDT 24 |
Peak memory | 209204 kb |
Host | smart-3ab6c829-3e45-4785-8920-7fc91e24c19e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1300928764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.1300928764 |
Directory | /workspace/20.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.clkmgr_trans.2475073050 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 64469140 ps |
CPU time | 0.93 seconds |
Started | Apr 04 03:47:26 PM PDT 24 |
Finished | Apr 04 03:47:28 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-f7dbafe3-46e1-446c-b851-f4a3e24cecf3 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475073050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.2475073050 |
Directory | /workspace/20.clkmgr_trans/latest |
Test location | /workspace/coverage/default/21.clkmgr_alert_test.1179487490 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 35698803 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:47:29 PM PDT 24 |
Finished | Apr 04 03:47:29 PM PDT 24 |
Peak memory | 200440 kb |
Host | smart-41d62929-4477-4b04-bdb6-4e929da41449 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179487490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk mgr_alert_test.1179487490 |
Directory | /workspace/21.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.3710528601 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 17534430 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:47:29 PM PDT 24 |
Finished | Apr 04 03:47:30 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-c4800727-f297-418d-89eb-e3185865046d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710528601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.3710528601 |
Directory | /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/21.clkmgr_clk_status.2961128668 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 13427847 ps |
CPU time | 0.7 seconds |
Started | Apr 04 03:47:31 PM PDT 24 |
Finished | Apr 04 03:47:32 PM PDT 24 |
Peak memory | 199608 kb |
Host | smart-fdec16ca-62e8-4a95-bdc1-17420e4615d8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961128668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.2961128668 |
Directory | /workspace/21.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/21.clkmgr_div_intersig_mubi.3021789966 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 54173763 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:47:28 PM PDT 24 |
Finished | Apr 04 03:47:29 PM PDT 24 |
Peak memory | 200580 kb |
Host | smart-c05826a0-6b44-48b7-9391-84e46a4a37c2 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021789966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.3021789966 |
Directory | /workspace/21.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/21.clkmgr_extclk.1164555077 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 348774241 ps |
CPU time | 1.75 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:34 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-bbc93da8-7825-4a7d-99dc-66aac517f99d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164555077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.1164555077 |
Directory | /workspace/21.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/21.clkmgr_frequency.3448708701 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 1408639966 ps |
CPU time | 6.35 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:34 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-21424ea4-7e5e-4c00-855f-85c44a6fcc3b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448708701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.3448708701 |
Directory | /workspace/21.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/21.clkmgr_frequency_timeout.2490510596 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 1595411789 ps |
CPU time | 6.13 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:34 PM PDT 24 |
Peak memory | 200688 kb |
Host | smart-41190a12-39e0-45d5-adbb-0586196c125a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490510596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t imeout.2490510596 |
Directory | /workspace/21.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.1595907644 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 23774618 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:33 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-83850131-b24b-44a2-8cf4-afae56091c55 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595907644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.1595907644 |
Directory | /workspace/21.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.2855550098 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 17319328 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:47:29 PM PDT 24 |
Finished | Apr 04 03:47:30 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-62a63106-11a7-4ab7-9f90-ce18d5b4bfe9 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855550098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.clkmgr_lc_clk_byp_req_intersig_mubi.2855550098 |
Directory | /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.335530874 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 127388721 ps |
CPU time | 1.16 seconds |
Started | Apr 04 03:47:26 PM PDT 24 |
Finished | Apr 04 03:47:28 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-b101006e-525f-48c6-97cc-ccbf5cf10470 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335530874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.clkmgr_lc_ctrl_intersig_mubi.335530874 |
Directory | /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/21.clkmgr_peri.1121184444 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 17004873 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:47:26 PM PDT 24 |
Finished | Apr 04 03:47:27 PM PDT 24 |
Peak memory | 200348 kb |
Host | smart-511c5961-2faf-4264-af49-f71ed9604f39 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121184444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.1121184444 |
Directory | /workspace/21.clkmgr_peri/latest |
Test location | /workspace/coverage/default/21.clkmgr_regwen.1714995254 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 593456059 ps |
CPU time | 2.56 seconds |
Started | Apr 04 03:47:27 PM PDT 24 |
Finished | Apr 04 03:47:29 PM PDT 24 |
Peak memory | 200740 kb |
Host | smart-6abb92f6-6ace-4b08-9fcd-154494662153 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714995254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.1714995254 |
Directory | /workspace/21.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/21.clkmgr_smoke.73645560 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 44215791 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:47:35 PM PDT 24 |
Finished | Apr 04 03:47:36 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-f5a27bc9-a59c-4bb9-888c-7cc4a5566529 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73645560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.73645560 |
Directory | /workspace/21.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/21.clkmgr_stress_all.4190349485 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 7494874784 ps |
CPU time | 37.83 seconds |
Started | Apr 04 03:47:31 PM PDT 24 |
Finished | Apr 04 03:48:09 PM PDT 24 |
Peak memory | 201088 kb |
Host | smart-3e5c1302-12fd-486a-8bb3-a32ba61a90bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190349485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.4190349485 |
Directory | /workspace/21.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/21.clkmgr_trans.249133645 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 158845213 ps |
CPU time | 1.39 seconds |
Started | Apr 04 03:47:28 PM PDT 24 |
Finished | Apr 04 03:47:29 PM PDT 24 |
Peak memory | 200564 kb |
Host | smart-4f3c9d09-bdf8-4dfa-91b3-84d8e21a757e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249133645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.249133645 |
Directory | /workspace/21.clkmgr_trans/latest |
Test location | /workspace/coverage/default/22.clkmgr_alert_test.3065985883 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 26601748 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:33 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-a4045099-4f84-4a83-9f8e-a3c02a1df090 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065985883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk mgr_alert_test.3065985883 |
Directory | /workspace/22.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.2868899015 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 19663657 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:47:37 PM PDT 24 |
Finished | Apr 04 03:47:38 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-fe5842fd-c271-4ccc-95cf-0c96afdb851e |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868899015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.2868899015 |
Directory | /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/22.clkmgr_clk_status.994657475 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 15491786 ps |
CPU time | 0.7 seconds |
Started | Apr 04 03:47:30 PM PDT 24 |
Finished | Apr 04 03:47:31 PM PDT 24 |
Peak memory | 199588 kb |
Host | smart-35736d54-a175-4159-b534-8d3d15a05d70 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994657475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.994657475 |
Directory | /workspace/22.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/22.clkmgr_div_intersig_mubi.3947949015 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 70055213 ps |
CPU time | 0.94 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:33 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-6eb1f68b-5f29-4bad-9ddb-a52615815676 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947949015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.3947949015 |
Directory | /workspace/22.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/22.clkmgr_extclk.35746960 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 125342335 ps |
CPU time | 1.09 seconds |
Started | Apr 04 03:47:29 PM PDT 24 |
Finished | Apr 04 03:47:30 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-b6fbc738-6392-41b5-9106-42e673f64355 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35746960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.35746960 |
Directory | /workspace/22.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/22.clkmgr_frequency.3942193710 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 442198972 ps |
CPU time | 4.07 seconds |
Started | Apr 04 03:47:31 PM PDT 24 |
Finished | Apr 04 03:47:35 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-c435adc4-15d7-4914-8c3e-4d81f53e67be |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942193710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.3942193710 |
Directory | /workspace/22.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/22.clkmgr_frequency_timeout.1604118960 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 1579207590 ps |
CPU time | 8.45 seconds |
Started | Apr 04 03:47:25 PM PDT 24 |
Finished | Apr 04 03:47:34 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-797c4e48-559a-442e-9298-fe6b151b6626 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604118960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t imeout.1604118960 |
Directory | /workspace/22.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.3248050040 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 30411015 ps |
CPU time | 0.96 seconds |
Started | Apr 04 03:47:36 PM PDT 24 |
Finished | Apr 04 03:47:37 PM PDT 24 |
Peak memory | 200592 kb |
Host | smart-d82048ac-42ff-4172-a171-b9a6eeb90ca3 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248050040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.3248050040 |
Directory | /workspace/22.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.3624593855 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 66607821 ps |
CPU time | 0.98 seconds |
Started | Apr 04 03:47:31 PM PDT 24 |
Finished | Apr 04 03:47:33 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-a3c43b6a-2b04-47f6-9537-1c70a17889d0 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624593855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.clkmgr_lc_clk_byp_req_intersig_mubi.3624593855 |
Directory | /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.2449365180 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 23763014 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:47:36 PM PDT 24 |
Finished | Apr 04 03:47:37 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-a0712776-448f-4044-948c-16a287d1ffbe |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449365180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.clkmgr_lc_ctrl_intersig_mubi.2449365180 |
Directory | /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/22.clkmgr_peri.1769045998 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 18023957 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:47:26 PM PDT 24 |
Finished | Apr 04 03:47:28 PM PDT 24 |
Peak memory | 200416 kb |
Host | smart-9195ec1a-907a-4407-b499-05a42516e96b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769045998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.1769045998 |
Directory | /workspace/22.clkmgr_peri/latest |
Test location | /workspace/coverage/default/22.clkmgr_regwen.891885550 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 1472571548 ps |
CPU time | 5.48 seconds |
Started | Apr 04 03:47:34 PM PDT 24 |
Finished | Apr 04 03:47:39 PM PDT 24 |
Peak memory | 200800 kb |
Host | smart-5c786c05-920a-4a1d-94fc-fbc0242845da |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891885550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.891885550 |
Directory | /workspace/22.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/22.clkmgr_smoke.2243830847 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 59934083 ps |
CPU time | 1.01 seconds |
Started | Apr 04 03:47:30 PM PDT 24 |
Finished | Apr 04 03:47:32 PM PDT 24 |
Peak memory | 200688 kb |
Host | smart-9443c2fd-eb9f-4f3b-ad05-399dcf61fae0 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243830847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.2243830847 |
Directory | /workspace/22.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/22.clkmgr_stress_all.3549386412 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 125495801 ps |
CPU time | 1.08 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:33 PM PDT 24 |
Peak memory | 200356 kb |
Host | smart-d2185f20-e1da-4a0b-9f0c-d3af2bb327d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549386412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.3549386412 |
Directory | /workspace/22.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.3038476494 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 16890232571 ps |
CPU time | 238.88 seconds |
Started | Apr 04 03:47:31 PM PDT 24 |
Finished | Apr 04 03:51:30 PM PDT 24 |
Peak memory | 217364 kb |
Host | smart-04d84d10-c08c-4af1-aa3a-e3c9060964dd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3038476494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.3038476494 |
Directory | /workspace/22.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.clkmgr_trans.987172 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 28897042 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:47:31 PM PDT 24 |
Finished | Apr 04 03:47:31 PM PDT 24 |
Peak memory | 200540 kb |
Host | smart-bcd16ee2-dd08-41f6-8943-c25b59b910d2 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.987172 |
Directory | /workspace/22.clkmgr_trans/latest |
Test location | /workspace/coverage/default/23.clkmgr_alert_test.2416163612 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 14097146 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:47:36 PM PDT 24 |
Finished | Apr 04 03:47:37 PM PDT 24 |
Peak memory | 200400 kb |
Host | smart-b6a7f62e-db55-4d97-a69c-7687bdbee043 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416163612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk mgr_alert_test.2416163612 |
Directory | /workspace/23.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.2820488934 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 65011824 ps |
CPU time | 0.94 seconds |
Started | Apr 04 03:47:35 PM PDT 24 |
Finished | Apr 04 03:47:36 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-f171a864-29f1-43bf-b5b7-0c892996d143 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820488934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.2820488934 |
Directory | /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/23.clkmgr_clk_status.1683404451 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 14428250 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:47:39 PM PDT 24 |
Finished | Apr 04 03:47:40 PM PDT 24 |
Peak memory | 200324 kb |
Host | smart-402d6dba-083b-4b88-b47b-63802e292efb |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683404451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.1683404451 |
Directory | /workspace/23.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/23.clkmgr_div_intersig_mubi.1853784087 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 20593707 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:47:33 PM PDT 24 |
Finished | Apr 04 03:47:34 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-c49c27da-d2b4-45d0-885f-58e5656222d8 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853784087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_div_intersig_mubi.1853784087 |
Directory | /workspace/23.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/23.clkmgr_extclk.145305558 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 15970471 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:33 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-9b9819cc-08fb-472d-9ee9-c516cb88a29b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145305558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.145305558 |
Directory | /workspace/23.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/23.clkmgr_frequency.1289829270 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 703674705 ps |
CPU time | 3.06 seconds |
Started | Apr 04 03:47:31 PM PDT 24 |
Finished | Apr 04 03:47:35 PM PDT 24 |
Peak memory | 200528 kb |
Host | smart-ef24b231-5620-45c8-84c0-8f8a069e441c |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289829270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.1289829270 |
Directory | /workspace/23.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/23.clkmgr_frequency_timeout.3212755262 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 1249646785 ps |
CPU time | 4.06 seconds |
Started | Apr 04 03:47:39 PM PDT 24 |
Finished | Apr 04 03:47:43 PM PDT 24 |
Peak memory | 200708 kb |
Host | smart-bee625bf-94fa-4b1d-a441-cec1558f2087 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212755262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t imeout.3212755262 |
Directory | /workspace/23.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.3000706811 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 20602465 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:47:30 PM PDT 24 |
Finished | Apr 04 03:47:31 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-83d66a9e-3715-4d7d-84f7-e0d25dcca16a |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000706811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.3000706811 |
Directory | /workspace/23.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.1864305607 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 57393711 ps |
CPU time | 0.93 seconds |
Started | Apr 04 03:47:31 PM PDT 24 |
Finished | Apr 04 03:47:32 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-18eccf83-b35d-4bfe-bbf5-21762568aea8 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864305607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.clkmgr_lc_clk_byp_req_intersig_mubi.1864305607 |
Directory | /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.1160851152 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 35483117 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:47:30 PM PDT 24 |
Finished | Apr 04 03:47:31 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-183a24ca-dc87-43c8-bd61-f5f382425056 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160851152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.clkmgr_lc_ctrl_intersig_mubi.1160851152 |
Directory | /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/23.clkmgr_peri.1008166793 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 67527452 ps |
CPU time | 0.91 seconds |
Started | Apr 04 03:47:33 PM PDT 24 |
Finished | Apr 04 03:47:34 PM PDT 24 |
Peak memory | 200364 kb |
Host | smart-d820aa0b-d983-48cb-8813-43bb39d7ada2 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008166793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.1008166793 |
Directory | /workspace/23.clkmgr_peri/latest |
Test location | /workspace/coverage/default/23.clkmgr_regwen.1962680875 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 218049434 ps |
CPU time | 1.36 seconds |
Started | Apr 04 03:47:33 PM PDT 24 |
Finished | Apr 04 03:47:34 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-149d7277-6b7a-44a4-bb1d-55a8955fe8a1 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962680875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.1962680875 |
Directory | /workspace/23.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/23.clkmgr_smoke.3661822242 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 43408917 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:47:34 PM PDT 24 |
Finished | Apr 04 03:47:35 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-0b1008c8-153e-4687-a560-f47d256677d3 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661822242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.3661822242 |
Directory | /workspace/23.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/23.clkmgr_stress_all.1357966593 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 6708977408 ps |
CPU time | 34.06 seconds |
Started | Apr 04 03:47:39 PM PDT 24 |
Finished | Apr 04 03:48:14 PM PDT 24 |
Peak memory | 201032 kb |
Host | smart-ebc745fa-b50c-4943-af3e-a207c307dbec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357966593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.1357966593 |
Directory | /workspace/23.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.3651369755 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 28808955022 ps |
CPU time | 222.61 seconds |
Started | Apr 04 03:47:39 PM PDT 24 |
Finished | Apr 04 03:51:22 PM PDT 24 |
Peak memory | 209308 kb |
Host | smart-cf5022ef-b5e2-4599-9fbc-56f453d090a5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3651369755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.3651369755 |
Directory | /workspace/23.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/23.clkmgr_trans.1117525509 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 24257211 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:47:34 PM PDT 24 |
Finished | Apr 04 03:47:35 PM PDT 24 |
Peak memory | 200496 kb |
Host | smart-356d39cb-aafd-40cf-9210-a2578b2a280a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117525509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.1117525509 |
Directory | /workspace/23.clkmgr_trans/latest |
Test location | /workspace/coverage/default/24.clkmgr_alert_test.3051436244 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 22823754 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:47:50 PM PDT 24 |
Finished | Apr 04 03:47:51 PM PDT 24 |
Peak memory | 200520 kb |
Host | smart-852c1b26-5a56-430b-aa2b-6b99cdd7a4b4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051436244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk mgr_alert_test.3051436244 |
Directory | /workspace/24.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.213954080 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 100766049 ps |
CPU time | 0.99 seconds |
Started | Apr 04 03:47:34 PM PDT 24 |
Finished | Apr 04 03:47:35 PM PDT 24 |
Peak memory | 200584 kb |
Host | smart-53c4a9fe-de06-42c6-b821-18a50b1e8ea9 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213954080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.213954080 |
Directory | /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/24.clkmgr_clk_status.2088980923 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 15338482 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:47:34 PM PDT 24 |
Finished | Apr 04 03:47:35 PM PDT 24 |
Peak memory | 199524 kb |
Host | smart-c95038be-6919-40e6-a2f7-8e1a1ec5305c |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088980923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.2088980923 |
Directory | /workspace/24.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/24.clkmgr_div_intersig_mubi.1376897397 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 21271820 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:47:33 PM PDT 24 |
Finished | Apr 04 03:47:34 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-144c62bf-1841-48ed-901f-7401d898cfb0 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376897397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.1376897397 |
Directory | /workspace/24.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/24.clkmgr_extclk.1696515144 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 55799625 ps |
CPU time | 0.89 seconds |
Started | Apr 04 03:47:34 PM PDT 24 |
Finished | Apr 04 03:47:35 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-5c6fe233-3817-4809-b237-61db84af3a81 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696515144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.1696515144 |
Directory | /workspace/24.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/24.clkmgr_frequency.397843062 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 1037251121 ps |
CPU time | 8.38 seconds |
Started | Apr 04 03:47:35 PM PDT 24 |
Finished | Apr 04 03:47:43 PM PDT 24 |
Peak memory | 200596 kb |
Host | smart-b2a85ba8-e80f-4dbd-ba39-d3397c47b4c4 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397843062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.397843062 |
Directory | /workspace/24.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/24.clkmgr_frequency_timeout.2626388812 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 1705074043 ps |
CPU time | 8.56 seconds |
Started | Apr 04 03:47:30 PM PDT 24 |
Finished | Apr 04 03:47:39 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-2fefd6cb-8f4f-49a5-850e-55a279879460 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626388812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t imeout.2626388812 |
Directory | /workspace/24.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.3894080070 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 16349760 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:47:34 PM PDT 24 |
Finished | Apr 04 03:47:34 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-a60f4b93-972b-4f38-adea-528bf3cc5e0b |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894080070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.3894080070 |
Directory | /workspace/24.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.3104331121 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 18873539 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:47:35 PM PDT 24 |
Finished | Apr 04 03:47:36 PM PDT 24 |
Peak memory | 200560 kb |
Host | smart-07306ade-ebfb-4960-9361-5d327a825a92 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104331121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.clkmgr_lc_clk_byp_req_intersig_mubi.3104331121 |
Directory | /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.2097164234 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 68867331 ps |
CPU time | 1.05 seconds |
Started | Apr 04 03:47:34 PM PDT 24 |
Finished | Apr 04 03:47:35 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-098ed0ae-071d-4730-abf4-e7b1dad08a56 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097164234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.clkmgr_lc_ctrl_intersig_mubi.2097164234 |
Directory | /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/24.clkmgr_peri.1248845120 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 13834101 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:47:32 PM PDT 24 |
Finished | Apr 04 03:47:33 PM PDT 24 |
Peak memory | 200296 kb |
Host | smart-98c0ce69-3937-4e26-86c6-6b85d20233b8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248845120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.1248845120 |
Directory | /workspace/24.clkmgr_peri/latest |
Test location | /workspace/coverage/default/24.clkmgr_regwen.1159426240 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 1192470094 ps |
CPU time | 5.02 seconds |
Started | Apr 04 03:47:34 PM PDT 24 |
Finished | Apr 04 03:47:39 PM PDT 24 |
Peak memory | 200732 kb |
Host | smart-8f5a8c01-e70f-46fd-9a47-9c23dce3d0d8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159426240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.1159426240 |
Directory | /workspace/24.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/24.clkmgr_smoke.147791056 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 135829074 ps |
CPU time | 1.11 seconds |
Started | Apr 04 03:47:35 PM PDT 24 |
Finished | Apr 04 03:47:36 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-8cc3e3c3-966b-40f0-81b4-db1950a88773 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147791056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.147791056 |
Directory | /workspace/24.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/24.clkmgr_stress_all.1456083070 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 13957168420 ps |
CPU time | 49.47 seconds |
Started | Apr 04 03:47:50 PM PDT 24 |
Finished | Apr 04 03:48:40 PM PDT 24 |
Peak memory | 201060 kb |
Host | smart-fae663bd-7fff-4470-a1ba-cbd5eab5f678 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456083070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.1456083070 |
Directory | /workspace/24.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.181867730 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 43993645899 ps |
CPU time | 667.59 seconds |
Started | Apr 04 03:47:49 PM PDT 24 |
Finished | Apr 04 03:58:57 PM PDT 24 |
Peak memory | 211264 kb |
Host | smart-e6e5276b-f0a6-4198-8084-24ac9441ff6d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=181867730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.181867730 |
Directory | /workspace/24.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.clkmgr_trans.350509888 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 31387258 ps |
CPU time | 0.95 seconds |
Started | Apr 04 03:47:33 PM PDT 24 |
Finished | Apr 04 03:47:34 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-183308fd-0464-46f3-bcef-0cbc5d086416 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350509888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.350509888 |
Directory | /workspace/24.clkmgr_trans/latest |
Test location | /workspace/coverage/default/25.clkmgr_alert_test.860273280 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 62129172 ps |
CPU time | 0.91 seconds |
Started | Apr 04 03:47:45 PM PDT 24 |
Finished | Apr 04 03:47:46 PM PDT 24 |
Peak memory | 200496 kb |
Host | smart-b23d72c1-2b15-4819-80a3-43ec3b54492a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860273280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkm gr_alert_test.860273280 |
Directory | /workspace/25.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.3854184411 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 16962838 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:47:50 PM PDT 24 |
Finished | Apr 04 03:47:51 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-b0505789-fe29-4825-b808-02134b9dd489 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854184411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.3854184411 |
Directory | /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/25.clkmgr_clk_status.2100147001 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 12210564 ps |
CPU time | 0.69 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:47:58 PM PDT 24 |
Peak memory | 200332 kb |
Host | smart-a3745aed-8bf8-487d-8dff-bcf4571f9f22 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100147001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.2100147001 |
Directory | /workspace/25.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/25.clkmgr_div_intersig_mubi.2075900550 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 32116480 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:47:55 PM PDT 24 |
Finished | Apr 04 03:47:56 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-f8529131-f60a-4bc3-9443-c594d67fa802 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075900550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.2075900550 |
Directory | /workspace/25.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/25.clkmgr_extclk.685879555 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 85571005 ps |
CPU time | 0.99 seconds |
Started | Apr 04 03:47:46 PM PDT 24 |
Finished | Apr 04 03:47:47 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-8c6b1d61-3f2d-48b3-b918-e1fbac30c88a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685879555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.685879555 |
Directory | /workspace/25.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/25.clkmgr_frequency.2953802865 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 2381817296 ps |
CPU time | 9.97 seconds |
Started | Apr 04 03:47:55 PM PDT 24 |
Finished | Apr 04 03:48:06 PM PDT 24 |
Peak memory | 200860 kb |
Host | smart-ea0dc5eb-25cb-4381-8158-1837934c0455 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953802865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.2953802865 |
Directory | /workspace/25.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/25.clkmgr_frequency_timeout.3150282465 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 2422207961 ps |
CPU time | 16.08 seconds |
Started | Apr 04 03:47:48 PM PDT 24 |
Finished | Apr 04 03:48:04 PM PDT 24 |
Peak memory | 200924 kb |
Host | smart-40e814a9-6069-4afb-a08e-8378c565f7cd |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150282465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t imeout.3150282465 |
Directory | /workspace/25.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.594446995 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 27379416 ps |
CPU time | 0.94 seconds |
Started | Apr 04 03:47:55 PM PDT 24 |
Finished | Apr 04 03:47:56 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-62ba6aee-5726-4981-ac4a-af53eaa65cf3 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594446995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.clkmgr_idle_intersig_mubi.594446995 |
Directory | /workspace/25.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.3334734124 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 21983840 ps |
CPU time | 0.85 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:47:58 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-3a772767-5ddb-4410-9c47-adea66953090 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334734124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_clk_byp_req_intersig_mubi.3334734124 |
Directory | /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.1625080746 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 84993552 ps |
CPU time | 0.97 seconds |
Started | Apr 04 03:47:46 PM PDT 24 |
Finished | Apr 04 03:47:47 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-ab984eb9-6ea4-4e9f-a8c2-7fa01949b01d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625080746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_ctrl_intersig_mubi.1625080746 |
Directory | /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/25.clkmgr_peri.266433392 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 139639278 ps |
CPU time | 1.08 seconds |
Started | Apr 04 03:47:45 PM PDT 24 |
Finished | Apr 04 03:47:46 PM PDT 24 |
Peak memory | 200412 kb |
Host | smart-b0f38a80-8dec-4a20-80b8-07fd534077ba |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266433392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.266433392 |
Directory | /workspace/25.clkmgr_peri/latest |
Test location | /workspace/coverage/default/25.clkmgr_regwen.2050896018 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 1184237794 ps |
CPU time | 4.35 seconds |
Started | Apr 04 03:47:47 PM PDT 24 |
Finished | Apr 04 03:47:51 PM PDT 24 |
Peak memory | 200732 kb |
Host | smart-4681f37a-80b8-44a6-8d4b-ca62a278e928 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050896018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.2050896018 |
Directory | /workspace/25.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/25.clkmgr_smoke.4121055780 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 31769258 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:47:45 PM PDT 24 |
Finished | Apr 04 03:47:46 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-8b287696-dad7-46f2-93e5-39834047ccb0 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121055780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.4121055780 |
Directory | /workspace/25.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/25.clkmgr_stress_all.3227712786 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 7943248932 ps |
CPU time | 32.59 seconds |
Started | Apr 04 03:47:49 PM PDT 24 |
Finished | Apr 04 03:48:22 PM PDT 24 |
Peak memory | 201004 kb |
Host | smart-6507dece-cd1a-49b0-b69c-a1455454d929 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227712786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.3227712786 |
Directory | /workspace/25.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.3006239504 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 193212259412 ps |
CPU time | 985.63 seconds |
Started | Apr 04 03:47:46 PM PDT 24 |
Finished | Apr 04 04:04:12 PM PDT 24 |
Peak memory | 214136 kb |
Host | smart-f6d21cfa-aae4-4411-b3fd-4a3308994edd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3006239504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.3006239504 |
Directory | /workspace/25.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.clkmgr_trans.2124909763 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 17489820 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:47:47 PM PDT 24 |
Finished | Apr 04 03:47:48 PM PDT 24 |
Peak memory | 200516 kb |
Host | smart-8f3a26e6-80af-4228-abbd-d31c0bfc5712 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124909763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.2124909763 |
Directory | /workspace/25.clkmgr_trans/latest |
Test location | /workspace/coverage/default/26.clkmgr_alert_test.2986230869 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 37631768 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:47:58 PM PDT 24 |
Finished | Apr 04 03:47:59 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-ce1d197c-d05d-45da-9f8f-ffe7326aef5b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986230869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk mgr_alert_test.2986230869 |
Directory | /workspace/26.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.2878171599 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 214433941 ps |
CPU time | 1.37 seconds |
Started | Apr 04 03:47:45 PM PDT 24 |
Finished | Apr 04 03:47:46 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-a91a6dc6-f40d-4555-ab94-69a6655bef73 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878171599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.2878171599 |
Directory | /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/26.clkmgr_clk_status.1004564375 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 125883597 ps |
CPU time | 0.97 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:47:58 PM PDT 24 |
Peak memory | 200352 kb |
Host | smart-1be21d75-c82a-4043-8d08-7b096c9553f8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004564375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.1004564375 |
Directory | /workspace/26.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/26.clkmgr_div_intersig_mubi.3710976813 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 13700492 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:47:45 PM PDT 24 |
Finished | Apr 04 03:47:46 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-b13807a0-135a-41f1-8758-e945e8e0dc0a |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710976813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.3710976813 |
Directory | /workspace/26.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/26.clkmgr_extclk.199231850 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 29169086 ps |
CPU time | 0.93 seconds |
Started | Apr 04 03:47:48 PM PDT 24 |
Finished | Apr 04 03:47:49 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-43466d7c-7f03-40bb-b270-8b59d05719e0 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199231850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.199231850 |
Directory | /workspace/26.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/26.clkmgr_frequency.3350274523 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 1044770052 ps |
CPU time | 6.29 seconds |
Started | Apr 04 03:47:48 PM PDT 24 |
Finished | Apr 04 03:47:55 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-34a4b756-7cb1-4f0b-9e89-a52a4751e4d4 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350274523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.3350274523 |
Directory | /workspace/26.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/26.clkmgr_frequency_timeout.4039451407 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 271043651 ps |
CPU time | 1.67 seconds |
Started | Apr 04 03:47:46 PM PDT 24 |
Finished | Apr 04 03:47:47 PM PDT 24 |
Peak memory | 200728 kb |
Host | smart-f2f18225-0383-4e03-a085-a0d1eacd03d1 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039451407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t imeout.4039451407 |
Directory | /workspace/26.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.2823448784 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 25679400 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:47:50 PM PDT 24 |
Finished | Apr 04 03:47:50 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-d12542d6-a2d1-4cf6-9f1f-24639d37b6e3 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823448784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_idle_intersig_mubi.2823448784 |
Directory | /workspace/26.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.2642430573 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 185541015 ps |
CPU time | 1.23 seconds |
Started | Apr 04 03:47:46 PM PDT 24 |
Finished | Apr 04 03:47:47 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-b17236b9-4dba-4108-99c5-d681341af456 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642430573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 26.clkmgr_lc_clk_byp_req_intersig_mubi.2642430573 |
Directory | /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.31217406 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 24010269 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:47:48 PM PDT 24 |
Finished | Apr 04 03:47:49 PM PDT 24 |
Peak memory | 200564 kb |
Host | smart-c93755a7-c540-4923-a9e9-853de5f8a199 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31217406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_ctrl_intersig_mubi.31217406 |
Directory | /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/26.clkmgr_peri.1063076476 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 38484130 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:47:46 PM PDT 24 |
Finished | Apr 04 03:47:46 PM PDT 24 |
Peak memory | 200316 kb |
Host | smart-524eeda5-6f3c-4def-ae6e-612afb873f14 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063076476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.1063076476 |
Directory | /workspace/26.clkmgr_peri/latest |
Test location | /workspace/coverage/default/26.clkmgr_regwen.2511114965 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 650832566 ps |
CPU time | 3.89 seconds |
Started | Apr 04 03:47:45 PM PDT 24 |
Finished | Apr 04 03:47:49 PM PDT 24 |
Peak memory | 200796 kb |
Host | smart-e81f739d-02d3-40ca-8922-a3a7ac426287 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511114965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.2511114965 |
Directory | /workspace/26.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/26.clkmgr_smoke.4019251604 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 61597858 ps |
CPU time | 0.9 seconds |
Started | Apr 04 03:47:45 PM PDT 24 |
Finished | Apr 04 03:47:46 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-58f6ac84-8338-4e02-99c9-38046644b441 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019251604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.4019251604 |
Directory | /workspace/26.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/26.clkmgr_stress_all.2708588108 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 1779257171 ps |
CPU time | 13.24 seconds |
Started | Apr 04 03:47:47 PM PDT 24 |
Finished | Apr 04 03:48:00 PM PDT 24 |
Peak memory | 200848 kb |
Host | smart-d6853123-60a5-4170-bca0-d419499e3420 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708588108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.2708588108 |
Directory | /workspace/26.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/26.clkmgr_trans.3795125562 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 44857361 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:47:46 PM PDT 24 |
Finished | Apr 04 03:47:47 PM PDT 24 |
Peak memory | 200428 kb |
Host | smart-117697e6-1876-47f4-92de-decd7bd8f041 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795125562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.3795125562 |
Directory | /workspace/26.clkmgr_trans/latest |
Test location | /workspace/coverage/default/27.clkmgr_alert_test.3469367253 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 36767532 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:48:10 PM PDT 24 |
Finished | Apr 04 03:48:11 PM PDT 24 |
Peak memory | 200492 kb |
Host | smart-858eb860-6584-49e3-ad36-84e6cf51f8b5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469367253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk mgr_alert_test.3469367253 |
Directory | /workspace/27.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1530421002 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 51652130 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:47:58 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-c6fafc26-f78c-42a7-97ad-2aaaf152d4b0 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530421002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.1530421002 |
Directory | /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/27.clkmgr_clk_status.2375063485 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 42963771 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:47:48 PM PDT 24 |
Finished | Apr 04 03:47:49 PM PDT 24 |
Peak memory | 200360 kb |
Host | smart-5cfd12a4-03f6-4d65-a7c0-4129c2565cf3 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375063485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.2375063485 |
Directory | /workspace/27.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/27.clkmgr_div_intersig_mubi.3750274022 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 24394180 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:47:58 PM PDT 24 |
Finished | Apr 04 03:47:59 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-4234fe59-c568-4bfd-b966-94a5795a45cc |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750274022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.3750274022 |
Directory | /workspace/27.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/27.clkmgr_extclk.3389591151 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 14632906 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:47:49 PM PDT 24 |
Finished | Apr 04 03:47:50 PM PDT 24 |
Peak memory | 200596 kb |
Host | smart-1014f893-081a-4543-b2d3-9a362aa14018 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389591151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.3389591151 |
Directory | /workspace/27.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/27.clkmgr_frequency.1086341885 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 2021641504 ps |
CPU time | 8.78 seconds |
Started | Apr 04 03:47:46 PM PDT 24 |
Finished | Apr 04 03:47:55 PM PDT 24 |
Peak memory | 200864 kb |
Host | smart-0491bc53-3e66-4b03-a64f-ba0cff6ec744 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086341885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.1086341885 |
Directory | /workspace/27.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/27.clkmgr_frequency_timeout.995041257 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 1151675154 ps |
CPU time | 4.7 seconds |
Started | Apr 04 03:47:56 PM PDT 24 |
Finished | Apr 04 03:48:01 PM PDT 24 |
Peak memory | 200692 kb |
Host | smart-eff70f80-351d-4cb3-bb29-ea1e3cf2895c |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995041257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_ti meout.995041257 |
Directory | /workspace/27.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.3823618614 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 186029123 ps |
CPU time | 1.37 seconds |
Started | Apr 04 03:47:47 PM PDT 24 |
Finished | Apr 04 03:47:48 PM PDT 24 |
Peak memory | 200584 kb |
Host | smart-34ca37a5-4414-4cd3-9983-04cd5ee59148 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823618614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.3823618614 |
Directory | /workspace/27.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.3950768026 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 21586897 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:47:48 PM PDT 24 |
Finished | Apr 04 03:47:49 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-4e529d26-3182-4d8c-8678-c7d308b6c9ce |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950768026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.clkmgr_lc_clk_byp_req_intersig_mubi.3950768026 |
Directory | /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.1763084744 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 121504088 ps |
CPU time | 1.06 seconds |
Started | Apr 04 03:47:48 PM PDT 24 |
Finished | Apr 04 03:47:49 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-f13cb741-ce51-498e-817a-0740a36045c9 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763084744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.clkmgr_lc_ctrl_intersig_mubi.1763084744 |
Directory | /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/27.clkmgr_peri.3045008151 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 34565256 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:47:49 PM PDT 24 |
Finished | Apr 04 03:47:50 PM PDT 24 |
Peak memory | 200312 kb |
Host | smart-8ce31bc3-c039-4f57-a4be-7d45c60ad871 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045008151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.3045008151 |
Directory | /workspace/27.clkmgr_peri/latest |
Test location | /workspace/coverage/default/27.clkmgr_regwen.681502756 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 1374125800 ps |
CPU time | 5.04 seconds |
Started | Apr 04 03:48:02 PM PDT 24 |
Finished | Apr 04 03:48:07 PM PDT 24 |
Peak memory | 200756 kb |
Host | smart-84245972-4f38-43c5-9810-82c6d43488d3 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681502756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.681502756 |
Directory | /workspace/27.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/27.clkmgr_smoke.4007844561 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 70749163 ps |
CPU time | 0.95 seconds |
Started | Apr 04 03:47:44 PM PDT 24 |
Finished | Apr 04 03:47:45 PM PDT 24 |
Peak memory | 200680 kb |
Host | smart-10b3ca3b-0ec6-43d6-a6e9-ab7eb35e4ed9 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007844561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.4007844561 |
Directory | /workspace/27.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/27.clkmgr_stress_all.860628029 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 8506969453 ps |
CPU time | 28.37 seconds |
Started | Apr 04 03:48:01 PM PDT 24 |
Finished | Apr 04 03:48:29 PM PDT 24 |
Peak memory | 200996 kb |
Host | smart-afee9bf5-bbea-4af4-b39e-f6c980c01c92 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860628029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.860628029 |
Directory | /workspace/27.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.1108785758 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 12518330090 ps |
CPU time | 167.8 seconds |
Started | Apr 04 03:47:56 PM PDT 24 |
Finished | Apr 04 03:50:44 PM PDT 24 |
Peak memory | 209252 kb |
Host | smart-615b5cb4-16a7-4217-9ba2-769f465e4c8a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1108785758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.1108785758 |
Directory | /workspace/27.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.clkmgr_trans.1852955486 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 156157486 ps |
CPU time | 1.28 seconds |
Started | Apr 04 03:47:48 PM PDT 24 |
Finished | Apr 04 03:47:49 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-894a48a9-a84a-46e7-9f22-a63f8c2a956a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852955486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.1852955486 |
Directory | /workspace/27.clkmgr_trans/latest |
Test location | /workspace/coverage/default/28.clkmgr_alert_test.3652607360 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 32576806 ps |
CPU time | 0.85 seconds |
Started | Apr 04 03:47:56 PM PDT 24 |
Finished | Apr 04 03:47:57 PM PDT 24 |
Peak memory | 200508 kb |
Host | smart-a69ddc1e-4e59-4f43-bd94-94aded22401e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652607360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk mgr_alert_test.3652607360 |
Directory | /workspace/28.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.3784783430 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 18311898 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:47:58 PM PDT 24 |
Finished | Apr 04 03:47:59 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-9cfbd30b-d4d5-464d-9163-dbbd3f067c9b |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784783430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.3784783430 |
Directory | /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/28.clkmgr_clk_status.1423445679 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 15357805 ps |
CPU time | 0.69 seconds |
Started | Apr 04 03:47:59 PM PDT 24 |
Finished | Apr 04 03:48:00 PM PDT 24 |
Peak memory | 199592 kb |
Host | smart-d0d4ac8b-ad47-4a4c-af67-03d556596fb3 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423445679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.1423445679 |
Directory | /workspace/28.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/28.clkmgr_div_intersig_mubi.13460208 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 18180774 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:47:58 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-892e1bad-35eb-4eb0-97de-916b5332e988 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13460208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28 .clkmgr_div_intersig_mubi.13460208 |
Directory | /workspace/28.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/28.clkmgr_extclk.868038357 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 35048083 ps |
CPU time | 0.85 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:47:58 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-d0601dec-469e-4394-9d12-5770d7013a8d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868038357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.868038357 |
Directory | /workspace/28.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/28.clkmgr_frequency.3903290009 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 2366982090 ps |
CPU time | 12.3 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:48:09 PM PDT 24 |
Peak memory | 200832 kb |
Host | smart-cfd17001-d3bb-4944-93d1-4eb942027298 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903290009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.3903290009 |
Directory | /workspace/28.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/28.clkmgr_frequency_timeout.3752956776 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 1782397292 ps |
CPU time | 7.32 seconds |
Started | Apr 04 03:47:56 PM PDT 24 |
Finished | Apr 04 03:48:03 PM PDT 24 |
Peak memory | 200696 kb |
Host | smart-3b60cfd2-5004-46f5-912d-3292c0e70291 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752956776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t imeout.3752956776 |
Directory | /workspace/28.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.57011548 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 32868892 ps |
CPU time | 0.98 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:47:58 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-4aa75906-788d-4e04-a2e7-96383ff0bc59 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57011548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28 .clkmgr_idle_intersig_mubi.57011548 |
Directory | /workspace/28.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.2479530218 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 253027043 ps |
CPU time | 1.47 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:47:59 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-3bbce3c7-ecb0-4bfe-9902-6c263a069f5d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479530218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.clkmgr_lc_clk_byp_req_intersig_mubi.2479530218 |
Directory | /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.4126265709 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 120908140 ps |
CPU time | 1.07 seconds |
Started | Apr 04 03:47:58 PM PDT 24 |
Finished | Apr 04 03:47:59 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-5597ef04-6693-4a3a-b9d8-12ccfcf14a99 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126265709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.clkmgr_lc_ctrl_intersig_mubi.4126265709 |
Directory | /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/28.clkmgr_peri.3500844121 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 24499186 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:48:00 PM PDT 24 |
Finished | Apr 04 03:48:00 PM PDT 24 |
Peak memory | 200384 kb |
Host | smart-2def560e-94a8-4c89-ae14-1f908a5580dc |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500844121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.3500844121 |
Directory | /workspace/28.clkmgr_peri/latest |
Test location | /workspace/coverage/default/28.clkmgr_regwen.1328492430 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 1263104137 ps |
CPU time | 5.8 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:48:03 PM PDT 24 |
Peak memory | 200756 kb |
Host | smart-8098d484-e0d1-4c6d-9f7e-fc3b0703e7b5 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328492430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.1328492430 |
Directory | /workspace/28.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/28.clkmgr_smoke.925816120 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 24732885 ps |
CPU time | 0.85 seconds |
Started | Apr 04 03:48:05 PM PDT 24 |
Finished | Apr 04 03:48:06 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-2db3390c-cea2-4758-b467-3694c6d0be79 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925816120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.925816120 |
Directory | /workspace/28.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/28.clkmgr_stress_all.366362143 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 3027741553 ps |
CPU time | 16.36 seconds |
Started | Apr 04 03:47:58 PM PDT 24 |
Finished | Apr 04 03:48:14 PM PDT 24 |
Peak memory | 200856 kb |
Host | smart-7f3a6add-9b26-4c38-b2e6-0d162c41de8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366362143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.366362143 |
Directory | /workspace/28.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.2775206075 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 145633881370 ps |
CPU time | 841.59 seconds |
Started | Apr 04 03:47:56 PM PDT 24 |
Finished | Apr 04 04:01:58 PM PDT 24 |
Peak memory | 209272 kb |
Host | smart-eaaedc32-adda-4a08-b524-d5735d8e3104 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2775206075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.2775206075 |
Directory | /workspace/28.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.clkmgr_trans.972427082 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 123122227 ps |
CPU time | 1.27 seconds |
Started | Apr 04 03:47:58 PM PDT 24 |
Finished | Apr 04 03:47:59 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-8f3acb87-f6aa-4b16-ab44-ec894a088acd |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972427082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.972427082 |
Directory | /workspace/28.clkmgr_trans/latest |
Test location | /workspace/coverage/default/29.clkmgr_alert_test.2065858005 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 26561139 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:47:56 PM PDT 24 |
Finished | Apr 04 03:47:56 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-d9ee1310-5016-464c-8adc-9f7cd89ef3bb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065858005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk mgr_alert_test.2065858005 |
Directory | /workspace/29.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.4017993208 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 75930878 ps |
CPU time | 0.97 seconds |
Started | Apr 04 03:48:00 PM PDT 24 |
Finished | Apr 04 03:48:01 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-57ffce52-6b7a-475f-a503-99c652d423b5 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017993208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.4017993208 |
Directory | /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/29.clkmgr_clk_status.3565539028 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 42246376 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:47:58 PM PDT 24 |
Peak memory | 199592 kb |
Host | smart-ed47af3c-f54e-488c-9e5e-c8068f01cfb1 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565539028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.3565539028 |
Directory | /workspace/29.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/29.clkmgr_div_intersig_mubi.3961599069 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 34179792 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:48:18 PM PDT 24 |
Finished | Apr 04 03:48:20 PM PDT 24 |
Peak memory | 200120 kb |
Host | smart-c9795730-c30a-42f7-9b43-73884691f43f |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961599069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.3961599069 |
Directory | /workspace/29.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/29.clkmgr_extclk.2545740334 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 24831969 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:47:58 PM PDT 24 |
Peak memory | 200580 kb |
Host | smart-67217111-4aac-4e49-9da3-c343b0106217 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545740334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.2545740334 |
Directory | /workspace/29.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/29.clkmgr_frequency.1301859299 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 1885822226 ps |
CPU time | 10.16 seconds |
Started | Apr 04 03:47:56 PM PDT 24 |
Finished | Apr 04 03:48:07 PM PDT 24 |
Peak memory | 200868 kb |
Host | smart-cab857f0-c3e0-4ae1-ab86-b37a0545c938 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301859299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.1301859299 |
Directory | /workspace/29.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/29.clkmgr_frequency_timeout.4031122880 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 861818603 ps |
CPU time | 5.44 seconds |
Started | Apr 04 03:47:56 PM PDT 24 |
Finished | Apr 04 03:48:01 PM PDT 24 |
Peak memory | 200712 kb |
Host | smart-2713c1f2-1134-4acf-b782-0c9b6f5603b8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031122880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t imeout.4031122880 |
Directory | /workspace/29.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.3943200298 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 52663931 ps |
CPU time | 1.01 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:47:59 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-96f01dee-f08b-43d6-9d9a-ecda9f0b29e2 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943200298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.3943200298 |
Directory | /workspace/29.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1699011285 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 18927826 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:48:00 PM PDT 24 |
Finished | Apr 04 03:48:00 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-39d6a93c-e378-42b1-bd74-171e3d11956e |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699011285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_clk_byp_req_intersig_mubi.1699011285 |
Directory | /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.2259043775 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 55604790 ps |
CPU time | 0.89 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:47:58 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-90a042d8-efcd-4048-a9b1-2d2733db023a |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259043775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_ctrl_intersig_mubi.2259043775 |
Directory | /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/29.clkmgr_peri.3492826979 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 153773501 ps |
CPU time | 1.1 seconds |
Started | Apr 04 03:48:19 PM PDT 24 |
Finished | Apr 04 03:48:21 PM PDT 24 |
Peak memory | 200364 kb |
Host | smart-f2c6e019-3b70-4d4c-b4aa-c5dfdd1c0d8e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492826979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.3492826979 |
Directory | /workspace/29.clkmgr_peri/latest |
Test location | /workspace/coverage/default/29.clkmgr_regwen.965511274 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 579838309 ps |
CPU time | 2.45 seconds |
Started | Apr 04 03:48:11 PM PDT 24 |
Finished | Apr 04 03:48:14 PM PDT 24 |
Peak memory | 200740 kb |
Host | smart-1233719f-5e6d-471c-8803-acdbe5f6ab27 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965511274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.965511274 |
Directory | /workspace/29.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/29.clkmgr_smoke.2586555358 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 16548339 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:48:10 PM PDT 24 |
Finished | Apr 04 03:48:11 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-2d0bfe84-31e1-4473-8228-f6cf77622e48 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586555358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.2586555358 |
Directory | /workspace/29.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/29.clkmgr_stress_all.22512982 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 2068517496 ps |
CPU time | 6.65 seconds |
Started | Apr 04 03:47:58 PM PDT 24 |
Finished | Apr 04 03:48:05 PM PDT 24 |
Peak memory | 200728 kb |
Host | smart-490e6790-187e-4676-94e0-c0e95a48f32b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22512982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_ TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.clkmgr_stress_all.22512982 |
Directory | /workspace/29.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.1310385107 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 16700803145 ps |
CPU time | 251.19 seconds |
Started | Apr 04 03:48:11 PM PDT 24 |
Finished | Apr 04 03:52:22 PM PDT 24 |
Peak memory | 209248 kb |
Host | smart-a94bf3ec-3799-4f33-924b-45f14179d4f6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1310385107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.1310385107 |
Directory | /workspace/29.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.clkmgr_trans.2692830435 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 23445718 ps |
CPU time | 0.85 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:47:58 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-64a91e78-dfc4-4cc2-9ce8-1a90b895e11e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692830435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.2692830435 |
Directory | /workspace/29.clkmgr_trans/latest |
Test location | /workspace/coverage/default/3.clkmgr_alert_test.2887616746 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 13222098 ps |
CPU time | 0.7 seconds |
Started | Apr 04 03:46:24 PM PDT 24 |
Finished | Apr 04 03:46:25 PM PDT 24 |
Peak memory | 200424 kb |
Host | smart-0c6495ef-df1b-4cdd-b7d0-fad3c397d862 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887616746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm gr_alert_test.2887616746 |
Directory | /workspace/3.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.2563310162 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 269168490 ps |
CPU time | 1.52 seconds |
Started | Apr 04 03:46:27 PM PDT 24 |
Finished | Apr 04 03:46:29 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-537886a0-7961-410f-a38f-9719be96d99d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563310162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.2563310162 |
Directory | /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/3.clkmgr_clk_status.2900182237 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 13710884 ps |
CPU time | 0.71 seconds |
Started | Apr 04 03:46:27 PM PDT 24 |
Finished | Apr 04 03:46:28 PM PDT 24 |
Peak memory | 200264 kb |
Host | smart-b7f8de41-381a-4753-8608-cf64da4f3a5f |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900182237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2900182237 |
Directory | /workspace/3.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/3.clkmgr_div_intersig_mubi.1484115492 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 16999401 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:46:27 PM PDT 24 |
Finished | Apr 04 03:46:28 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-e2ac52ea-e745-4a4e-8eec-9b58a02940e4 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484115492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.1484115492 |
Directory | /workspace/3.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/3.clkmgr_extclk.46352554 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 23962669 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:46:26 PM PDT 24 |
Finished | Apr 04 03:46:26 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-fa26d145-5b34-4836-ae38-216e22dc99ae |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46352554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.46352554 |
Directory | /workspace/3.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/3.clkmgr_frequency.2563320239 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 1332081838 ps |
CPU time | 6.11 seconds |
Started | Apr 04 03:46:25 PM PDT 24 |
Finished | Apr 04 03:46:31 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-d4a6c5a1-9226-48ca-99a0-a2d4e5cff14c |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563320239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.2563320239 |
Directory | /workspace/3.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/3.clkmgr_frequency_timeout.1380461112 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 1717013151 ps |
CPU time | 7.34 seconds |
Started | Apr 04 03:46:27 PM PDT 24 |
Finished | Apr 04 03:46:34 PM PDT 24 |
Peak memory | 200696 kb |
Host | smart-9e8d0d81-1360-41c6-8849-5a9e481c1b18 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380461112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti meout.1380461112 |
Directory | /workspace/3.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.3116977821 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 102245146 ps |
CPU time | 1.18 seconds |
Started | Apr 04 03:46:26 PM PDT 24 |
Finished | Apr 04 03:46:27 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-45b87bfc-c93f-4ad3-a284-83a7e5131542 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116977821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.3116977821 |
Directory | /workspace/3.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.1482987789 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 38977715 ps |
CPU time | 0.9 seconds |
Started | Apr 04 03:46:29 PM PDT 24 |
Finished | Apr 04 03:46:30 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-e6ac3f0a-7afd-4b3b-9c48-8455b5d0ad05 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482987789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.clkmgr_lc_clk_byp_req_intersig_mubi.1482987789 |
Directory | /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.1863130279 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 24791341 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:46:25 PM PDT 24 |
Finished | Apr 04 03:46:26 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-9bfb8b2d-4516-4c44-b663-3553c9713db2 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863130279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.clkmgr_lc_ctrl_intersig_mubi.1863130279 |
Directory | /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/3.clkmgr_peri.1089227176 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 15550577 ps |
CPU time | 0.68 seconds |
Started | Apr 04 03:46:25 PM PDT 24 |
Finished | Apr 04 03:46:26 PM PDT 24 |
Peak memory | 200388 kb |
Host | smart-ca7fde62-908d-4327-a1e8-8de9dec36a9b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089227176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.1089227176 |
Directory | /workspace/3.clkmgr_peri/latest |
Test location | /workspace/coverage/default/3.clkmgr_regwen.2914401563 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 423996163 ps |
CPU time | 2.41 seconds |
Started | Apr 04 03:46:29 PM PDT 24 |
Finished | Apr 04 03:46:31 PM PDT 24 |
Peak memory | 200816 kb |
Host | smart-1d53b3d3-6b4b-41b2-804b-c302a7b6e351 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914401563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.2914401563 |
Directory | /workspace/3.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/3.clkmgr_sec_cm.2491997800 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 552249489 ps |
CPU time | 3.41 seconds |
Started | Apr 04 03:46:26 PM PDT 24 |
Finished | Apr 04 03:46:29 PM PDT 24 |
Peak memory | 217320 kb |
Host | smart-a3bfce20-f9a8-418f-a99e-9a6c91b93707 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491997800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg r_sec_cm.2491997800 |
Directory | /workspace/3.clkmgr_sec_cm/latest |
Test location | /workspace/coverage/default/3.clkmgr_smoke.2964704756 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 39674886 ps |
CPU time | 0.91 seconds |
Started | Apr 04 03:46:26 PM PDT 24 |
Finished | Apr 04 03:46:27 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-0eca333a-f970-42d8-9154-d387fb44986a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964704756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.2964704756 |
Directory | /workspace/3.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/3.clkmgr_stress_all.812362411 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 6921537169 ps |
CPU time | 50.74 seconds |
Started | Apr 04 03:46:31 PM PDT 24 |
Finished | Apr 04 03:47:22 PM PDT 24 |
Peak memory | 200968 kb |
Host | smart-6b09b710-0d54-42bd-9f1b-f2088b693eff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812362411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.812362411 |
Directory | /workspace/3.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.2396070543 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 94535004630 ps |
CPU time | 826.67 seconds |
Started | Apr 04 03:46:29 PM PDT 24 |
Finished | Apr 04 04:00:16 PM PDT 24 |
Peak memory | 217400 kb |
Host | smart-eaef67c5-67f3-4ce2-a991-28cd2f4fbb4e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2396070543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.2396070543 |
Directory | /workspace/3.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/3.clkmgr_trans.3696903934 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 42902659 ps |
CPU time | 0.93 seconds |
Started | Apr 04 03:46:32 PM PDT 24 |
Finished | Apr 04 03:46:33 PM PDT 24 |
Peak memory | 200584 kb |
Host | smart-9cd9066f-d998-4d47-a466-3611084d94b8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696903934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.3696903934 |
Directory | /workspace/3.clkmgr_trans/latest |
Test location | /workspace/coverage/default/30.clkmgr_alert_test.3855962370 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 20778804 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:48:14 PM PDT 24 |
Finished | Apr 04 03:48:15 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-6a34b013-f764-4a9f-a681-cd52ebc9da6d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855962370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk mgr_alert_test.3855962370 |
Directory | /workspace/30.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.1544718045 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 217154746 ps |
CPU time | 1.45 seconds |
Started | Apr 04 03:48:11 PM PDT 24 |
Finished | Apr 04 03:48:13 PM PDT 24 |
Peak memory | 200588 kb |
Host | smart-bb57b63d-802a-4bda-bf94-036a1c7d73f3 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544718045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.1544718045 |
Directory | /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/30.clkmgr_clk_status.2806029044 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 40389537 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:47:58 PM PDT 24 |
Finished | Apr 04 03:47:59 PM PDT 24 |
Peak memory | 200328 kb |
Host | smart-2acfaeaa-f9cf-498a-b112-7db20d337b80 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806029044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.2806029044 |
Directory | /workspace/30.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/30.clkmgr_div_intersig_mubi.3881171984 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 17424948 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:48:14 PM PDT 24 |
Finished | Apr 04 03:48:16 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-b0e0cdae-667a-4535-9954-1a1333838790 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881171984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.3881171984 |
Directory | /workspace/30.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/30.clkmgr_extclk.1252984986 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 24672236 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:47:58 PM PDT 24 |
Finished | Apr 04 03:47:59 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-f5aeab27-f63c-4d77-b370-162e4a810c23 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252984986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.1252984986 |
Directory | /workspace/30.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/30.clkmgr_frequency.1613172003 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 1170568821 ps |
CPU time | 5.3 seconds |
Started | Apr 04 03:47:57 PM PDT 24 |
Finished | Apr 04 03:48:02 PM PDT 24 |
Peak memory | 200612 kb |
Host | smart-3c3dae57-f3d8-44eb-8c5b-cb042f649ac1 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613172003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.1613172003 |
Directory | /workspace/30.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/30.clkmgr_frequency_timeout.3118244816 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 2414403907 ps |
CPU time | 16.24 seconds |
Started | Apr 04 03:47:55 PM PDT 24 |
Finished | Apr 04 03:48:11 PM PDT 24 |
Peak memory | 200928 kb |
Host | smart-6564c777-648c-4c7c-8987-52941def02b3 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118244816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t imeout.3118244816 |
Directory | /workspace/30.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.660189339 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 26640404 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:47:58 PM PDT 24 |
Finished | Apr 04 03:47:59 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-6d41a363-4352-4123-958c-e5afeb59f49a |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660189339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.clkmgr_idle_intersig_mubi.660189339 |
Directory | /workspace/30.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.2926815943 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 44868235 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:47:58 PM PDT 24 |
Finished | Apr 04 03:47:59 PM PDT 24 |
Peak memory | 200592 kb |
Host | smart-693378d4-a290-4016-a3dc-14a77ae5a4bc |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926815943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 30.clkmgr_lc_clk_byp_req_intersig_mubi.2926815943 |
Directory | /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.1175286083 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 16975290 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:48:20 PM PDT 24 |
Finished | Apr 04 03:48:21 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-d4446d0e-53a3-4f90-817f-115f0490fd90 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175286083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 30.clkmgr_lc_ctrl_intersig_mubi.1175286083 |
Directory | /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/30.clkmgr_peri.1342754786 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 32433668 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:48:11 PM PDT 24 |
Finished | Apr 04 03:48:13 PM PDT 24 |
Peak memory | 200352 kb |
Host | smart-351d988d-9e55-40bf-a6db-407a170f8a86 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342754786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.1342754786 |
Directory | /workspace/30.clkmgr_peri/latest |
Test location | /workspace/coverage/default/30.clkmgr_regwen.1986917404 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 949492587 ps |
CPU time | 5.26 seconds |
Started | Apr 04 03:48:13 PM PDT 24 |
Finished | Apr 04 03:48:18 PM PDT 24 |
Peak memory | 200752 kb |
Host | smart-efbc0f39-1adc-4e4c-8c5a-7df91b14dd31 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986917404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.1986917404 |
Directory | /workspace/30.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/30.clkmgr_smoke.4237337729 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 21803921 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:47:58 PM PDT 24 |
Finished | Apr 04 03:47:59 PM PDT 24 |
Peak memory | 200680 kb |
Host | smart-310484b9-2863-4d79-8238-195a699f94e4 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237337729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.4237337729 |
Directory | /workspace/30.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/30.clkmgr_stress_all.821617075 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 6834826973 ps |
CPU time | 46.41 seconds |
Started | Apr 04 03:48:08 PM PDT 24 |
Finished | Apr 04 03:48:55 PM PDT 24 |
Peak memory | 200900 kb |
Host | smart-a30779d9-7c32-4c55-92b6-6080cf8b12d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821617075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.821617075 |
Directory | /workspace/30.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.3432553601 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 17789011769 ps |
CPU time | 147.71 seconds |
Started | Apr 04 03:48:11 PM PDT 24 |
Finished | Apr 04 03:50:39 PM PDT 24 |
Peak memory | 209268 kb |
Host | smart-23affb19-1dfd-43e8-8489-320d4f9d9cbe |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3432553601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.3432553601 |
Directory | /workspace/30.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.clkmgr_trans.1292287153 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 100392538 ps |
CPU time | 1.08 seconds |
Started | Apr 04 03:48:11 PM PDT 24 |
Finished | Apr 04 03:48:12 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-dc7f50d6-5ecd-4e94-985d-618c1fc9a66b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292287153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.1292287153 |
Directory | /workspace/30.clkmgr_trans/latest |
Test location | /workspace/coverage/default/31.clkmgr_alert_test.4064133289 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 16124104 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:48:09 PM PDT 24 |
Finished | Apr 04 03:48:10 PM PDT 24 |
Peak memory | 200528 kb |
Host | smart-090b8de0-0f84-461e-8ead-a517d62df7ae |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064133289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk mgr_alert_test.4064133289 |
Directory | /workspace/31.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.1116601340 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 73620791 ps |
CPU time | 1 seconds |
Started | Apr 04 03:48:09 PM PDT 24 |
Finished | Apr 04 03:48:10 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-018e5d17-010d-49bc-87ce-4cb2123b1ffb |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116601340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.1116601340 |
Directory | /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/31.clkmgr_clk_status.3863012087 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 34974359 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:48:11 PM PDT 24 |
Finished | Apr 04 03:48:12 PM PDT 24 |
Peak memory | 200328 kb |
Host | smart-9313e013-6bb6-4054-94ef-bc92d884162d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863012087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.3863012087 |
Directory | /workspace/31.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/31.clkmgr_div_intersig_mubi.3749484988 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 28643856 ps |
CPU time | 0.88 seconds |
Started | Apr 04 03:48:20 PM PDT 24 |
Finished | Apr 04 03:48:21 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-8623ef40-8782-4dff-8214-61aeb0f92471 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749484988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.3749484988 |
Directory | /workspace/31.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/31.clkmgr_extclk.2741942741 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 40097299 ps |
CPU time | 0.96 seconds |
Started | Apr 04 03:48:07 PM PDT 24 |
Finished | Apr 04 03:48:08 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-318d962c-982d-4fb7-9be3-5095960f49ae |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741942741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.2741942741 |
Directory | /workspace/31.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/31.clkmgr_frequency.1927872490 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 1994965040 ps |
CPU time | 15.25 seconds |
Started | Apr 04 03:48:13 PM PDT 24 |
Finished | Apr 04 03:48:29 PM PDT 24 |
Peak memory | 200796 kb |
Host | smart-723dcc70-e7dc-40e2-85af-0132fb204397 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927872490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.1927872490 |
Directory | /workspace/31.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/31.clkmgr_frequency_timeout.3416118096 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 2314960388 ps |
CPU time | 9.2 seconds |
Started | Apr 04 03:48:16 PM PDT 24 |
Finished | Apr 04 03:48:26 PM PDT 24 |
Peak memory | 200912 kb |
Host | smart-fe549043-0906-4726-b1c5-6ce25e27e5db |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416118096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t imeout.3416118096 |
Directory | /workspace/31.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.3037069260 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 200975258 ps |
CPU time | 1.47 seconds |
Started | Apr 04 03:48:13 PM PDT 24 |
Finished | Apr 04 03:48:16 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-d3269524-0515-4b38-a120-729c42fbb9cd |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037069260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.3037069260 |
Directory | /workspace/31.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.3309136062 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 126822252 ps |
CPU time | 1.01 seconds |
Started | Apr 04 03:48:16 PM PDT 24 |
Finished | Apr 04 03:48:18 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-ded8c2a6-5b1d-40b5-8a39-558c71562fb2 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309136062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 31.clkmgr_lc_clk_byp_req_intersig_mubi.3309136062 |
Directory | /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.1838812285 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 17144363 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:48:12 PM PDT 24 |
Finished | Apr 04 03:48:13 PM PDT 24 |
Peak memory | 200548 kb |
Host | smart-78b14ece-a663-4de8-ac34-0395c643cabb |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838812285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 31.clkmgr_lc_ctrl_intersig_mubi.1838812285 |
Directory | /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/31.clkmgr_peri.2283079863 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 108315126 ps |
CPU time | 0.98 seconds |
Started | Apr 04 03:48:12 PM PDT 24 |
Finished | Apr 04 03:48:13 PM PDT 24 |
Peak memory | 200324 kb |
Host | smart-c97adc97-467b-4034-8e4b-85c8ce726473 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283079863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.2283079863 |
Directory | /workspace/31.clkmgr_peri/latest |
Test location | /workspace/coverage/default/31.clkmgr_regwen.3407558481 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 386700964 ps |
CPU time | 2.2 seconds |
Started | Apr 04 03:48:13 PM PDT 24 |
Finished | Apr 04 03:48:15 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-205752da-7f97-4320-9369-c3d42eb1fc1b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407558481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.3407558481 |
Directory | /workspace/31.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/31.clkmgr_smoke.1847311957 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 100106570 ps |
CPU time | 1.09 seconds |
Started | Apr 04 03:48:12 PM PDT 24 |
Finished | Apr 04 03:48:13 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-8088857e-26e7-40d6-ae70-ef8deeacc357 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847311957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.1847311957 |
Directory | /workspace/31.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/31.clkmgr_stress_all.3096291958 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 1918166031 ps |
CPU time | 14.31 seconds |
Started | Apr 04 03:48:14 PM PDT 24 |
Finished | Apr 04 03:48:29 PM PDT 24 |
Peak memory | 200864 kb |
Host | smart-95e62260-a2e7-4f00-b466-165947667344 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096291958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.3096291958 |
Directory | /workspace/31.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.2386980244 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 36045375973 ps |
CPU time | 508.9 seconds |
Started | Apr 04 03:48:11 PM PDT 24 |
Finished | Apr 04 03:56:40 PM PDT 24 |
Peak memory | 209424 kb |
Host | smart-2fd1ada5-b430-422b-bf02-29909708fc74 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2386980244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.2386980244 |
Directory | /workspace/31.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.clkmgr_trans.144051170 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 26128507 ps |
CPU time | 0.93 seconds |
Started | Apr 04 03:48:13 PM PDT 24 |
Finished | Apr 04 03:48:14 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-c3e90e01-a8ed-4fad-b5a8-994b47ac879e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144051170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.144051170 |
Directory | /workspace/31.clkmgr_trans/latest |
Test location | /workspace/coverage/default/32.clkmgr_alert_test.3000898068 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 29386707 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:48:10 PM PDT 24 |
Finished | Apr 04 03:48:11 PM PDT 24 |
Peak memory | 200556 kb |
Host | smart-7201db53-83a2-40b3-b2c5-d976688f5750 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000898068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk mgr_alert_test.3000898068 |
Directory | /workspace/32.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.873954653 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 41531212 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:48:10 PM PDT 24 |
Finished | Apr 04 03:48:11 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-f6573f14-f57c-49c8-92e5-f010428dfeab |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873954653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.873954653 |
Directory | /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/32.clkmgr_clk_status.175581569 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 12741822 ps |
CPU time | 0.69 seconds |
Started | Apr 04 03:48:12 PM PDT 24 |
Finished | Apr 04 03:48:12 PM PDT 24 |
Peak memory | 199512 kb |
Host | smart-b34baea6-4d1b-46b5-b7c8-843490173464 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175581569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.175581569 |
Directory | /workspace/32.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/32.clkmgr_div_intersig_mubi.574980428 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 17271064 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:48:13 PM PDT 24 |
Finished | Apr 04 03:48:14 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-402653a5-2a31-43c0-a413-f632b86c94d9 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574980428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.clkmgr_div_intersig_mubi.574980428 |
Directory | /workspace/32.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/32.clkmgr_extclk.902921707 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 347826809 ps |
CPU time | 1.83 seconds |
Started | Apr 04 03:48:10 PM PDT 24 |
Finished | Apr 04 03:48:12 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-3c16eaf8-7221-446d-b68a-ca6c7b0d2ac6 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902921707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.902921707 |
Directory | /workspace/32.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/32.clkmgr_frequency.314133860 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 2021957222 ps |
CPU time | 8.98 seconds |
Started | Apr 04 03:48:16 PM PDT 24 |
Finished | Apr 04 03:48:26 PM PDT 24 |
Peak memory | 200848 kb |
Host | smart-1332ee9e-4745-4b53-aa1d-2edf5f947c79 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314133860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.314133860 |
Directory | /workspace/32.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/32.clkmgr_frequency_timeout.3158039253 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 854054521 ps |
CPU time | 6.35 seconds |
Started | Apr 04 03:48:18 PM PDT 24 |
Finished | Apr 04 03:48:25 PM PDT 24 |
Peak memory | 200216 kb |
Host | smart-31d0c837-c292-418e-88c7-84fab4de8a8d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158039253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t imeout.3158039253 |
Directory | /workspace/32.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.613658744 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 53592665 ps |
CPU time | 1.05 seconds |
Started | Apr 04 03:48:10 PM PDT 24 |
Finished | Apr 04 03:48:11 PM PDT 24 |
Peak memory | 200568 kb |
Host | smart-5836aa8a-5588-4247-a2f3-6acd33dc9065 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613658744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.clkmgr_idle_intersig_mubi.613658744 |
Directory | /workspace/32.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.4147199438 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 18586613 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:48:11 PM PDT 24 |
Finished | Apr 04 03:48:13 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-25c7f164-245f-4f83-b2b4-d3341ed5c694 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147199438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.clkmgr_lc_clk_byp_req_intersig_mubi.4147199438 |
Directory | /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.1455290685 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 18882231 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:48:13 PM PDT 24 |
Finished | Apr 04 03:48:14 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-2f12b614-9734-4d62-8aaf-2cfa75c3cb2e |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455290685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.clkmgr_lc_ctrl_intersig_mubi.1455290685 |
Directory | /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/32.clkmgr_peri.3698390458 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 187933732 ps |
CPU time | 1.2 seconds |
Started | Apr 04 03:48:12 PM PDT 24 |
Finished | Apr 04 03:48:14 PM PDT 24 |
Peak memory | 200352 kb |
Host | smart-5efea0fd-351f-4d76-89f6-a72daaac087b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698390458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.3698390458 |
Directory | /workspace/32.clkmgr_peri/latest |
Test location | /workspace/coverage/default/32.clkmgr_smoke.2671449237 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 47375096 ps |
CPU time | 0.89 seconds |
Started | Apr 04 03:48:17 PM PDT 24 |
Finished | Apr 04 03:48:19 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-ba1de5f3-4ffd-43e0-8ed8-93909c716e0b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671449237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.2671449237 |
Directory | /workspace/32.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/32.clkmgr_stress_all.779506230 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 4979415777 ps |
CPU time | 37.3 seconds |
Started | Apr 04 03:48:14 PM PDT 24 |
Finished | Apr 04 03:48:52 PM PDT 24 |
Peak memory | 201032 kb |
Host | smart-e99862fb-cdaf-4eab-9c46-db921d976158 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779506230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.779506230 |
Directory | /workspace/32.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.2578965400 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 22781273430 ps |
CPU time | 209.79 seconds |
Started | Apr 04 03:48:14 PM PDT 24 |
Finished | Apr 04 03:51:45 PM PDT 24 |
Peak memory | 217388 kb |
Host | smart-13a83342-b718-4603-aa76-fe586a30f230 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2578965400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.2578965400 |
Directory | /workspace/32.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.clkmgr_trans.579772716 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 43705876 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:48:11 PM PDT 24 |
Finished | Apr 04 03:48:12 PM PDT 24 |
Peak memory | 200560 kb |
Host | smart-9b3dd11e-f0b6-4955-a821-8c46339acca0 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579772716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.579772716 |
Directory | /workspace/32.clkmgr_trans/latest |
Test location | /workspace/coverage/default/33.clkmgr_alert_test.194308427 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 18120089 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:48:32 PM PDT 24 |
Finished | Apr 04 03:48:33 PM PDT 24 |
Peak memory | 200548 kb |
Host | smart-149328cb-62eb-4dd2-b9bb-09a1021335e6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194308427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkm gr_alert_test.194308427 |
Directory | /workspace/33.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.1459851246 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 94808324 ps |
CPU time | 0.98 seconds |
Started | Apr 04 03:48:31 PM PDT 24 |
Finished | Apr 04 03:48:32 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-35375da2-aad6-46da-a5d8-089399421c10 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459851246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.1459851246 |
Directory | /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/33.clkmgr_clk_status.3987574383 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 19659874 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:48:31 PM PDT 24 |
Finished | Apr 04 03:48:32 PM PDT 24 |
Peak memory | 200352 kb |
Host | smart-6d7c1822-e3f9-4011-a710-6fb1868f632c |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987574383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.3987574383 |
Directory | /workspace/33.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/33.clkmgr_div_intersig_mubi.3458002470 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 19732308 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:48:30 PM PDT 24 |
Finished | Apr 04 03:48:31 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-36447868-3f8e-4630-9fe1-858a02a41901 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458002470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.3458002470 |
Directory | /workspace/33.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/33.clkmgr_extclk.2966050156 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 142364055 ps |
CPU time | 1.22 seconds |
Started | Apr 04 03:48:09 PM PDT 24 |
Finished | Apr 04 03:48:10 PM PDT 24 |
Peak memory | 200612 kb |
Host | smart-7e2cce85-0258-4d4b-9555-14e6c5c27fc5 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966050156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.2966050156 |
Directory | /workspace/33.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/33.clkmgr_frequency.2776835654 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 636556378 ps |
CPU time | 2.85 seconds |
Started | Apr 04 03:48:09 PM PDT 24 |
Finished | Apr 04 03:48:12 PM PDT 24 |
Peak memory | 200588 kb |
Host | smart-81a53b37-7490-4607-8ee6-2e3c47d703f9 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776835654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.2776835654 |
Directory | /workspace/33.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/33.clkmgr_frequency_timeout.471904220 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 401860822 ps |
CPU time | 2.05 seconds |
Started | Apr 04 03:48:11 PM PDT 24 |
Finished | Apr 04 03:48:14 PM PDT 24 |
Peak memory | 200716 kb |
Host | smart-634404a1-843a-4f79-8bcc-8ea73a25ed50 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471904220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_ti meout.471904220 |
Directory | /workspace/33.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.3243535466 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 44995418 ps |
CPU time | 1.07 seconds |
Started | Apr 04 03:48:31 PM PDT 24 |
Finished | Apr 04 03:48:32 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-4fc073c7-1c99-4d42-95ea-bebaa5de641d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243535466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.3243535466 |
Directory | /workspace/33.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.4139595014 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 24001254 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:48:28 PM PDT 24 |
Finished | Apr 04 03:48:30 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-c4f64b1d-a454-499a-b481-725b017cace0 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139595014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_clk_byp_req_intersig_mubi.4139595014 |
Directory | /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.3927769450 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 119981270 ps |
CPU time | 1.14 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:37 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-addae61d-c9be-4f56-8f45-1099d071654d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927769450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_ctrl_intersig_mubi.3927769450 |
Directory | /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/33.clkmgr_peri.3807446307 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 17465011 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:48:30 PM PDT 24 |
Finished | Apr 04 03:48:31 PM PDT 24 |
Peak memory | 200324 kb |
Host | smart-8a521701-65a6-4ceb-8472-388644adb547 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807446307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.3807446307 |
Directory | /workspace/33.clkmgr_peri/latest |
Test location | /workspace/coverage/default/33.clkmgr_regwen.2798705957 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 500933347 ps |
CPU time | 2.15 seconds |
Started | Apr 04 03:48:28 PM PDT 24 |
Finished | Apr 04 03:48:31 PM PDT 24 |
Peak memory | 200572 kb |
Host | smart-671fc2e3-9d02-49a4-aa40-0b974b99dfc4 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798705957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.2798705957 |
Directory | /workspace/33.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/33.clkmgr_smoke.1271387147 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 18888366 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:48:10 PM PDT 24 |
Finished | Apr 04 03:48:11 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-de7d8c6b-f071-4d98-b4c3-f3dedfaa3a82 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271387147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.1271387147 |
Directory | /workspace/33.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/33.clkmgr_stress_all.3129580822 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 6386298074 ps |
CPU time | 26.35 seconds |
Started | Apr 04 03:48:30 PM PDT 24 |
Finished | Apr 04 03:48:57 PM PDT 24 |
Peak memory | 200976 kb |
Host | smart-9197dfb8-49ae-4bca-9277-336d15c53852 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129580822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.3129580822 |
Directory | /workspace/33.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.345541124 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 28682558676 ps |
CPU time | 216.13 seconds |
Started | Apr 04 03:48:33 PM PDT 24 |
Finished | Apr 04 03:52:09 PM PDT 24 |
Peak memory | 209212 kb |
Host | smart-a6a8e88a-d655-4da8-b118-e390fefbb370 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=345541124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.345541124 |
Directory | /workspace/33.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.clkmgr_trans.657132724 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 95714247 ps |
CPU time | 1.18 seconds |
Started | Apr 04 03:48:29 PM PDT 24 |
Finished | Apr 04 03:48:31 PM PDT 24 |
Peak memory | 200588 kb |
Host | smart-ab949671-c954-4b37-a545-1fc55e4ff405 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657132724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.657132724 |
Directory | /workspace/33.clkmgr_trans/latest |
Test location | /workspace/coverage/default/34.clkmgr_alert_test.625235970 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 25121006 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:37 PM PDT 24 |
Peak memory | 200496 kb |
Host | smart-f81ba0bb-9074-40d0-b768-45c1840e6ddd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625235970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkm gr_alert_test.625235970 |
Directory | /workspace/34.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.323544867 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 38782655 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:36 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-7dd22144-a59f-4417-93f3-ff185d0a3831 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323544867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.323544867 |
Directory | /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/34.clkmgr_clk_status.2855901274 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 49060605 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:36 PM PDT 24 |
Peak memory | 200344 kb |
Host | smart-37de7c2e-42e0-4f4b-abd0-e94cb9e7a2fe |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855901274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.2855901274 |
Directory | /workspace/34.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/34.clkmgr_div_intersig_mubi.3834732420 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 47014471 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:36 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-edef79a2-2031-42d5-ab29-cf4db76e43e8 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834732420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.3834732420 |
Directory | /workspace/34.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/34.clkmgr_extclk.1441910608 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 22944910 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:48:31 PM PDT 24 |
Finished | Apr 04 03:48:32 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-083fc3de-33dd-44da-b5bf-f4d52acaa0b5 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441910608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.1441910608 |
Directory | /workspace/34.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/34.clkmgr_frequency.3367332668 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 1644498292 ps |
CPU time | 11.07 seconds |
Started | Apr 04 03:48:32 PM PDT 24 |
Finished | Apr 04 03:48:43 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-11f275d8-8e16-47ac-b67e-e0d94f95ea5d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367332668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.3367332668 |
Directory | /workspace/34.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/34.clkmgr_frequency_timeout.253960229 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 1826305253 ps |
CPU time | 7.45 seconds |
Started | Apr 04 03:48:32 PM PDT 24 |
Finished | Apr 04 03:48:40 PM PDT 24 |
Peak memory | 200704 kb |
Host | smart-3c807ba6-9882-434d-8b80-3dda804c2e3b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253960229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_ti meout.253960229 |
Directory | /workspace/34.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.119559891 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 100459265 ps |
CPU time | 1.23 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-0477abac-8475-4251-8916-e2d5d9f6cdb0 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119559891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.clkmgr_idle_intersig_mubi.119559891 |
Directory | /workspace/34.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.1621836075 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 23853796 ps |
CPU time | 0.88 seconds |
Started | Apr 04 03:48:38 PM PDT 24 |
Finished | Apr 04 03:48:39 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-5a368075-91ee-4de6-b648-4082592ce3e7 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621836075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 34.clkmgr_lc_clk_byp_req_intersig_mubi.1621836075 |
Directory | /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.1233145803 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 83167952 ps |
CPU time | 1.09 seconds |
Started | Apr 04 03:48:38 PM PDT 24 |
Finished | Apr 04 03:48:39 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-f2a11a9c-a780-4f9c-969b-2f1e9e3d142e |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233145803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 34.clkmgr_lc_ctrl_intersig_mubi.1233145803 |
Directory | /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/34.clkmgr_peri.2038330910 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 33540882 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:48:32 PM PDT 24 |
Finished | Apr 04 03:48:33 PM PDT 24 |
Peak memory | 200412 kb |
Host | smart-418c1df0-e9cb-4499-a54f-99c50ddcdd02 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038330910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.2038330910 |
Directory | /workspace/34.clkmgr_peri/latest |
Test location | /workspace/coverage/default/34.clkmgr_regwen.1085101960 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 422441789 ps |
CPU time | 1.99 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:37 PM PDT 24 |
Peak memory | 200580 kb |
Host | smart-377b250c-52bf-4f64-8fa3-c48996786525 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085101960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.1085101960 |
Directory | /workspace/34.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/34.clkmgr_smoke.3286463180 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 76702644 ps |
CPU time | 0.97 seconds |
Started | Apr 04 03:48:32 PM PDT 24 |
Finished | Apr 04 03:48:33 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-ef912f6a-396a-45b2-ac26-dc14b63914d4 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286463180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.3286463180 |
Directory | /workspace/34.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/34.clkmgr_stress_all.2876308912 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 5914779237 ps |
CPU time | 24.32 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:49:01 PM PDT 24 |
Peak memory | 200888 kb |
Host | smart-9228eba1-a04d-4c0d-a4b2-bd05e1823584 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876308912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.2876308912 |
Directory | /workspace/34.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.1945505545 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 19578852475 ps |
CPU time | 255.76 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:52:51 PM PDT 24 |
Peak memory | 217460 kb |
Host | smart-411442d5-112f-4c11-97bc-8f126df0e8c2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1945505545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.1945505545 |
Directory | /workspace/34.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.clkmgr_trans.215348626 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 60339549 ps |
CPU time | 0.98 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-49c535fd-296b-431b-b622-ce639c9f86de |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215348626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.215348626 |
Directory | /workspace/34.clkmgr_trans/latest |
Test location | /workspace/coverage/default/35.clkmgr_alert_test.1505482448 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 52232929 ps |
CPU time | 0.85 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:35 PM PDT 24 |
Peak memory | 200512 kb |
Host | smart-c6db3347-b05a-4016-842b-5020d21d2bb8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505482448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk mgr_alert_test.1505482448 |
Directory | /workspace/35.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.628332874 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 17945573 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:36 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-faaa64d8-f894-4e72-ae1b-f707200a802f |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628332874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.628332874 |
Directory | /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/35.clkmgr_clk_status.4157375049 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 17785226 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200304 kb |
Host | smart-5b2efef7-3dff-4532-849a-8a45f89aa6b8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157375049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.4157375049 |
Directory | /workspace/35.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/35.clkmgr_div_intersig_mubi.895392732 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 79484342 ps |
CPU time | 1.03 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-9fa3885e-b3ea-4073-b355-82ae3c3f0ee0 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895392732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.clkmgr_div_intersig_mubi.895392732 |
Directory | /workspace/35.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/35.clkmgr_extclk.3034264112 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 62843779 ps |
CPU time | 0.92 seconds |
Started | Apr 04 03:48:38 PM PDT 24 |
Finished | Apr 04 03:48:39 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-4e61ec9d-e7df-48a3-852a-6834e746c179 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034264112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3034264112 |
Directory | /workspace/35.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/35.clkmgr_frequency.1104472936 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 561935316 ps |
CPU time | 3.65 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:41 PM PDT 24 |
Peak memory | 200612 kb |
Host | smart-1395e9bd-5324-4c18-958b-8d425aa0544b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104472936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.1104472936 |
Directory | /workspace/35.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/35.clkmgr_frequency_timeout.4133997870 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 746741035 ps |
CPU time | 3.88 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:41 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-778fa97c-305a-42c2-ad74-768bcc3083ed |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133997870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t imeout.4133997870 |
Directory | /workspace/35.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.3892920141 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 28311506 ps |
CPU time | 0.94 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-3bd9771b-cfd7-421d-9bcf-6810cf135905 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892920141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.3892920141 |
Directory | /workspace/35.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.1180583461 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 20679277 ps |
CPU time | 0.88 seconds |
Started | Apr 04 03:48:38 PM PDT 24 |
Finished | Apr 04 03:48:39 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-9a3469cd-a166-4cc8-bbc7-a3aa544fa3ff |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180583461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.clkmgr_lc_clk_byp_req_intersig_mubi.1180583461 |
Directory | /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.3891756360 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 46374228 ps |
CPU time | 0.92 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:37 PM PDT 24 |
Peak memory | 200596 kb |
Host | smart-9561482b-6661-46ec-bc9d-444bb7925459 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891756360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.clkmgr_lc_ctrl_intersig_mubi.3891756360 |
Directory | /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/35.clkmgr_peri.1688646007 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 14475978 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200368 kb |
Host | smart-e9fc9a52-c988-434c-926e-9d62f9c06150 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688646007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.1688646007 |
Directory | /workspace/35.clkmgr_peri/latest |
Test location | /workspace/coverage/default/35.clkmgr_regwen.362599402 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 411500365 ps |
CPU time | 1.65 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:37 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-8d18f6f2-14b7-4495-aaed-c4df953bfdd2 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362599402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.362599402 |
Directory | /workspace/35.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/35.clkmgr_smoke.1962233575 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 73202620 ps |
CPU time | 0.97 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:35 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-05b48b85-8de5-4223-bb67-47ba1f7c0e79 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962233575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.1962233575 |
Directory | /workspace/35.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/35.clkmgr_stress_all.330538815 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 75061333 ps |
CPU time | 0.93 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200612 kb |
Host | smart-54d41669-c9a0-4d7b-ad3d-ad33bbf36118 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330538815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.330538815 |
Directory | /workspace/35.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.2836309974 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 32733463073 ps |
CPU time | 450.6 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:56:08 PM PDT 24 |
Peak memory | 217432 kb |
Host | smart-007dc96d-a609-4aca-9b91-76a53c970249 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2836309974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.2836309974 |
Directory | /workspace/35.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.clkmgr_trans.909170972 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 37903349 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200532 kb |
Host | smart-f7a6ab8c-7adc-4666-ba38-6010baa7e5e1 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909170972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.909170972 |
Directory | /workspace/35.clkmgr_trans/latest |
Test location | /workspace/coverage/default/36.clkmgr_alert_test.1448089364 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 50750333 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:48:32 PM PDT 24 |
Finished | Apr 04 03:48:33 PM PDT 24 |
Peak memory | 200548 kb |
Host | smart-e0d1122e-d2dc-4ed7-ae28-7ac64f0cdb68 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448089364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk mgr_alert_test.1448089364 |
Directory | /workspace/36.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.2046495023 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 63545427 ps |
CPU time | 0.9 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:35 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-fb9b55e7-b511-4c15-9c05-6e6fff36c6b0 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046495023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.2046495023 |
Directory | /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/36.clkmgr_clk_status.2498296087 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 40286126 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200340 kb |
Host | smart-ec22ccd5-b743-4f41-bb55-a6b13f3051b2 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498296087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.2498296087 |
Directory | /workspace/36.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/36.clkmgr_div_intersig_mubi.1566135756 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 13138475 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:48:33 PM PDT 24 |
Finished | Apr 04 03:48:33 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-55ddef80-899d-4595-90c4-ac4fb384760d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566135756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.1566135756 |
Directory | /workspace/36.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/36.clkmgr_extclk.3549677904 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 21101804 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:37 PM PDT 24 |
Peak memory | 200424 kb |
Host | smart-cbaed579-e228-4d30-83a0-7a9b11fffe6d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549677904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.3549677904 |
Directory | /workspace/36.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/36.clkmgr_frequency.2617154234 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 2381847544 ps |
CPU time | 9.72 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:44 PM PDT 24 |
Peak memory | 200832 kb |
Host | smart-e1fe6823-5cf7-4452-a3ce-332e775e796a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617154234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.2617154234 |
Directory | /workspace/36.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/36.clkmgr_frequency_timeout.2219551729 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 635577247 ps |
CPU time | 2.93 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:39 PM PDT 24 |
Peak memory | 200720 kb |
Host | smart-0efd3c76-9ad7-4b2f-8ba2-083526f1a7d9 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219551729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t imeout.2219551729 |
Directory | /workspace/36.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.3447791074 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 141633540 ps |
CPU time | 1.36 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:35 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-1919443d-a926-4fbb-92dd-a1557054fad9 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447791074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.3447791074 |
Directory | /workspace/36.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.277092879 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 40164712 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:48:30 PM PDT 24 |
Finished | Apr 04 03:48:31 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-f2cfe474-fab1-4321-9fc3-00d38e2d1ffd |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277092879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.clkmgr_lc_clk_byp_req_intersig_mubi.277092879 |
Directory | /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.3822791436 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 115831262 ps |
CPU time | 1.07 seconds |
Started | Apr 04 03:48:29 PM PDT 24 |
Finished | Apr 04 03:48:31 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-c3793a26-b558-4e05-b5db-5b2359d272f5 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822791436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 36.clkmgr_lc_ctrl_intersig_mubi.3822791436 |
Directory | /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/36.clkmgr_peri.3258199423 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 17391997 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:35 PM PDT 24 |
Peak memory | 200400 kb |
Host | smart-e03390ee-541f-45e4-9388-0e18d0ea60ab |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258199423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.3258199423 |
Directory | /workspace/36.clkmgr_peri/latest |
Test location | /workspace/coverage/default/36.clkmgr_regwen.64562925 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 1026920830 ps |
CPU time | 4.38 seconds |
Started | Apr 04 03:48:30 PM PDT 24 |
Finished | Apr 04 03:48:35 PM PDT 24 |
Peak memory | 200760 kb |
Host | smart-59755be1-586d-4767-833f-79e1df6db278 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64562925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.64562925 |
Directory | /workspace/36.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/36.clkmgr_smoke.370224727 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 82395780 ps |
CPU time | 1.04 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:37 PM PDT 24 |
Peak memory | 200488 kb |
Host | smart-9f36844c-ffcc-4df5-82a3-b6fec01da615 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370224727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.370224727 |
Directory | /workspace/36.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/36.clkmgr_stress_all.442193135 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 11285352477 ps |
CPU time | 83.02 seconds |
Started | Apr 04 03:48:30 PM PDT 24 |
Finished | Apr 04 03:49:53 PM PDT 24 |
Peak memory | 201008 kb |
Host | smart-775ba3a6-860d-44d8-b195-09c52f99f1ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442193135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.442193135 |
Directory | /workspace/36.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.3120367842 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 105459575211 ps |
CPU time | 685.92 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 04:00:00 PM PDT 24 |
Peak memory | 209184 kb |
Host | smart-ec4f07d1-edae-4903-867c-b8378d3a044b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3120367842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.3120367842 |
Directory | /workspace/36.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.clkmgr_trans.700919593 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 36774663 ps |
CPU time | 1 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:37 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-9517c1d3-3c44-4f4b-a8ff-30f57cc73241 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700919593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.700919593 |
Directory | /workspace/36.clkmgr_trans/latest |
Test location | /workspace/coverage/default/37.clkmgr_alert_test.2878032106 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 34295976 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:37 PM PDT 24 |
Peak memory | 200456 kb |
Host | smart-dfeb0a3c-e967-46b1-b24b-459909600b17 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878032106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk mgr_alert_test.2878032106 |
Directory | /workspace/37.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.537629592 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 31634872 ps |
CPU time | 0.85 seconds |
Started | Apr 04 03:48:38 PM PDT 24 |
Finished | Apr 04 03:48:39 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-424f16e6-8827-411f-93e7-fc1cfb766894 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537629592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.537629592 |
Directory | /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/37.clkmgr_clk_status.3796679938 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 19958626 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:35 PM PDT 24 |
Peak memory | 199576 kb |
Host | smart-e82efeb2-aa5e-4b3b-8a04-e4c35eb59bea |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796679938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.3796679938 |
Directory | /workspace/37.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/37.clkmgr_div_intersig_mubi.4289578758 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 23932737 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:35 PM PDT 24 |
Peak memory | 200500 kb |
Host | smart-9cee9cfc-b32c-4f79-afcc-e4ce3b218368 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289578758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.4289578758 |
Directory | /workspace/37.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/37.clkmgr_extclk.1114631000 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 60775059 ps |
CPU time | 0.88 seconds |
Started | Apr 04 03:48:32 PM PDT 24 |
Finished | Apr 04 03:48:33 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-1a648aa6-efb1-44a1-a767-05bfb2f35461 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114631000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.1114631000 |
Directory | /workspace/37.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/37.clkmgr_frequency.1170591971 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 2002047232 ps |
CPU time | 15.26 seconds |
Started | Apr 04 03:48:31 PM PDT 24 |
Finished | Apr 04 03:48:47 PM PDT 24 |
Peak memory | 200812 kb |
Host | smart-758e3d53-ca81-496e-b090-7605c5cdc8da |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170591971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.1170591971 |
Directory | /workspace/37.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/37.clkmgr_frequency_timeout.116646747 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 504779202 ps |
CPU time | 3.26 seconds |
Started | Apr 04 03:48:38 PM PDT 24 |
Finished | Apr 04 03:48:42 PM PDT 24 |
Peak memory | 200700 kb |
Host | smart-d340348d-93e7-4bc7-96a9-d0a230cf1a21 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116646747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_ti meout.116646747 |
Directory | /workspace/37.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.262654361 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 23742887 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:37 PM PDT 24 |
Peak memory | 200532 kb |
Host | smart-ab73eb1f-2744-442b-b4b1-aff1b5896ed1 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262654361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.clkmgr_idle_intersig_mubi.262654361 |
Directory | /workspace/37.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.2456258510 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 18851257 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:36 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-0c88c964-815d-4799-8519-fa131f9c120f |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456258510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.clkmgr_lc_clk_byp_req_intersig_mubi.2456258510 |
Directory | /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1102605507 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 19764782 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:36 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-a5da578f-be45-495a-86d0-4761ea5f0fbe |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102605507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.clkmgr_lc_ctrl_intersig_mubi.1102605507 |
Directory | /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/37.clkmgr_peri.4246807803 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 36526193 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:48:33 PM PDT 24 |
Finished | Apr 04 03:48:34 PM PDT 24 |
Peak memory | 200364 kb |
Host | smart-b600d722-5ee0-4cfb-8856-c8565ece5b43 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246807803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.4246807803 |
Directory | /workspace/37.clkmgr_peri/latest |
Test location | /workspace/coverage/default/37.clkmgr_regwen.370510957 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 1001866540 ps |
CPU time | 4.1 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:39 PM PDT 24 |
Peak memory | 200820 kb |
Host | smart-b6c8514e-1b57-4d14-a29e-3e7b86fdd11a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370510957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.370510957 |
Directory | /workspace/37.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/37.clkmgr_smoke.3617856230 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 24471331 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:35 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-4fb2ed7c-842a-4f0d-a4d7-835d7bf4a10f |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617856230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.3617856230 |
Directory | /workspace/37.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/37.clkmgr_stress_all.1850436260 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 122116119 ps |
CPU time | 1.11 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:37 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-e34dc937-5332-43d1-a34c-a953cc907121 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850436260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.1850436260 |
Directory | /workspace/37.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.2881965604 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 34932472435 ps |
CPU time | 517.94 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:57:14 PM PDT 24 |
Peak memory | 209248 kb |
Host | smart-aa4283d2-4043-4b79-9970-e6e05e2f63ab |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2881965604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.2881965604 |
Directory | /workspace/37.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.clkmgr_trans.4267091499 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 83363409 ps |
CPU time | 0.98 seconds |
Started | Apr 04 03:48:32 PM PDT 24 |
Finished | Apr 04 03:48:33 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-912fc1d0-e546-4e49-809b-82fd095149bf |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267091499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.4267091499 |
Directory | /workspace/37.clkmgr_trans/latest |
Test location | /workspace/coverage/default/38.clkmgr_alert_test.1185933895 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 44827009 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200444 kb |
Host | smart-4a3f01b6-23ef-40ef-9fbd-32c75092a694 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185933895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk mgr_alert_test.1185933895 |
Directory | /workspace/38.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.1264893731 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 81909127 ps |
CPU time | 1.01 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:35 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-d5872224-d822-4eb5-a37d-4873a70ab4f8 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264893731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.1264893731 |
Directory | /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/38.clkmgr_clk_status.3682260496 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 22466379 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 199556 kb |
Host | smart-4881b579-f0af-4912-9231-93ad2e4a8538 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682260496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.3682260496 |
Directory | /workspace/38.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/38.clkmgr_div_intersig_mubi.2320329248 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 14784878 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:48:38 PM PDT 24 |
Finished | Apr 04 03:48:39 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-88e31e5f-ed0e-4ed8-a3c8-811b7d92a68d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320329248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.2320329248 |
Directory | /workspace/38.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/38.clkmgr_extclk.58630270 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 62842208 ps |
CPU time | 0.96 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:36 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-12b9d803-1d49-45a9-990c-6a77a21edb5b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58630270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.58630270 |
Directory | /workspace/38.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/38.clkmgr_frequency.3358958080 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 1582793485 ps |
CPU time | 7.03 seconds |
Started | Apr 04 03:48:33 PM PDT 24 |
Finished | Apr 04 03:48:40 PM PDT 24 |
Peak memory | 200712 kb |
Host | smart-cc3f829e-abb1-4da9-a4df-93a18f2677cf |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358958080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.3358958080 |
Directory | /workspace/38.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/38.clkmgr_frequency_timeout.3039206832 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 858889924 ps |
CPU time | 6.31 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:41 PM PDT 24 |
Peak memory | 200696 kb |
Host | smart-75ba6211-db55-4431-a310-72489d6d177b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039206832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t imeout.3039206832 |
Directory | /workspace/38.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.2176771563 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 29781970 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:48:33 PM PDT 24 |
Finished | Apr 04 03:48:34 PM PDT 24 |
Peak memory | 200488 kb |
Host | smart-12e5797a-4d43-4958-96b9-6b889a3f29c2 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176771563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.2176771563 |
Directory | /workspace/38.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.2988904947 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 16564610 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:36 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-0648494b-e773-4f80-90bf-5c1fbdff4cd9 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988904947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 38.clkmgr_lc_clk_byp_req_intersig_mubi.2988904947 |
Directory | /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.2317121195 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 52294251 ps |
CPU time | 0.92 seconds |
Started | Apr 04 03:48:38 PM PDT 24 |
Finished | Apr 04 03:48:39 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-1cb96d58-97b9-4790-8eeb-979adf5c4e71 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317121195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 38.clkmgr_lc_ctrl_intersig_mubi.2317121195 |
Directory | /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/38.clkmgr_peri.2492302822 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 16378275 ps |
CPU time | 0.71 seconds |
Started | Apr 04 03:48:34 PM PDT 24 |
Finished | Apr 04 03:48:35 PM PDT 24 |
Peak memory | 200296 kb |
Host | smart-700d0af2-e14f-4478-99d9-518b41f841e3 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492302822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.2492302822 |
Directory | /workspace/38.clkmgr_peri/latest |
Test location | /workspace/coverage/default/38.clkmgr_regwen.2072937647 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 859573341 ps |
CPU time | 4.06 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:40 PM PDT 24 |
Peak memory | 200744 kb |
Host | smart-21f679fd-4fae-485d-a65a-b662aab8fce8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072937647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.2072937647 |
Directory | /workspace/38.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/38.clkmgr_smoke.1816940968 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 24528939 ps |
CPU time | 0.85 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:36 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-be8387b8-65d6-42c5-bd1c-8623128ec3f4 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816940968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.1816940968 |
Directory | /workspace/38.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/38.clkmgr_stress_all.3390672497 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 620073855 ps |
CPU time | 5.5 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:43 PM PDT 24 |
Peak memory | 200888 kb |
Host | smart-79488748-f478-4bd9-ac68-f6234acf0071 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390672497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.3390672497 |
Directory | /workspace/38.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.3858283022 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 27081007323 ps |
CPU time | 482.87 seconds |
Started | Apr 04 03:48:38 PM PDT 24 |
Finished | Apr 04 03:56:41 PM PDT 24 |
Peak memory | 217464 kb |
Host | smart-b828d0c1-a79b-4f40-86af-c27c29387f4d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3858283022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.3858283022 |
Directory | /workspace/38.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.clkmgr_trans.2287524433 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 39681752 ps |
CPU time | 1.03 seconds |
Started | Apr 04 03:48:38 PM PDT 24 |
Finished | Apr 04 03:48:39 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-8cf8c342-82b5-4f31-8e99-4fabc99dd9af |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287524433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.2287524433 |
Directory | /workspace/38.clkmgr_trans/latest |
Test location | /workspace/coverage/default/39.clkmgr_alert_test.3955309167 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 71599852 ps |
CPU time | 0.99 seconds |
Started | Apr 04 03:48:38 PM PDT 24 |
Finished | Apr 04 03:48:39 PM PDT 24 |
Peak memory | 200528 kb |
Host | smart-42e9dce9-4ee3-4bd4-a5a0-993e3806a408 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955309167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk mgr_alert_test.3955309167 |
Directory | /workspace/39.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.1284575057 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 65982044 ps |
CPU time | 0.96 seconds |
Started | Apr 04 03:48:43 PM PDT 24 |
Finished | Apr 04 03:48:45 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-957e8a2d-1f8c-489c-bf87-50be9ebc457b |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284575057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.1284575057 |
Directory | /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/39.clkmgr_clk_status.3145266918 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 16098081 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:48:42 PM PDT 24 |
Finished | Apr 04 03:48:43 PM PDT 24 |
Peak memory | 200356 kb |
Host | smart-519f8970-cad6-4b2f-927b-4b3d51bc9dcd |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145266918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.3145266918 |
Directory | /workspace/39.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/39.clkmgr_div_intersig_mubi.2119030723 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 34914465 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-83d6bdea-e49a-4046-83bb-560dcb787287 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119030723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.2119030723 |
Directory | /workspace/39.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/39.clkmgr_extclk.967722911 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 45674943 ps |
CPU time | 0.99 seconds |
Started | Apr 04 03:48:40 PM PDT 24 |
Finished | Apr 04 03:48:41 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-acf90f2e-a0eb-4ca1-9cc1-8b3b91b0afc3 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967722911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.967722911 |
Directory | /workspace/39.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/39.clkmgr_frequency.1911150369 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 441935953 ps |
CPU time | 3.88 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:40 PM PDT 24 |
Peak memory | 200576 kb |
Host | smart-42430263-391c-42b9-9d4f-c5b01f485aba |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911150369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.1911150369 |
Directory | /workspace/39.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/39.clkmgr_frequency_timeout.3185499558 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 1238437054 ps |
CPU time | 4.87 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:41 PM PDT 24 |
Peak memory | 200692 kb |
Host | smart-6375553b-d2d1-406c-93ec-4fe3720e45d3 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185499558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t imeout.3185499558 |
Directory | /workspace/39.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.3096835110 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 30022662 ps |
CPU time | 1 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200592 kb |
Host | smart-d90ab6d8-5a2b-4735-bac4-b1590fd365fc |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096835110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.3096835110 |
Directory | /workspace/39.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.233368944 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 22030562 ps |
CPU time | 0.89 seconds |
Started | Apr 04 03:48:41 PM PDT 24 |
Finished | Apr 04 03:48:42 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-bbb4ea74-0057-4d55-af55-b5c2a34a1955 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233368944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.clkmgr_lc_clk_byp_req_intersig_mubi.233368944 |
Directory | /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.160455860 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 131767589 ps |
CPU time | 1.15 seconds |
Started | Apr 04 03:48:40 PM PDT 24 |
Finished | Apr 04 03:48:42 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-aca94d18-df89-44eb-91b9-89cb4b50c2ed |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160455860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.clkmgr_lc_ctrl_intersig_mubi.160455860 |
Directory | /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/39.clkmgr_peri.3924103686 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 18982108 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200356 kb |
Host | smart-7050bcb3-0be2-4a19-9c61-95ee8cbfada8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924103686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.3924103686 |
Directory | /workspace/39.clkmgr_peri/latest |
Test location | /workspace/coverage/default/39.clkmgr_regwen.1312316142 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 500867929 ps |
CPU time | 2.29 seconds |
Started | Apr 04 03:48:40 PM PDT 24 |
Finished | Apr 04 03:48:43 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-92fe89d6-1c1d-42fa-865c-8f3e6c8cb73d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312316142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1312316142 |
Directory | /workspace/39.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/39.clkmgr_smoke.3051484531 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 53584057 ps |
CPU time | 0.95 seconds |
Started | Apr 04 03:48:41 PM PDT 24 |
Finished | Apr 04 03:48:42 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-aea75b65-76ab-4255-9e59-05d9ddd8e8f0 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051484531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.3051484531 |
Directory | /workspace/39.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/39.clkmgr_stress_all.3438688181 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 5561649808 ps |
CPU time | 27.28 seconds |
Started | Apr 04 03:48:39 PM PDT 24 |
Finished | Apr 04 03:49:06 PM PDT 24 |
Peak memory | 201016 kb |
Host | smart-2940bf9a-36df-45e0-a3a4-79da9cd46b97 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438688181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.3438688181 |
Directory | /workspace/39.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.1828528491 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 79492910489 ps |
CPU time | 447.11 seconds |
Started | Apr 04 03:48:39 PM PDT 24 |
Finished | Apr 04 03:56:06 PM PDT 24 |
Peak memory | 209308 kb |
Host | smart-5505bd3c-8aa9-49d5-8685-3750c4f5fdff |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1828528491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.1828528491 |
Directory | /workspace/39.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.clkmgr_trans.2067775878 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 160860298 ps |
CPU time | 1.25 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-47843962-b2dd-4223-9958-cc5f9f425a2e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067775878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.2067775878 |
Directory | /workspace/39.clkmgr_trans/latest |
Test location | /workspace/coverage/default/4.clkmgr_alert_test.52849945 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 27315395 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:46:31 PM PDT 24 |
Finished | Apr 04 03:46:32 PM PDT 24 |
Peak memory | 200484 kb |
Host | smart-854af7c3-5b3b-402f-9e94-487d026ea15b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52849945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr _alert_test.52849945 |
Directory | /workspace/4.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.110704750 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 65918985 ps |
CPU time | 1.01 seconds |
Started | Apr 04 03:46:25 PM PDT 24 |
Finished | Apr 04 03:46:26 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-dd789e7a-8193-43e8-9bc6-2480451d41f4 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110704750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.110704750 |
Directory | /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/4.clkmgr_clk_status.1516761208 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 24222333 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:46:30 PM PDT 24 |
Finished | Apr 04 03:46:30 PM PDT 24 |
Peak memory | 199616 kb |
Host | smart-dc0e48ad-2440-42de-bc4d-6976d2c5c11e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516761208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.1516761208 |
Directory | /workspace/4.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/4.clkmgr_div_intersig_mubi.2856552203 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 42786447 ps |
CPU time | 0.88 seconds |
Started | Apr 04 03:46:30 PM PDT 24 |
Finished | Apr 04 03:46:31 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-95f56e28-51ae-46e2-8548-98414094b7ec |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856552203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.2856552203 |
Directory | /workspace/4.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/4.clkmgr_extclk.2578858770 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 78490010 ps |
CPU time | 1.08 seconds |
Started | Apr 04 03:46:30 PM PDT 24 |
Finished | Apr 04 03:46:31 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-fe853d55-d77e-40d5-a664-c022c8fb106e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578858770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.2578858770 |
Directory | /workspace/4.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/4.clkmgr_frequency.2591603169 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 2245284981 ps |
CPU time | 12.59 seconds |
Started | Apr 04 03:46:26 PM PDT 24 |
Finished | Apr 04 03:46:38 PM PDT 24 |
Peak memory | 200856 kb |
Host | smart-38b40b82-8625-46a5-a4d3-b0a785af0e10 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591603169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.2591603169 |
Directory | /workspace/4.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/4.clkmgr_frequency_timeout.2782869222 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 1098464177 ps |
CPU time | 8.05 seconds |
Started | Apr 04 03:46:25 PM PDT 24 |
Finished | Apr 04 03:46:33 PM PDT 24 |
Peak memory | 200696 kb |
Host | smart-ef7e64d5-04b0-459e-accd-1caaffa94a19 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782869222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti meout.2782869222 |
Directory | /workspace/4.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.3918486501 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 32683717 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:46:27 PM PDT 24 |
Finished | Apr 04 03:46:28 PM PDT 24 |
Peak memory | 200472 kb |
Host | smart-1e6fb953-109b-4909-bae9-edcbe7b81ac2 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918486501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.3918486501 |
Directory | /workspace/4.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.2331354764 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 13584942 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:46:27 PM PDT 24 |
Finished | Apr 04 03:46:28 PM PDT 24 |
Peak memory | 200524 kb |
Host | smart-0977ed2e-a521-48fc-96be-405f433bd9e1 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331354764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.clkmgr_lc_clk_byp_req_intersig_mubi.2331354764 |
Directory | /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.1040487181 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 42882666 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:46:26 PM PDT 24 |
Finished | Apr 04 03:46:27 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-c8f896a5-5510-4b23-b1db-973d71d5aa4c |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040487181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.clkmgr_lc_ctrl_intersig_mubi.1040487181 |
Directory | /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/4.clkmgr_peri.3273803683 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 15072607 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:46:26 PM PDT 24 |
Finished | Apr 04 03:46:27 PM PDT 24 |
Peak memory | 200360 kb |
Host | smart-669a015e-495c-47bf-956e-7e90b52b95f4 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273803683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.3273803683 |
Directory | /workspace/4.clkmgr_peri/latest |
Test location | /workspace/coverage/default/4.clkmgr_regwen.1976498646 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 864160805 ps |
CPU time | 3.13 seconds |
Started | Apr 04 03:46:28 PM PDT 24 |
Finished | Apr 04 03:46:31 PM PDT 24 |
Peak memory | 200788 kb |
Host | smart-7c8d0b2a-15ef-427b-ad9d-46ca58a6424c |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976498646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.1976498646 |
Directory | /workspace/4.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/4.clkmgr_sec_cm.2556333273 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 212660635 ps |
CPU time | 1.99 seconds |
Started | Apr 04 03:46:26 PM PDT 24 |
Finished | Apr 04 03:46:28 PM PDT 24 |
Peak memory | 219944 kb |
Host | smart-ce0f0b30-058f-4726-94b2-33abea3950ff |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556333273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg r_sec_cm.2556333273 |
Directory | /workspace/4.clkmgr_sec_cm/latest |
Test location | /workspace/coverage/default/4.clkmgr_smoke.2878110289 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 15478200 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:46:25 PM PDT 24 |
Finished | Apr 04 03:46:26 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-5c889fad-a8db-46f6-a6da-1004e6d56179 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878110289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.2878110289 |
Directory | /workspace/4.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.2984300312 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 337133756006 ps |
CPU time | 1388.99 seconds |
Started | Apr 04 03:46:24 PM PDT 24 |
Finished | Apr 04 04:09:33 PM PDT 24 |
Peak memory | 217444 kb |
Host | smart-9801a60d-0a7d-4a9b-a3d2-8c8466f25029 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2984300312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.2984300312 |
Directory | /workspace/4.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.clkmgr_trans.3543370619 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 63746588 ps |
CPU time | 0.96 seconds |
Started | Apr 04 03:46:24 PM PDT 24 |
Finished | Apr 04 03:46:25 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-322ba38e-e81c-42b3-b2d0-18cd246625a8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543370619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.3543370619 |
Directory | /workspace/4.clkmgr_trans/latest |
Test location | /workspace/coverage/default/40.clkmgr_alert_test.1065339180 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 48507789 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:48:43 PM PDT 24 |
Finished | Apr 04 03:48:44 PM PDT 24 |
Peak memory | 200476 kb |
Host | smart-ac1ab328-bccc-46a4-afd6-5f4c1d195f7f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065339180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk mgr_alert_test.1065339180 |
Directory | /workspace/40.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.1359454290 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 58187277 ps |
CPU time | 0.97 seconds |
Started | Apr 04 03:48:41 PM PDT 24 |
Finished | Apr 04 03:48:42 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-fb272800-c59a-4ef1-9cc4-3575d6b29189 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359454290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.1359454290 |
Directory | /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/40.clkmgr_clk_status.4255894703 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 15134342 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:48:40 PM PDT 24 |
Finished | Apr 04 03:48:41 PM PDT 24 |
Peak memory | 200332 kb |
Host | smart-67d6d648-b833-40f0-9d4e-ba8850e91c6d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255894703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.4255894703 |
Directory | /workspace/40.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/40.clkmgr_div_intersig_mubi.521502825 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 17222981 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:48:40 PM PDT 24 |
Finished | Apr 04 03:48:41 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-e7ad4e1e-9581-456c-ac5d-bcb0f20c1be0 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521502825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.clkmgr_div_intersig_mubi.521502825 |
Directory | /workspace/40.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/40.clkmgr_extclk.4081977817 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 41677643 ps |
CPU time | 0.92 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:37 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-68b5cc5d-8e87-4b1a-9630-df7457ae746f |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081977817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.4081977817 |
Directory | /workspace/40.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/40.clkmgr_frequency.312346435 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 808478628 ps |
CPU time | 4.75 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:41 PM PDT 24 |
Peak memory | 200580 kb |
Host | smart-c21acd1c-fa9b-45c5-8947-183150db38e1 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312346435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.312346435 |
Directory | /workspace/40.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/40.clkmgr_frequency_timeout.2625094385 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 1824272977 ps |
CPU time | 9.56 seconds |
Started | Apr 04 03:48:38 PM PDT 24 |
Finished | Apr 04 03:48:48 PM PDT 24 |
Peak memory | 200700 kb |
Host | smart-17e5b553-f48e-4717-81da-76a86e66ca0e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625094385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t imeout.2625094385 |
Directory | /workspace/40.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.3538041691 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 65805459 ps |
CPU time | 1.12 seconds |
Started | Apr 04 03:48:36 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200592 kb |
Host | smart-111c61df-a9a1-435e-82d1-c2620118f954 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538041691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_idle_intersig_mubi.3538041691 |
Directory | /workspace/40.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.2756290968 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 14684693 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:48:44 PM PDT 24 |
Finished | Apr 04 03:48:45 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-bc98cf2d-0eba-4d82-9fbf-75dc8ed40063 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756290968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_clk_byp_req_intersig_mubi.2756290968 |
Directory | /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.3483929316 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 66817393 ps |
CPU time | 0.99 seconds |
Started | Apr 04 03:48:45 PM PDT 24 |
Finished | Apr 04 03:48:46 PM PDT 24 |
Peak memory | 200696 kb |
Host | smart-ea459ced-8af8-4766-b3fe-47650f03fffc |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483929316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_ctrl_intersig_mubi.3483929316 |
Directory | /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/40.clkmgr_peri.520366624 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 13615912 ps |
CPU time | 0.71 seconds |
Started | Apr 04 03:48:41 PM PDT 24 |
Finished | Apr 04 03:48:41 PM PDT 24 |
Peak memory | 200428 kb |
Host | smart-93c7b9a1-10ea-477b-bb3b-2d41107d88d0 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520366624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.520366624 |
Directory | /workspace/40.clkmgr_peri/latest |
Test location | /workspace/coverage/default/40.clkmgr_regwen.3451696944 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 1218717685 ps |
CPU time | 4.2 seconds |
Started | Apr 04 03:48:35 PM PDT 24 |
Finished | Apr 04 03:48:39 PM PDT 24 |
Peak memory | 200756 kb |
Host | smart-4446eb33-a7fa-49bc-bf59-966154460751 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451696944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.3451696944 |
Directory | /workspace/40.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/40.clkmgr_smoke.1092466587 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 25376049 ps |
CPU time | 0.85 seconds |
Started | Apr 04 03:48:45 PM PDT 24 |
Finished | Apr 04 03:48:47 PM PDT 24 |
Peak memory | 200688 kb |
Host | smart-88dea443-d0fb-4e95-bc4b-395e47f3b6b5 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092466587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.1092466587 |
Directory | /workspace/40.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/40.clkmgr_stress_all.3839036831 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 8469257609 ps |
CPU time | 61.41 seconds |
Started | Apr 04 03:48:41 PM PDT 24 |
Finished | Apr 04 03:49:43 PM PDT 24 |
Peak memory | 201028 kb |
Host | smart-d33b62b8-06fc-45a4-b68d-d797d909d816 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839036831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.3839036831 |
Directory | /workspace/40.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.2930527075 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 25888072296 ps |
CPU time | 285.55 seconds |
Started | Apr 04 03:48:41 PM PDT 24 |
Finished | Apr 04 03:53:27 PM PDT 24 |
Peak memory | 209320 kb |
Host | smart-7e65e19b-b6b3-4a50-9626-d10f544b49e5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2930527075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.2930527075 |
Directory | /workspace/40.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.clkmgr_trans.3309951554 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 65618842 ps |
CPU time | 0.98 seconds |
Started | Apr 04 03:48:41 PM PDT 24 |
Finished | Apr 04 03:48:42 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-24ba8edb-5c86-4f0c-9489-8d43e1dc4fe7 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309951554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.3309951554 |
Directory | /workspace/40.clkmgr_trans/latest |
Test location | /workspace/coverage/default/41.clkmgr_alert_test.4102704140 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 19808905 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:48:54 PM PDT 24 |
Finished | Apr 04 03:48:55 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-9ffdc29a-986c-4196-84d2-a482049f2031 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102704140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk mgr_alert_test.4102704140 |
Directory | /workspace/41.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.3291440542 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 18817620 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:48:43 PM PDT 24 |
Finished | Apr 04 03:48:44 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-025e4300-4bf2-4f87-aee6-f4ed20e2d090 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291440542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.3291440542 |
Directory | /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/41.clkmgr_clk_status.636021325 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 38227664 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:48:43 PM PDT 24 |
Finished | Apr 04 03:48:45 PM PDT 24 |
Peak memory | 199588 kb |
Host | smart-7352c5ce-5d0a-4d70-aa30-2592f6054472 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636021325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.636021325 |
Directory | /workspace/41.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/41.clkmgr_div_intersig_mubi.1440672155 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 91284718 ps |
CPU time | 1.06 seconds |
Started | Apr 04 03:48:41 PM PDT 24 |
Finished | Apr 04 03:48:42 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-66556bcb-b2da-46af-b754-a515fff55bd5 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440672155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.1440672155 |
Directory | /workspace/41.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/41.clkmgr_extclk.3667163243 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 70764829 ps |
CPU time | 0.99 seconds |
Started | Apr 04 03:48:46 PM PDT 24 |
Finished | Apr 04 03:48:47 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-f5c8a690-d7ba-4943-9459-76b904a56e4f |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667163243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.3667163243 |
Directory | /workspace/41.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/41.clkmgr_frequency.292616609 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 1521917127 ps |
CPU time | 10.96 seconds |
Started | Apr 04 03:48:41 PM PDT 24 |
Finished | Apr 04 03:48:52 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-d92be1b3-f1c8-4f79-ace0-af8067ef2b18 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292616609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.292616609 |
Directory | /workspace/41.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/41.clkmgr_frequency_timeout.3854929713 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 1099073754 ps |
CPU time | 8.13 seconds |
Started | Apr 04 03:48:41 PM PDT 24 |
Finished | Apr 04 03:48:49 PM PDT 24 |
Peak memory | 200760 kb |
Host | smart-f135c98b-e938-435a-80e4-332d644e7bc7 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854929713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t imeout.3854929713 |
Directory | /workspace/41.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.4115664738 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 16154894 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:48:45 PM PDT 24 |
Finished | Apr 04 03:48:47 PM PDT 24 |
Peak memory | 200696 kb |
Host | smart-cdb50dfb-2bdd-4258-8b89-84df80883a59 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115664738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.4115664738 |
Directory | /workspace/41.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.465763173 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 22589863 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:48:37 PM PDT 24 |
Finished | Apr 04 03:48:38 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-3751d5fc-ae7c-4d57-88f2-e26e727a4c9e |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465763173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.clkmgr_lc_clk_byp_req_intersig_mubi.465763173 |
Directory | /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.1402486566 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 161497711 ps |
CPU time | 1.3 seconds |
Started | Apr 04 03:48:40 PM PDT 24 |
Finished | Apr 04 03:48:42 PM PDT 24 |
Peak memory | 200528 kb |
Host | smart-867ad947-71b3-4463-9544-97e749b42dc8 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402486566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_ctrl_intersig_mubi.1402486566 |
Directory | /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/41.clkmgr_peri.4033614325 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 26041080 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:48:44 PM PDT 24 |
Finished | Apr 04 03:48:45 PM PDT 24 |
Peak memory | 200408 kb |
Host | smart-eaf0b984-1f71-4856-a44d-bd40a886f649 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033614325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.4033614325 |
Directory | /workspace/41.clkmgr_peri/latest |
Test location | /workspace/coverage/default/41.clkmgr_regwen.926146527 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 699166236 ps |
CPU time | 3.34 seconds |
Started | Apr 04 03:48:53 PM PDT 24 |
Finished | Apr 04 03:48:56 PM PDT 24 |
Peak memory | 200816 kb |
Host | smart-cfb8f840-96fc-47d3-b826-9d7716ba9dff |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926146527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.926146527 |
Directory | /workspace/41.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/41.clkmgr_smoke.2639174648 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 23334014 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:48:44 PM PDT 24 |
Finished | Apr 04 03:48:45 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-aa62caf9-85e3-448b-8bf7-92d9ad67bf5b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639174648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.2639174648 |
Directory | /workspace/41.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/41.clkmgr_stress_all.1720473350 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 61273340 ps |
CPU time | 1.04 seconds |
Started | Apr 04 03:48:48 PM PDT 24 |
Finished | Apr 04 03:48:49 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-792f3e44-43a6-4c0a-903e-cca0e6ba354d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720473350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.1720473350 |
Directory | /workspace/41.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.490811106 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 61731743683 ps |
CPU time | 572.31 seconds |
Started | Apr 04 03:48:51 PM PDT 24 |
Finished | Apr 04 03:58:24 PM PDT 24 |
Peak memory | 209272 kb |
Host | smart-0affe1c5-fcda-4540-8d56-dcd19796bfd0 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=490811106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.490811106 |
Directory | /workspace/41.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.clkmgr_trans.442493264 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 16829411 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:48:39 PM PDT 24 |
Finished | Apr 04 03:48:40 PM PDT 24 |
Peak memory | 200432 kb |
Host | smart-533d7d2f-b8fe-4c91-ab8e-5a042c8995f1 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442493264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.442493264 |
Directory | /workspace/41.clkmgr_trans/latest |
Test location | /workspace/coverage/default/42.clkmgr_alert_test.2280487195 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 32133842 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:48:58 PM PDT 24 |
Finished | Apr 04 03:48:59 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-d1949f94-3f97-4dfb-8e6b-01b35b05b72e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280487195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk mgr_alert_test.2280487195 |
Directory | /workspace/42.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.2104659819 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 52920640 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:48:48 PM PDT 24 |
Finished | Apr 04 03:48:50 PM PDT 24 |
Peak memory | 200576 kb |
Host | smart-4e16c373-ec55-4870-b256-9968d91e99b2 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104659819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.2104659819 |
Directory | /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/42.clkmgr_clk_status.499654849 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 33455504 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:48:50 PM PDT 24 |
Finished | Apr 04 03:48:51 PM PDT 24 |
Peak memory | 200364 kb |
Host | smart-7d22ee63-3900-4af1-a331-b3b7fa1c0ec9 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499654849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.499654849 |
Directory | /workspace/42.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/42.clkmgr_div_intersig_mubi.3851753474 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 222239289 ps |
CPU time | 1.5 seconds |
Started | Apr 04 03:48:55 PM PDT 24 |
Finished | Apr 04 03:48:57 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-d093ef53-eaeb-482b-9d39-84d4e16b9eca |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851753474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.3851753474 |
Directory | /workspace/42.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/42.clkmgr_extclk.1251356418 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 14338583 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:48:49 PM PDT 24 |
Finished | Apr 04 03:48:50 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-8b1bee75-4f35-42a0-b4bd-057f5961c0fd |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251356418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.1251356418 |
Directory | /workspace/42.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/42.clkmgr_frequency.3026575673 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 1155990641 ps |
CPU time | 8.77 seconds |
Started | Apr 04 03:48:50 PM PDT 24 |
Finished | Apr 04 03:48:59 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-6628ccbe-e952-4118-b4e8-99071a3287a1 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026575673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.3026575673 |
Directory | /workspace/42.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/42.clkmgr_frequency_timeout.3116677418 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 754821392 ps |
CPU time | 3.53 seconds |
Started | Apr 04 03:48:55 PM PDT 24 |
Finished | Apr 04 03:48:58 PM PDT 24 |
Peak memory | 200708 kb |
Host | smart-553485fc-e04b-41e3-89c5-9a7f9d8540fe |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116677418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t imeout.3116677418 |
Directory | /workspace/42.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.2650876437 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 27084304 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:48:54 PM PDT 24 |
Finished | Apr 04 03:48:55 PM PDT 24 |
Peak memory | 200172 kb |
Host | smart-1fad3a7f-ab04-4ea8-8524-ea7cace40f87 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650876437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.2650876437 |
Directory | /workspace/42.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.2236650390 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 54635224 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:48:51 PM PDT 24 |
Finished | Apr 04 03:48:52 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-fcbd3b7b-5dfd-4bda-8368-4be04edddb89 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236650390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 42.clkmgr_lc_clk_byp_req_intersig_mubi.2236650390 |
Directory | /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.977271715 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 29295126 ps |
CPU time | 0.9 seconds |
Started | Apr 04 03:48:50 PM PDT 24 |
Finished | Apr 04 03:48:51 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-13e1879d-46bf-4d9d-ba2b-5ef0d0dba440 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977271715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.clkmgr_lc_ctrl_intersig_mubi.977271715 |
Directory | /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/42.clkmgr_peri.3328920957 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 67796375 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:48:55 PM PDT 24 |
Finished | Apr 04 03:48:56 PM PDT 24 |
Peak memory | 200420 kb |
Host | smart-43f88b09-6689-4bd1-a492-b67a09deba8e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328920957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.3328920957 |
Directory | /workspace/42.clkmgr_peri/latest |
Test location | /workspace/coverage/default/42.clkmgr_regwen.781814333 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 898410313 ps |
CPU time | 5.07 seconds |
Started | Apr 04 03:48:58 PM PDT 24 |
Finished | Apr 04 03:49:04 PM PDT 24 |
Peak memory | 200812 kb |
Host | smart-88dba3f9-f6e7-4d78-9a04-a7cc24c34557 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781814333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.781814333 |
Directory | /workspace/42.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/42.clkmgr_smoke.1049778178 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 18419386 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:48:50 PM PDT 24 |
Finished | Apr 04 03:48:51 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-75ffcc55-c3aa-4fb0-af0e-889b50fab4e8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049778178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.1049778178 |
Directory | /workspace/42.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/42.clkmgr_stress_all.2475011354 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 156004199 ps |
CPU time | 1.67 seconds |
Started | Apr 04 03:48:51 PM PDT 24 |
Finished | Apr 04 03:48:54 PM PDT 24 |
Peak memory | 200712 kb |
Host | smart-523e32de-34c8-4cdc-b3cf-36d19c6d25ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475011354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.2475011354 |
Directory | /workspace/42.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.522016019 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 73690743310 ps |
CPU time | 433.83 seconds |
Started | Apr 04 03:48:52 PM PDT 24 |
Finished | Apr 04 03:56:06 PM PDT 24 |
Peak memory | 210452 kb |
Host | smart-2e4f0bd7-a829-4692-9dc2-242c07cc2027 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=522016019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.522016019 |
Directory | /workspace/42.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.clkmgr_trans.2212247885 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 18108177 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:48:54 PM PDT 24 |
Finished | Apr 04 03:48:55 PM PDT 24 |
Peak memory | 200540 kb |
Host | smart-76f04433-7486-4e56-97b6-84ff50a0569f |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212247885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.2212247885 |
Directory | /workspace/42.clkmgr_trans/latest |
Test location | /workspace/coverage/default/43.clkmgr_alert_test.2371633877 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 27852362 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:48:49 PM PDT 24 |
Finished | Apr 04 03:48:50 PM PDT 24 |
Peak memory | 200488 kb |
Host | smart-4e94ff48-999f-442e-8212-ee149b3a4e2b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371633877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk mgr_alert_test.2371633877 |
Directory | /workspace/43.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.4073169094 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 21478875 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:48:48 PM PDT 24 |
Finished | Apr 04 03:48:50 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-12c570b7-f38c-4e8f-8a8d-baff1dbd30eb |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073169094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.4073169094 |
Directory | /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/43.clkmgr_clk_status.253461519 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 15559331 ps |
CPU time | 0.71 seconds |
Started | Apr 04 03:48:47 PM PDT 24 |
Finished | Apr 04 03:48:48 PM PDT 24 |
Peak memory | 199580 kb |
Host | smart-38b16d5b-cb6c-4980-b455-09b1428519ec |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253461519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.253461519 |
Directory | /workspace/43.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/43.clkmgr_div_intersig_mubi.88712778 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 28046771 ps |
CPU time | 0.91 seconds |
Started | Apr 04 03:48:46 PM PDT 24 |
Finished | Apr 04 03:48:47 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-f5cd3458-6ae3-4e12-8c5d-6a87341e5896 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88712778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43 .clkmgr_div_intersig_mubi.88712778 |
Directory | /workspace/43.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/43.clkmgr_extclk.467085789 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 41992861 ps |
CPU time | 0.89 seconds |
Started | Apr 04 03:48:48 PM PDT 24 |
Finished | Apr 04 03:48:50 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-7b17cb21-6bda-47e6-8eb4-a08b4f6b6f11 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467085789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.467085789 |
Directory | /workspace/43.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/43.clkmgr_frequency.506348457 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 2608018590 ps |
CPU time | 10.59 seconds |
Started | Apr 04 03:48:58 PM PDT 24 |
Finished | Apr 04 03:49:08 PM PDT 24 |
Peak memory | 200872 kb |
Host | smart-124c4039-ad1e-4ac6-87f8-0bd85c99d780 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506348457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.506348457 |
Directory | /workspace/43.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/43.clkmgr_frequency_timeout.2526537891 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 1340305621 ps |
CPU time | 9.66 seconds |
Started | Apr 04 03:48:47 PM PDT 24 |
Finished | Apr 04 03:48:57 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-119d6ccb-179b-4f3d-8ebc-1edca6605f1b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526537891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t imeout.2526537891 |
Directory | /workspace/43.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1909431025 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 26946831 ps |
CPU time | 0.88 seconds |
Started | Apr 04 03:48:55 PM PDT 24 |
Finished | Apr 04 03:48:55 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-577d248a-70a2-456d-bc5d-e5433dab1084 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909431025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.1909431025 |
Directory | /workspace/43.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.2214740838 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 62135672 ps |
CPU time | 0.91 seconds |
Started | Apr 04 03:48:53 PM PDT 24 |
Finished | Apr 04 03:48:54 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-c8f81199-1f5e-4a7d-80c8-5c74d4feb9b5 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214740838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.clkmgr_lc_clk_byp_req_intersig_mubi.2214740838 |
Directory | /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.3238925293 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 28708892 ps |
CPU time | 0.95 seconds |
Started | Apr 04 03:48:50 PM PDT 24 |
Finished | Apr 04 03:48:51 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-beea80f2-c2ff-4639-b935-8a636452f260 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238925293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.clkmgr_lc_ctrl_intersig_mubi.3238925293 |
Directory | /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/43.clkmgr_peri.1057974435 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 16786318 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:48:49 PM PDT 24 |
Finished | Apr 04 03:48:50 PM PDT 24 |
Peak memory | 200372 kb |
Host | smart-00d9b9fc-4627-44c2-a1ff-3027ec6dea89 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057974435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.1057974435 |
Directory | /workspace/43.clkmgr_peri/latest |
Test location | /workspace/coverage/default/43.clkmgr_regwen.3311275792 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 121998562 ps |
CPU time | 1.3 seconds |
Started | Apr 04 03:48:54 PM PDT 24 |
Finished | Apr 04 03:48:55 PM PDT 24 |
Peak memory | 200296 kb |
Host | smart-366a9869-1e3d-4b5f-b624-af60716e909c |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311275792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.3311275792 |
Directory | /workspace/43.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/43.clkmgr_smoke.4013654456 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 42899833 ps |
CPU time | 0.88 seconds |
Started | Apr 04 03:48:55 PM PDT 24 |
Finished | Apr 04 03:48:56 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-3bfe639f-925d-4969-901a-6d711f46d418 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013654456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.4013654456 |
Directory | /workspace/43.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/43.clkmgr_stress_all.299608433 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 122105004 ps |
CPU time | 1.26 seconds |
Started | Apr 04 03:48:55 PM PDT 24 |
Finished | Apr 04 03:48:56 PM PDT 24 |
Peak memory | 200720 kb |
Host | smart-cfdf1f96-b6fe-45c3-9547-7f017e9fd847 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299608433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.299608433 |
Directory | /workspace/43.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.1524249250 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 105066280640 ps |
CPU time | 785.95 seconds |
Started | Apr 04 03:48:55 PM PDT 24 |
Finished | Apr 04 04:02:01 PM PDT 24 |
Peak memory | 213568 kb |
Host | smart-0b4d7f43-2003-49ba-bf19-3fe65e6228be |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1524249250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.1524249250 |
Directory | /workspace/43.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.clkmgr_trans.2502863050 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 27993720 ps |
CPU time | 1 seconds |
Started | Apr 04 03:48:51 PM PDT 24 |
Finished | Apr 04 03:48:52 PM PDT 24 |
Peak memory | 200572 kb |
Host | smart-ba2b080a-07c2-4867-8f0f-7f75643bb584 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502863050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.2502863050 |
Directory | /workspace/43.clkmgr_trans/latest |
Test location | /workspace/coverage/default/44.clkmgr_alert_test.1104910211 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 21654902 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:49:03 PM PDT 24 |
Finished | Apr 04 03:49:04 PM PDT 24 |
Peak memory | 200536 kb |
Host | smart-d06f8bf6-0562-4ab5-a28f-963949b224d2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104910211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk mgr_alert_test.1104910211 |
Directory | /workspace/44.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.1137355457 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 63720251 ps |
CPU time | 0.94 seconds |
Started | Apr 04 03:48:51 PM PDT 24 |
Finished | Apr 04 03:48:52 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-d4405d8a-90d5-4f2e-bd53-4f8d86ebb59a |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137355457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.1137355457 |
Directory | /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/44.clkmgr_clk_status.576965235 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 17580321 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:48:53 PM PDT 24 |
Finished | Apr 04 03:48:55 PM PDT 24 |
Peak memory | 200360 kb |
Host | smart-8f6deb50-24a5-4e5e-8618-8f094f109718 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576965235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.576965235 |
Directory | /workspace/44.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/44.clkmgr_div_intersig_mubi.2153766146 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 30464117 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:48:48 PM PDT 24 |
Finished | Apr 04 03:48:49 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-67de18db-ed32-43aa-99f9-1b3479805eba |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153766146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.2153766146 |
Directory | /workspace/44.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/44.clkmgr_extclk.362287211 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 33844641 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:48:50 PM PDT 24 |
Finished | Apr 04 03:48:51 PM PDT 24 |
Peak memory | 200708 kb |
Host | smart-60c41af2-9955-4ff2-856f-dea60c1d8f65 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362287211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.362287211 |
Directory | /workspace/44.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/44.clkmgr_frequency.3940889858 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 316911278 ps |
CPU time | 2.89 seconds |
Started | Apr 04 03:48:52 PM PDT 24 |
Finished | Apr 04 03:48:55 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-f31d61c7-bba5-4466-b7c4-4700ddafa3fd |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940889858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.3940889858 |
Directory | /workspace/44.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/44.clkmgr_frequency_timeout.2371186106 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 1346188567 ps |
CPU time | 6.82 seconds |
Started | Apr 04 03:48:50 PM PDT 24 |
Finished | Apr 04 03:48:57 PM PDT 24 |
Peak memory | 200764 kb |
Host | smart-1639fe3c-1796-4aaa-8461-a6b6634de92b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371186106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t imeout.2371186106 |
Directory | /workspace/44.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.3589313625 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 129781455 ps |
CPU time | 1.21 seconds |
Started | Apr 04 03:48:58 PM PDT 24 |
Finished | Apr 04 03:48:59 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-4f9f853c-cfc6-4a7f-a7db-3939a4deefd8 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589313625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_idle_intersig_mubi.3589313625 |
Directory | /workspace/44.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1020643029 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 30789108 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:48:49 PM PDT 24 |
Finished | Apr 04 03:48:50 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-51df437e-6c66-4f4c-9d03-5354ad18ec5b |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020643029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.clkmgr_lc_clk_byp_req_intersig_mubi.1020643029 |
Directory | /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.3140379062 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 68538898 ps |
CPU time | 0.97 seconds |
Started | Apr 04 03:48:49 PM PDT 24 |
Finished | Apr 04 03:48:51 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-afeac373-ed48-46b7-aee5-6f2ca4ff61ff |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140379062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.clkmgr_lc_ctrl_intersig_mubi.3140379062 |
Directory | /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/44.clkmgr_peri.1720185335 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 15710903 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:48:51 PM PDT 24 |
Finished | Apr 04 03:48:52 PM PDT 24 |
Peak memory | 200376 kb |
Host | smart-0d84b627-ef2d-4dd1-82cb-cc9d1f01a2fd |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720185335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.1720185335 |
Directory | /workspace/44.clkmgr_peri/latest |
Test location | /workspace/coverage/default/44.clkmgr_regwen.4058622613 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 592840980 ps |
CPU time | 3.64 seconds |
Started | Apr 04 03:49:04 PM PDT 24 |
Finished | Apr 04 03:49:08 PM PDT 24 |
Peak memory | 200788 kb |
Host | smart-e1a90482-529b-4723-b75b-aa61cd937f4d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058622613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.4058622613 |
Directory | /workspace/44.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/44.clkmgr_smoke.1430530717 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 24361445 ps |
CPU time | 1 seconds |
Started | Apr 04 03:48:55 PM PDT 24 |
Finished | Apr 04 03:48:57 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-fa58bfc3-043b-4720-9595-55a49eed5d3e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430530717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.1430530717 |
Directory | /workspace/44.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/44.clkmgr_stress_all.2514648203 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 7407378086 ps |
CPU time | 43.5 seconds |
Started | Apr 04 03:49:07 PM PDT 24 |
Finished | Apr 04 03:49:51 PM PDT 24 |
Peak memory | 201040 kb |
Host | smart-ce449aa2-050e-45ab-aae1-b5fedab08c12 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514648203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.2514648203 |
Directory | /workspace/44.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.625365382 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 17957507226 ps |
CPU time | 247.73 seconds |
Started | Apr 04 03:49:09 PM PDT 24 |
Finished | Apr 04 03:53:17 PM PDT 24 |
Peak memory | 209168 kb |
Host | smart-43f6297b-375d-425b-acf6-25245a461daf |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=625365382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.625365382 |
Directory | /workspace/44.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.clkmgr_trans.3267384548 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 128997931 ps |
CPU time | 1.39 seconds |
Started | Apr 04 03:48:48 PM PDT 24 |
Finished | Apr 04 03:48:50 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-6ac635be-422b-4c55-955a-1e9aa5b9655d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267384548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.3267384548 |
Directory | /workspace/44.clkmgr_trans/latest |
Test location | /workspace/coverage/default/45.clkmgr_alert_test.1018744433 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 31460697 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:49:05 PM PDT 24 |
Finished | Apr 04 03:49:06 PM PDT 24 |
Peak memory | 200420 kb |
Host | smart-5608a39c-ef58-4a56-b01e-abddfa274f2c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018744433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk mgr_alert_test.1018744433 |
Directory | /workspace/45.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.4108497235 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 49289861 ps |
CPU time | 0.96 seconds |
Started | Apr 04 03:49:11 PM PDT 24 |
Finished | Apr 04 03:49:12 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-6eebb538-3972-4905-8351-6cc131a665f1 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108497235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.4108497235 |
Directory | /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/45.clkmgr_clk_status.1889915043 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 38789062 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:49:04 PM PDT 24 |
Finished | Apr 04 03:49:05 PM PDT 24 |
Peak memory | 199608 kb |
Host | smart-aa920625-43e8-4a9e-91eb-28985450cd94 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889915043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1889915043 |
Directory | /workspace/45.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/45.clkmgr_div_intersig_mubi.2076064609 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 53435364 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:49:03 PM PDT 24 |
Finished | Apr 04 03:49:04 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-e23edefa-99fd-4a0f-a1a6-0818d3678512 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076064609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.2076064609 |
Directory | /workspace/45.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/45.clkmgr_extclk.1233518296 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 60003569 ps |
CPU time | 0.92 seconds |
Started | Apr 04 03:49:03 PM PDT 24 |
Finished | Apr 04 03:49:04 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-58a2c2ad-ff88-4d8d-afd8-77e9ace43a63 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233518296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.1233518296 |
Directory | /workspace/45.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/45.clkmgr_frequency.1863483971 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 197074824 ps |
CPU time | 2.38 seconds |
Started | Apr 04 03:49:02 PM PDT 24 |
Finished | Apr 04 03:49:04 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-225721ab-77a3-46d2-9213-1fcfd449c0b4 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863483971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.1863483971 |
Directory | /workspace/45.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/45.clkmgr_frequency_timeout.2959149658 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 2195285205 ps |
CPU time | 9.09 seconds |
Started | Apr 04 03:49:04 PM PDT 24 |
Finished | Apr 04 03:49:13 PM PDT 24 |
Peak memory | 200956 kb |
Host | smart-1ff93f6b-b013-4e43-be78-fb80fff98506 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959149658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t imeout.2959149658 |
Directory | /workspace/45.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.2921804006 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 20644902 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:49:03 PM PDT 24 |
Finished | Apr 04 03:49:04 PM PDT 24 |
Peak memory | 200476 kb |
Host | smart-6498a735-e169-4b5f-b087-81c672c945b6 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921804006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.2921804006 |
Directory | /workspace/45.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.2237170849 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 83380834 ps |
CPU time | 0.97 seconds |
Started | Apr 04 03:49:07 PM PDT 24 |
Finished | Apr 04 03:49:08 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-b1d64801-e116-4423-b11f-ba8959fc68b2 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237170849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.clkmgr_lc_clk_byp_req_intersig_mubi.2237170849 |
Directory | /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.751229342 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 33531883 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:49:05 PM PDT 24 |
Finished | Apr 04 03:49:06 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-42d6f4ce-c263-4fd9-959f-3d3a91de2657 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751229342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.clkmgr_lc_ctrl_intersig_mubi.751229342 |
Directory | /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/45.clkmgr_peri.4216598169 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 32504609 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:49:03 PM PDT 24 |
Finished | Apr 04 03:49:05 PM PDT 24 |
Peak memory | 200368 kb |
Host | smart-9b2b4c97-4302-461f-b9a0-d0d3e5e22666 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216598169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.4216598169 |
Directory | /workspace/45.clkmgr_peri/latest |
Test location | /workspace/coverage/default/45.clkmgr_regwen.3502693090 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 488623164 ps |
CPU time | 2.19 seconds |
Started | Apr 04 03:49:02 PM PDT 24 |
Finished | Apr 04 03:49:04 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-c4348ebe-f384-4403-8b7b-f1b2e7695f52 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502693090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.3502693090 |
Directory | /workspace/45.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/45.clkmgr_smoke.2867070777 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 41433424 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:49:08 PM PDT 24 |
Finished | Apr 04 03:49:09 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-41cea551-1d4b-43c4-9896-fa90a79a2d37 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867070777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.2867070777 |
Directory | /workspace/45.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/45.clkmgr_stress_all.2127716696 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 2942097784 ps |
CPU time | 22.58 seconds |
Started | Apr 04 03:49:02 PM PDT 24 |
Finished | Apr 04 03:49:25 PM PDT 24 |
Peak memory | 200976 kb |
Host | smart-e420caad-fd9f-47ea-b473-1d5ee960215a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127716696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.2127716696 |
Directory | /workspace/45.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.3892353830 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 85793016394 ps |
CPU time | 919.1 seconds |
Started | Apr 04 03:49:06 PM PDT 24 |
Finished | Apr 04 04:04:25 PM PDT 24 |
Peak memory | 209320 kb |
Host | smart-06dd9f58-eb9f-4ee6-91d3-ba4491cb84f6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3892353830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.3892353830 |
Directory | /workspace/45.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/45.clkmgr_trans.3508756583 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 48634848 ps |
CPU time | 1.01 seconds |
Started | Apr 04 03:49:01 PM PDT 24 |
Finished | Apr 04 03:49:02 PM PDT 24 |
Peak memory | 200584 kb |
Host | smart-016128c9-ba84-47ac-8855-1dedde751f7f |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508756583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.3508756583 |
Directory | /workspace/45.clkmgr_trans/latest |
Test location | /workspace/coverage/default/46.clkmgr_alert_test.3209584348 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 44607569 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:49:05 PM PDT 24 |
Finished | Apr 04 03:49:06 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-cc9b9d77-b8d9-4d37-85a1-c8b2c2626830 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209584348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk mgr_alert_test.3209584348 |
Directory | /workspace/46.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.188023766 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 37767482 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:49:04 PM PDT 24 |
Finished | Apr 04 03:49:06 PM PDT 24 |
Peak memory | 200612 kb |
Host | smart-630a4a5d-3214-4d1b-8412-6189d7225b25 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188023766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.188023766 |
Directory | /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/46.clkmgr_clk_status.3298807189 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 23941253 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:49:02 PM PDT 24 |
Finished | Apr 04 03:49:03 PM PDT 24 |
Peak memory | 199612 kb |
Host | smart-f64f77e9-c586-4303-b1cb-477bc991cd1e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298807189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.3298807189 |
Directory | /workspace/46.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/46.clkmgr_div_intersig_mubi.3535078537 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 22089485 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:49:04 PM PDT 24 |
Finished | Apr 04 03:49:05 PM PDT 24 |
Peak memory | 200524 kb |
Host | smart-99daab77-bc77-46d0-a3d9-7c1a4f339629 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535078537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.3535078537 |
Directory | /workspace/46.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/46.clkmgr_extclk.1129903972 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 93312603 ps |
CPU time | 1.04 seconds |
Started | Apr 04 03:49:03 PM PDT 24 |
Finished | Apr 04 03:49:04 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-62b08602-7914-44e8-b449-8a5e03314953 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129903972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.1129903972 |
Directory | /workspace/46.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/46.clkmgr_frequency.727067371 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 2241533412 ps |
CPU time | 16.19 seconds |
Started | Apr 04 03:49:03 PM PDT 24 |
Finished | Apr 04 03:49:20 PM PDT 24 |
Peak memory | 200840 kb |
Host | smart-7dc5281b-161e-4f25-934a-035a6fa14083 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727067371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.727067371 |
Directory | /workspace/46.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/46.clkmgr_frequency_timeout.1779800639 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 741681899 ps |
CPU time | 5.55 seconds |
Started | Apr 04 03:49:07 PM PDT 24 |
Finished | Apr 04 03:49:13 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-74fce399-0586-440d-9379-ca5c4cde753d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779800639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t imeout.1779800639 |
Directory | /workspace/46.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.4201204815 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 17101961 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:49:04 PM PDT 24 |
Finished | Apr 04 03:49:05 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-aa9a9e6e-e5dd-40d9-a67c-94fa14b8bbc7 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201204815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.4201204815 |
Directory | /workspace/46.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.1246814281 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 39080310 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:49:04 PM PDT 24 |
Finished | Apr 04 03:49:05 PM PDT 24 |
Peak memory | 200548 kb |
Host | smart-8fc44a7f-a45e-4506-889c-b194ba7b855a |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246814281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_clk_byp_req_intersig_mubi.1246814281 |
Directory | /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.1137029923 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 20457214 ps |
CPU time | 0.9 seconds |
Started | Apr 04 03:49:01 PM PDT 24 |
Finished | Apr 04 03:49:02 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-c288a570-8cd8-4734-9bf1-aff63a96d30d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137029923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_ctrl_intersig_mubi.1137029923 |
Directory | /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/46.clkmgr_peri.2133611443 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 21060075 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:49:05 PM PDT 24 |
Finished | Apr 04 03:49:06 PM PDT 24 |
Peak memory | 200364 kb |
Host | smart-95dedfc4-6c34-403c-8432-61945e22a7f2 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133611443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.2133611443 |
Directory | /workspace/46.clkmgr_peri/latest |
Test location | /workspace/coverage/default/46.clkmgr_regwen.1599139294 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 743542708 ps |
CPU time | 3.14 seconds |
Started | Apr 04 03:49:02 PM PDT 24 |
Finished | Apr 04 03:49:05 PM PDT 24 |
Peak memory | 200740 kb |
Host | smart-ab659e81-ea7f-417c-a0fc-7d7ab10d2f40 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599139294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.1599139294 |
Directory | /workspace/46.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/46.clkmgr_smoke.1097436108 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 137475323 ps |
CPU time | 1.1 seconds |
Started | Apr 04 03:49:08 PM PDT 24 |
Finished | Apr 04 03:49:09 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-03f0b5a5-d7c1-4885-8d4b-c90513ee8c84 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097436108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.1097436108 |
Directory | /workspace/46.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/46.clkmgr_stress_all.1302049061 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 3649967475 ps |
CPU time | 26.04 seconds |
Started | Apr 04 03:49:08 PM PDT 24 |
Finished | Apr 04 03:49:34 PM PDT 24 |
Peak memory | 200904 kb |
Host | smart-5de9b411-3c98-4746-a98c-e384003bd515 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302049061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.1302049061 |
Directory | /workspace/46.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.1473520918 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 1004761802987 ps |
CPU time | 3255.9 seconds |
Started | Apr 04 03:49:07 PM PDT 24 |
Finished | Apr 04 04:43:24 PM PDT 24 |
Peak memory | 217444 kb |
Host | smart-aeac0940-22d8-4e49-a304-af493a548f9a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1473520918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.1473520918 |
Directory | /workspace/46.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.clkmgr_trans.3841814360 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 44138490 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:49:03 PM PDT 24 |
Finished | Apr 04 03:49:04 PM PDT 24 |
Peak memory | 200492 kb |
Host | smart-675d4220-101f-4d60-8117-355d8b2303fa |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841814360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.3841814360 |
Directory | /workspace/46.clkmgr_trans/latest |
Test location | /workspace/coverage/default/47.clkmgr_alert_test.2316874416 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 25318044 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:49:13 PM PDT 24 |
Finished | Apr 04 03:49:14 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-542565f9-7e3c-4812-ab03-7168e9694e3e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316874416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk mgr_alert_test.2316874416 |
Directory | /workspace/47.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.562855356 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 27925920 ps |
CPU time | 0.99 seconds |
Started | Apr 04 03:49:15 PM PDT 24 |
Finished | Apr 04 03:49:16 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-9e84e1a4-00e4-4d01-b1d0-f9bacb2057e7 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562855356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.562855356 |
Directory | /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/47.clkmgr_clk_status.2375709426 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 17314349 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:49:02 PM PDT 24 |
Finished | Apr 04 03:49:03 PM PDT 24 |
Peak memory | 199596 kb |
Host | smart-3a931bec-2eb6-437a-815e-66d884568ba3 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375709426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.2375709426 |
Directory | /workspace/47.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/47.clkmgr_div_intersig_mubi.3715625132 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 16769574 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:49:14 PM PDT 24 |
Finished | Apr 04 03:49:14 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-c491491d-bc74-460c-8231-0cf5607b1b56 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715625132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.3715625132 |
Directory | /workspace/47.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/47.clkmgr_extclk.3040008127 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 112213193 ps |
CPU time | 1.05 seconds |
Started | Apr 04 03:49:03 PM PDT 24 |
Finished | Apr 04 03:49:04 PM PDT 24 |
Peak memory | 200636 kb |
Host | smart-0a1c6775-0208-4667-9924-7da84bae83a0 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040008127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.3040008127 |
Directory | /workspace/47.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/47.clkmgr_frequency.2935797915 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 1640341953 ps |
CPU time | 12.38 seconds |
Started | Apr 04 03:49:02 PM PDT 24 |
Finished | Apr 04 03:49:15 PM PDT 24 |
Peak memory | 200580 kb |
Host | smart-9ea523cd-8b8d-4ec5-b27b-00a6c3a922f3 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935797915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.2935797915 |
Directory | /workspace/47.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/47.clkmgr_frequency_timeout.2112952579 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 146104781 ps |
CPU time | 1.35 seconds |
Started | Apr 04 03:49:08 PM PDT 24 |
Finished | Apr 04 03:49:09 PM PDT 24 |
Peak memory | 200592 kb |
Host | smart-42320f8e-9334-4304-9ac9-6052e9d61372 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112952579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t imeout.2112952579 |
Directory | /workspace/47.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.2382886719 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 159526926 ps |
CPU time | 1.26 seconds |
Started | Apr 04 03:49:07 PM PDT 24 |
Finished | Apr 04 03:49:09 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-97f4f87b-1b0e-41d6-a6a4-540d03b65f3d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382886719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.2382886719 |
Directory | /workspace/47.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.3304146960 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 15297834 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:49:16 PM PDT 24 |
Finished | Apr 04 03:49:17 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-e572f490-60af-4929-8b89-6cc9bceb8109 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304146960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.clkmgr_lc_clk_byp_req_intersig_mubi.3304146960 |
Directory | /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.638950627 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 16312782 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:49:00 PM PDT 24 |
Finished | Apr 04 03:49:01 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-b1e33910-2f23-4f13-9496-227353fac3dd |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638950627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.clkmgr_lc_ctrl_intersig_mubi.638950627 |
Directory | /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/47.clkmgr_peri.1217577753 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 18188892 ps |
CPU time | 0.69 seconds |
Started | Apr 04 03:49:04 PM PDT 24 |
Finished | Apr 04 03:49:05 PM PDT 24 |
Peak memory | 200304 kb |
Host | smart-a67ba171-cff7-4235-a09c-427be9cd6e71 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217577753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.1217577753 |
Directory | /workspace/47.clkmgr_peri/latest |
Test location | /workspace/coverage/default/47.clkmgr_regwen.1350209691 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 798208178 ps |
CPU time | 4.82 seconds |
Started | Apr 04 03:49:17 PM PDT 24 |
Finished | Apr 04 03:49:22 PM PDT 24 |
Peak memory | 200768 kb |
Host | smart-cdb3a93d-8981-4eb5-b801-04ac1f1dc636 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350209691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.1350209691 |
Directory | /workspace/47.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/47.clkmgr_smoke.2207607907 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 38573662 ps |
CPU time | 0.9 seconds |
Started | Apr 04 03:49:01 PM PDT 24 |
Finished | Apr 04 03:49:02 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-024ba199-f557-4de0-b567-9c9c2f993dba |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207607907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.2207607907 |
Directory | /workspace/47.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/47.clkmgr_stress_all.4121243378 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 3816194883 ps |
CPU time | 25.77 seconds |
Started | Apr 04 03:49:14 PM PDT 24 |
Finished | Apr 04 03:49:40 PM PDT 24 |
Peak memory | 201000 kb |
Host | smart-18ac2b0c-a453-4676-9617-56087802575d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121243378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.4121243378 |
Directory | /workspace/47.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/47.clkmgr_trans.973334572 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 35536017 ps |
CPU time | 0.94 seconds |
Started | Apr 04 03:49:00 PM PDT 24 |
Finished | Apr 04 03:49:01 PM PDT 24 |
Peak memory | 200576 kb |
Host | smart-2912adaf-ebf9-459d-851c-3619cdaaa243 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973334572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.973334572 |
Directory | /workspace/47.clkmgr_trans/latest |
Test location | /workspace/coverage/default/48.clkmgr_alert_test.289516728 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 13243692 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:49:17 PM PDT 24 |
Finished | Apr 04 03:49:18 PM PDT 24 |
Peak memory | 200468 kb |
Host | smart-9bed42e5-3e3d-4aea-b456-be91ab7291a7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289516728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkm gr_alert_test.289516728 |
Directory | /workspace/48.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.2450416499 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 98071205 ps |
CPU time | 1.15 seconds |
Started | Apr 04 03:49:14 PM PDT 24 |
Finished | Apr 04 03:49:15 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-ccfd5376-9186-4190-a328-c5e40cab22e5 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450416499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.2450416499 |
Directory | /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/48.clkmgr_clk_status.3375894261 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 44104188 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:49:17 PM PDT 24 |
Finished | Apr 04 03:49:18 PM PDT 24 |
Peak memory | 199496 kb |
Host | smart-00488258-6410-4038-b8d3-5e0e8fd2aa96 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375894261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.3375894261 |
Directory | /workspace/48.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/48.clkmgr_div_intersig_mubi.4039015991 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 37501490 ps |
CPU time | 0.92 seconds |
Started | Apr 04 03:49:14 PM PDT 24 |
Finished | Apr 04 03:49:15 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-35e8ae02-8c88-4c1d-a759-5f00eca114f2 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039015991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.4039015991 |
Directory | /workspace/48.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/48.clkmgr_extclk.4012395881 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 56158815 ps |
CPU time | 0.89 seconds |
Started | Apr 04 03:49:15 PM PDT 24 |
Finished | Apr 04 03:49:16 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-4634bceb-2081-4d64-8126-6e54708c5626 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012395881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.4012395881 |
Directory | /workspace/48.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/48.clkmgr_frequency.1215573464 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 2481109868 ps |
CPU time | 12.27 seconds |
Started | Apr 04 03:49:13 PM PDT 24 |
Finished | Apr 04 03:49:25 PM PDT 24 |
Peak memory | 200840 kb |
Host | smart-39d6796f-a4af-4ace-a04f-655387ea7a71 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215573464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1215573464 |
Directory | /workspace/48.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/48.clkmgr_frequency_timeout.2309941521 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 261440077 ps |
CPU time | 2.42 seconds |
Started | Apr 04 03:49:17 PM PDT 24 |
Finished | Apr 04 03:49:19 PM PDT 24 |
Peak memory | 200704 kb |
Host | smart-2e78c467-2027-48ba-80f1-45bae4b60f26 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309941521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t imeout.2309941521 |
Directory | /workspace/48.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.34889360 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 63851313 ps |
CPU time | 1.04 seconds |
Started | Apr 04 03:49:15 PM PDT 24 |
Finished | Apr 04 03:49:16 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-3ca09d54-a6ef-490d-8455-59e755f9fadf |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34889360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .clkmgr_idle_intersig_mubi.34889360 |
Directory | /workspace/48.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.3183811859 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 15577111 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:49:14 PM PDT 24 |
Finished | Apr 04 03:49:15 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-8b6f6ba1-cb0c-45bd-b6d5-69bd12a72231 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183811859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.clkmgr_lc_clk_byp_req_intersig_mubi.3183811859 |
Directory | /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.2018644114 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 63347580 ps |
CPU time | 0.94 seconds |
Started | Apr 04 03:49:17 PM PDT 24 |
Finished | Apr 04 03:49:18 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-653b73cb-86f8-4d89-bc63-8ee4032b0662 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018644114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.clkmgr_lc_ctrl_intersig_mubi.2018644114 |
Directory | /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/48.clkmgr_peri.2801439626 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 17119969 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:49:14 PM PDT 24 |
Finished | Apr 04 03:49:15 PM PDT 24 |
Peak memory | 200416 kb |
Host | smart-c7f07620-e49a-4466-a39e-b04fc72425e2 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801439626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.2801439626 |
Directory | /workspace/48.clkmgr_peri/latest |
Test location | /workspace/coverage/default/48.clkmgr_regwen.1680394819 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 863246645 ps |
CPU time | 3.26 seconds |
Started | Apr 04 03:49:13 PM PDT 24 |
Finished | Apr 04 03:49:16 PM PDT 24 |
Peak memory | 200720 kb |
Host | smart-78ec1acf-1c8f-484b-ba1c-99cdc03ef2e7 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680394819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.1680394819 |
Directory | /workspace/48.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/48.clkmgr_smoke.1154699253 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 18451798 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:49:13 PM PDT 24 |
Finished | Apr 04 03:49:14 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-616e392f-e083-47c8-b306-15a733bf4e6b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154699253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.1154699253 |
Directory | /workspace/48.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/48.clkmgr_stress_all.1894532404 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 8284242312 ps |
CPU time | 29.59 seconds |
Started | Apr 04 03:49:17 PM PDT 24 |
Finished | Apr 04 03:49:46 PM PDT 24 |
Peak memory | 201036 kb |
Host | smart-55451c41-5a70-4ec0-a894-5db656bfe0bb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894532404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.1894532404 |
Directory | /workspace/48.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.3450742767 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 179414346203 ps |
CPU time | 1090.84 seconds |
Started | Apr 04 03:49:17 PM PDT 24 |
Finished | Apr 04 04:07:28 PM PDT 24 |
Peak memory | 214024 kb |
Host | smart-d02b3a00-9590-4b6b-821e-bfec74620710 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3450742767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.3450742767 |
Directory | /workspace/48.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.clkmgr_trans.1601956705 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 47244241 ps |
CPU time | 1 seconds |
Started | Apr 04 03:49:14 PM PDT 24 |
Finished | Apr 04 03:49:15 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-e841190d-6c3d-471d-b2cd-6b1d1fd83759 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601956705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.1601956705 |
Directory | /workspace/48.clkmgr_trans/latest |
Test location | /workspace/coverage/default/49.clkmgr_alert_test.3639781353 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 21299823 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:49:29 PM PDT 24 |
Finished | Apr 04 03:49:30 PM PDT 24 |
Peak memory | 200500 kb |
Host | smart-05bb4bcf-728c-4554-9990-4ddae5af271f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639781353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk mgr_alert_test.3639781353 |
Directory | /workspace/49.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.75116264 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 46014012 ps |
CPU time | 0.95 seconds |
Started | Apr 04 03:49:27 PM PDT 24 |
Finished | Apr 04 03:49:28 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-7a24a779-f717-49e9-98f2-b8fa8ea85f6e |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75116264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.clkmgr_clk_handshake_intersig_mubi.75116264 |
Directory | /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/49.clkmgr_clk_status.652621205 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 47689258 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:49:29 PM PDT 24 |
Finished | Apr 04 03:49:30 PM PDT 24 |
Peak memory | 199600 kb |
Host | smart-4a81f744-664b-4c06-81ee-522a68f25dc8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652621205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.652621205 |
Directory | /workspace/49.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/49.clkmgr_div_intersig_mubi.2468613093 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 20113587 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:49:31 PM PDT 24 |
Finished | Apr 04 03:49:32 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-c99a3f62-0a98-4a41-b74e-912494541d39 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468613093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.2468613093 |
Directory | /workspace/49.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/49.clkmgr_extclk.4174705623 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 22180065 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:49:15 PM PDT 24 |
Finished | Apr 04 03:49:16 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-af2a94bf-0aca-4013-95fe-6e87ab96aeec |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174705623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.4174705623 |
Directory | /workspace/49.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/49.clkmgr_frequency.335510382 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 929952652 ps |
CPU time | 5.5 seconds |
Started | Apr 04 03:49:16 PM PDT 24 |
Finished | Apr 04 03:49:22 PM PDT 24 |
Peak memory | 200576 kb |
Host | smart-b4c6003b-ccc6-4af1-b289-384a16e72538 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335510382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.335510382 |
Directory | /workspace/49.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/49.clkmgr_frequency_timeout.2277392727 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 1542376614 ps |
CPU time | 4.82 seconds |
Started | Apr 04 03:49:16 PM PDT 24 |
Finished | Apr 04 03:49:21 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-e0b7ca68-6bee-413f-b29e-ef5b6f4c0451 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277392727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t imeout.2277392727 |
Directory | /workspace/49.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.2437113113 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 21597826 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:49:27 PM PDT 24 |
Finished | Apr 04 03:49:28 PM PDT 24 |
Peak memory | 200452 kb |
Host | smart-42cb63a0-6906-41c0-84e4-d90f74c95f2b |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437113113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.2437113113 |
Directory | /workspace/49.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.2502898590 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 24820388 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:49:30 PM PDT 24 |
Finished | Apr 04 03:49:31 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-f53063eb-9c82-4cc8-8a3f-57c605867c03 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502898590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.clkmgr_lc_clk_byp_req_intersig_mubi.2502898590 |
Directory | /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3793085171 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 21189477 ps |
CPU time | 0.74 seconds |
Started | Apr 04 03:49:26 PM PDT 24 |
Finished | Apr 04 03:49:27 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-6d60f55d-e8a4-4942-b159-48d953549834 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793085171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.clkmgr_lc_ctrl_intersig_mubi.3793085171 |
Directory | /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/49.clkmgr_peri.1043547370 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 53322961 ps |
CPU time | 0.88 seconds |
Started | Apr 04 03:49:16 PM PDT 24 |
Finished | Apr 04 03:49:17 PM PDT 24 |
Peak memory | 200412 kb |
Host | smart-fef0bd61-e162-4bff-8324-c3052a152724 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043547370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.1043547370 |
Directory | /workspace/49.clkmgr_peri/latest |
Test location | /workspace/coverage/default/49.clkmgr_regwen.2067407620 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 1035598665 ps |
CPU time | 5.87 seconds |
Started | Apr 04 03:49:26 PM PDT 24 |
Finished | Apr 04 03:49:32 PM PDT 24 |
Peak memory | 200816 kb |
Host | smart-76feccd3-ab0e-43d3-b9ca-f5078be96ee0 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067407620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.2067407620 |
Directory | /workspace/49.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/49.clkmgr_smoke.3932412022 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 19824117 ps |
CPU time | 0.82 seconds |
Started | Apr 04 03:49:17 PM PDT 24 |
Finished | Apr 04 03:49:18 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-b1a3f37e-0037-46a3-9d9d-124828e42d46 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932412022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.3932412022 |
Directory | /workspace/49.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/49.clkmgr_stress_all.4236281501 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 2422895140 ps |
CPU time | 9.88 seconds |
Started | Apr 04 03:49:27 PM PDT 24 |
Finished | Apr 04 03:49:37 PM PDT 24 |
Peak memory | 200824 kb |
Host | smart-5d5af86c-e6a5-4c47-ba73-397dbaa33504 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236281501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.4236281501 |
Directory | /workspace/49.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.4066969968 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 775823608084 ps |
CPU time | 2700.95 seconds |
Started | Apr 04 03:49:25 PM PDT 24 |
Finished | Apr 04 04:34:26 PM PDT 24 |
Peak memory | 217344 kb |
Host | smart-b35dc833-439a-4433-b511-43e1d3c13298 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4066969968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.4066969968 |
Directory | /workspace/49.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.clkmgr_trans.775093273 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 15146413 ps |
CPU time | 0.71 seconds |
Started | Apr 04 03:49:15 PM PDT 24 |
Finished | Apr 04 03:49:16 PM PDT 24 |
Peak memory | 200440 kb |
Host | smart-7767ac3d-984d-4bc3-915e-da86aeaa2a9c |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775093273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.775093273 |
Directory | /workspace/49.clkmgr_trans/latest |
Test location | /workspace/coverage/default/5.clkmgr_alert_test.290939161 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 51701621 ps |
CPU time | 0.81 seconds |
Started | Apr 04 03:46:32 PM PDT 24 |
Finished | Apr 04 03:46:33 PM PDT 24 |
Peak memory | 200476 kb |
Host | smart-07df2f11-4713-4fe3-8c83-2f2bba3fb0d0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290939161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmg r_alert_test.290939161 |
Directory | /workspace/5.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.715451466 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 129710471 ps |
CPU time | 1.15 seconds |
Started | Apr 04 03:46:25 PM PDT 24 |
Finished | Apr 04 03:46:26 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-ea2a7b37-b646-46a3-97af-cb6eaadb9b4b |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715451466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.715451466 |
Directory | /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/5.clkmgr_clk_status.2528654409 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 14238949 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:46:28 PM PDT 24 |
Finished | Apr 04 03:46:29 PM PDT 24 |
Peak memory | 200328 kb |
Host | smart-ea850454-1aa2-4023-bcec-ec63f6f66979 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528654409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.2528654409 |
Directory | /workspace/5.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/5.clkmgr_div_intersig_mubi.3088456150 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 86082789 ps |
CPU time | 1 seconds |
Started | Apr 04 03:46:31 PM PDT 24 |
Finished | Apr 04 03:46:32 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-d17f8b3e-8597-4e49-b59e-e7ea591db6cd |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088456150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.3088456150 |
Directory | /workspace/5.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/5.clkmgr_extclk.3304887438 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 52762672 ps |
CPU time | 0.92 seconds |
Started | Apr 04 03:46:26 PM PDT 24 |
Finished | Apr 04 03:46:27 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-76eac4fb-86ac-48c0-b591-32348f39f7a5 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304887438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.3304887438 |
Directory | /workspace/5.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/5.clkmgr_frequency.1792599994 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 1735323774 ps |
CPU time | 7.62 seconds |
Started | Apr 04 03:46:27 PM PDT 24 |
Finished | Apr 04 03:46:35 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-72afac85-248c-4cf1-8cc1-8f57fa6f4312 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792599994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.1792599994 |
Directory | /workspace/5.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/5.clkmgr_frequency_timeout.2796516478 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 1603162533 ps |
CPU time | 6.84 seconds |
Started | Apr 04 03:46:31 PM PDT 24 |
Finished | Apr 04 03:46:38 PM PDT 24 |
Peak memory | 200712 kb |
Host | smart-6bbb7ba7-d56b-48b4-b488-792167e5a20c |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796516478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti meout.2796516478 |
Directory | /workspace/5.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.2251687758 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 33330086 ps |
CPU time | 1.04 seconds |
Started | Apr 04 03:46:26 PM PDT 24 |
Finished | Apr 04 03:46:27 PM PDT 24 |
Peak memory | 200556 kb |
Host | smart-5dedbc19-b52a-44fb-9ecf-1cb88709bf5c |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251687758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.2251687758 |
Directory | /workspace/5.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.2240344920 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 40315565 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:46:24 PM PDT 24 |
Finished | Apr 04 03:46:25 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-48c9d82b-d51a-48f1-84e3-1b011e303edc |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240344920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.clkmgr_lc_clk_byp_req_intersig_mubi.2240344920 |
Directory | /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.2887296467 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 64706581 ps |
CPU time | 0.91 seconds |
Started | Apr 04 03:46:24 PM PDT 24 |
Finished | Apr 04 03:46:25 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-0beecd83-6b6c-4e3d-94c7-3f071ddbf8c0 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887296467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.clkmgr_lc_ctrl_intersig_mubi.2887296467 |
Directory | /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/5.clkmgr_peri.2590984867 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 24083156 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:46:32 PM PDT 24 |
Finished | Apr 04 03:46:33 PM PDT 24 |
Peak memory | 200364 kb |
Host | smart-c3e03707-ddfc-4e82-a67f-c87df3d38fab |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590984867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.2590984867 |
Directory | /workspace/5.clkmgr_peri/latest |
Test location | /workspace/coverage/default/5.clkmgr_regwen.3142973969 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 386853425 ps |
CPU time | 2.27 seconds |
Started | Apr 04 03:46:27 PM PDT 24 |
Finished | Apr 04 03:46:29 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-3cfb2548-94d4-4311-a13b-81da75ce3d51 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142973969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.3142973969 |
Directory | /workspace/5.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/5.clkmgr_smoke.1582371279 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 24702929 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:46:27 PM PDT 24 |
Finished | Apr 04 03:46:28 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-41728d78-e4d3-4132-b747-2bb08dc9b9ca |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582371279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.1582371279 |
Directory | /workspace/5.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/5.clkmgr_stress_all.3551697851 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 1641312054 ps |
CPU time | 12.71 seconds |
Started | Apr 04 03:46:26 PM PDT 24 |
Finished | Apr 04 03:46:39 PM PDT 24 |
Peak memory | 200816 kb |
Host | smart-840fc4f3-d920-421a-af8f-00a19e684fa6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551697851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.3551697851 |
Directory | /workspace/5.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.2407620989 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 5337039260 ps |
CPU time | 32.86 seconds |
Started | Apr 04 03:46:28 PM PDT 24 |
Finished | Apr 04 03:47:01 PM PDT 24 |
Peak memory | 209224 kb |
Host | smart-0e8fdff2-acce-4fd5-bebc-0163ac7b7f4e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2407620989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.2407620989 |
Directory | /workspace/5.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.clkmgr_trans.3098752814 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 20624704 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:46:25 PM PDT 24 |
Finished | Apr 04 03:46:26 PM PDT 24 |
Peak memory | 200452 kb |
Host | smart-08b72579-1d04-41ba-8da8-519850246f65 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098752814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.3098752814 |
Directory | /workspace/5.clkmgr_trans/latest |
Test location | /workspace/coverage/default/6.clkmgr_alert_test.3892477942 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 20139339 ps |
CPU time | 0.73 seconds |
Started | Apr 04 03:46:30 PM PDT 24 |
Finished | Apr 04 03:46:30 PM PDT 24 |
Peak memory | 200444 kb |
Host | smart-42753b13-6eab-4e48-867a-897629e68060 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892477942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm gr_alert_test.3892477942 |
Directory | /workspace/6.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.375701203 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 77573016 ps |
CPU time | 1.07 seconds |
Started | Apr 04 03:46:29 PM PDT 24 |
Finished | Apr 04 03:46:31 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-51e52fef-f649-42df-a5c0-4c816c85e4f2 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375701203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.375701203 |
Directory | /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/6.clkmgr_clk_status.499269016 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 44785959 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:46:27 PM PDT 24 |
Finished | Apr 04 03:46:28 PM PDT 24 |
Peak memory | 200308 kb |
Host | smart-b58a7779-4777-4df3-8b83-5bcea7a75a2a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499269016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.499269016 |
Directory | /workspace/6.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/6.clkmgr_div_intersig_mubi.3898683492 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 54221859 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:46:31 PM PDT 24 |
Finished | Apr 04 03:46:31 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-fafeda81-8e7a-4d6a-83b3-d6fa0267b678 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898683492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.3898683492 |
Directory | /workspace/6.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/6.clkmgr_extclk.794404072 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 26915805 ps |
CPU time | 0.9 seconds |
Started | Apr 04 03:46:32 PM PDT 24 |
Finished | Apr 04 03:46:33 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-6e78f7b6-6393-4111-a191-4de1d357b5c8 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794404072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.794404072 |
Directory | /workspace/6.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/6.clkmgr_frequency.652568398 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 2244340818 ps |
CPU time | 16.88 seconds |
Started | Apr 04 03:46:23 PM PDT 24 |
Finished | Apr 04 03:46:40 PM PDT 24 |
Peak memory | 200840 kb |
Host | smart-f5311808-f4b0-4f39-a8c1-c16e08d922a0 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652568398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.652568398 |
Directory | /workspace/6.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/6.clkmgr_frequency_timeout.686019182 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 854884827 ps |
CPU time | 6.56 seconds |
Started | Apr 04 03:46:31 PM PDT 24 |
Finished | Apr 04 03:46:37 PM PDT 24 |
Peak memory | 200712 kb |
Host | smart-4b93c374-dbaf-42f8-942d-fdcb4eb1370a |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686019182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_tim eout.686019182 |
Directory | /workspace/6.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.3570050905 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 59650282 ps |
CPU time | 0.96 seconds |
Started | Apr 04 03:46:35 PM PDT 24 |
Finished | Apr 04 03:46:36 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-a68a744d-c69e-4737-a668-a8f81de16728 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570050905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.3570050905 |
Directory | /workspace/6.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.216537871 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 27076532 ps |
CPU time | 0.92 seconds |
Started | Apr 04 03:46:33 PM PDT 24 |
Finished | Apr 04 03:46:34 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-afff4fc3-1e24-486c-9cc0-30b41423153d |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216537871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.clkmgr_lc_clk_byp_req_intersig_mubi.216537871 |
Directory | /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.2585981530 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 100185057 ps |
CPU time | 1.1 seconds |
Started | Apr 04 03:46:29 PM PDT 24 |
Finished | Apr 04 03:46:30 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-52e13dcf-59e2-43fc-8833-fc550709770a |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585981530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 6.clkmgr_lc_ctrl_intersig_mubi.2585981530 |
Directory | /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/6.clkmgr_peri.1611563721 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 17755151 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:46:35 PM PDT 24 |
Finished | Apr 04 03:46:36 PM PDT 24 |
Peak memory | 200364 kb |
Host | smart-207fc26a-de69-4734-864b-bc7a5c730fbb |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611563721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.1611563721 |
Directory | /workspace/6.clkmgr_peri/latest |
Test location | /workspace/coverage/default/6.clkmgr_regwen.3761724846 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 457979429 ps |
CPU time | 2.19 seconds |
Started | Apr 04 03:46:34 PM PDT 24 |
Finished | Apr 04 03:46:36 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-66487573-f7a8-4fd5-a5fd-5abd2fb28f0b |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761724846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.3761724846 |
Directory | /workspace/6.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/6.clkmgr_smoke.3506607403 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 33211848 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:46:24 PM PDT 24 |
Finished | Apr 04 03:46:25 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-422a77d7-eed5-432d-a4c9-ff9ebc4de67f |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506607403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.3506607403 |
Directory | /workspace/6.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/6.clkmgr_stress_all.230407146 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 1098658105 ps |
CPU time | 6.35 seconds |
Started | Apr 04 03:46:27 PM PDT 24 |
Finished | Apr 04 03:46:33 PM PDT 24 |
Peak memory | 200944 kb |
Host | smart-f7c8ade0-b827-40fa-be4c-e14d9a698dea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230407146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.230407146 |
Directory | /workspace/6.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.2091485678 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 59133132418 ps |
CPU time | 617.44 seconds |
Started | Apr 04 03:46:30 PM PDT 24 |
Finished | Apr 04 03:56:47 PM PDT 24 |
Peak memory | 209300 kb |
Host | smart-1c446e47-1670-443a-b677-a16214c2f6aa |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2091485678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.2091485678 |
Directory | /workspace/6.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.clkmgr_trans.80890801 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 20201128 ps |
CPU time | 0.99 seconds |
Started | Apr 04 03:46:29 PM PDT 24 |
Finished | Apr 04 03:46:30 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-6753aaa3-c313-489f-ae6b-8b1defc1de4d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80890801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.80890801 |
Directory | /workspace/6.clkmgr_trans/latest |
Test location | /workspace/coverage/default/7.clkmgr_alert_test.2468981470 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 12401580 ps |
CPU time | 0.69 seconds |
Started | Apr 04 03:46:46 PM PDT 24 |
Finished | Apr 04 03:46:47 PM PDT 24 |
Peak memory | 199944 kb |
Host | smart-c2abe18f-2005-45a6-9ed4-6a2d470a08a4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468981470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm gr_alert_test.2468981470 |
Directory | /workspace/7.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.3168181824 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 111167055 ps |
CPU time | 1.17 seconds |
Started | Apr 04 03:46:34 PM PDT 24 |
Finished | Apr 04 03:46:35 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-c8b8b6c8-854d-43b6-882c-1c372264545b |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168181824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.3168181824 |
Directory | /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/7.clkmgr_clk_status.2280090294 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 57040493 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:46:25 PM PDT 24 |
Finished | Apr 04 03:46:26 PM PDT 24 |
Peak memory | 199584 kb |
Host | smart-42826668-d069-4d29-8924-7efeae332038 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280090294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.2280090294 |
Directory | /workspace/7.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/7.clkmgr_div_intersig_mubi.3405511100 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 79554592 ps |
CPU time | 1.03 seconds |
Started | Apr 04 03:46:39 PM PDT 24 |
Finished | Apr 04 03:46:40 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-aba86aad-70c0-4953-b73c-54b0da68e425 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405511100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.3405511100 |
Directory | /workspace/7.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/7.clkmgr_extclk.615693395 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 51626566 ps |
CPU time | 0.89 seconds |
Started | Apr 04 03:46:35 PM PDT 24 |
Finished | Apr 04 03:46:36 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-4dec8551-3bb9-490d-bbf8-20e891802ded |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615693395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.615693395 |
Directory | /workspace/7.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/7.clkmgr_frequency.1682918033 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 974653065 ps |
CPU time | 3.89 seconds |
Started | Apr 04 03:46:29 PM PDT 24 |
Finished | Apr 04 03:46:33 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-1224c7f0-a701-44d7-a266-fe5454e61328 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682918033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.1682918033 |
Directory | /workspace/7.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/7.clkmgr_frequency_timeout.4021776390 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 2319221842 ps |
CPU time | 9.9 seconds |
Started | Apr 04 03:46:34 PM PDT 24 |
Finished | Apr 04 03:46:44 PM PDT 24 |
Peak memory | 200924 kb |
Host | smart-cd25dde9-1895-42e4-96e3-eef8d78c1592 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021776390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti meout.4021776390 |
Directory | /workspace/7.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.4085176669 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 91733689 ps |
CPU time | 1.16 seconds |
Started | Apr 04 03:46:31 PM PDT 24 |
Finished | Apr 04 03:46:32 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-f650743d-84a9-4dc7-a032-28bbe3eccbf1 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085176669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.4085176669 |
Directory | /workspace/7.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.564749812 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 15672128 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:46:26 PM PDT 24 |
Finished | Apr 04 03:46:27 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-3ec2921e-bf3a-42ef-af38-0210af733b74 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564749812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.clkmgr_lc_clk_byp_req_intersig_mubi.564749812 |
Directory | /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.4208561134 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 19643143 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:46:31 PM PDT 24 |
Finished | Apr 04 03:46:32 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-186e8e42-087d-46a8-bc24-60f405d2c059 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208561134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 7.clkmgr_lc_ctrl_intersig_mubi.4208561134 |
Directory | /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/7.clkmgr_peri.2813232981 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 20456480 ps |
CPU time | 0.76 seconds |
Started | Apr 04 03:46:31 PM PDT 24 |
Finished | Apr 04 03:46:32 PM PDT 24 |
Peak memory | 200424 kb |
Host | smart-0d7e087c-1d1a-4f82-8f5d-d3ba4cde926e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813232981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.2813232981 |
Directory | /workspace/7.clkmgr_peri/latest |
Test location | /workspace/coverage/default/7.clkmgr_regwen.519313303 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 1543485629 ps |
CPU time | 5.59 seconds |
Started | Apr 04 03:46:41 PM PDT 24 |
Finished | Apr 04 03:46:46 PM PDT 24 |
Peak memory | 200792 kb |
Host | smart-c117b134-b06a-499c-a8e8-a93c8f8c8cf5 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519313303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.519313303 |
Directory | /workspace/7.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/7.clkmgr_smoke.345284833 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 23920799 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:46:30 PM PDT 24 |
Finished | Apr 04 03:46:31 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-de8ca1c4-c25b-415a-b661-a2dec2b4b3a4 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345284833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.345284833 |
Directory | /workspace/7.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/7.clkmgr_stress_all.129922154 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 2994988870 ps |
CPU time | 22.65 seconds |
Started | Apr 04 03:46:40 PM PDT 24 |
Finished | Apr 04 03:47:03 PM PDT 24 |
Peak memory | 200964 kb |
Host | smart-bb30c72c-f4c2-4cd0-85a3-4f4ff8392676 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129922154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.129922154 |
Directory | /workspace/7.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.3034628112 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 52394903582 ps |
CPU time | 761.72 seconds |
Started | Apr 04 03:46:39 PM PDT 24 |
Finished | Apr 04 03:59:20 PM PDT 24 |
Peak memory | 209308 kb |
Host | smart-5c1751c7-30e5-43d0-9a18-21a7ad79b944 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3034628112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.3034628112 |
Directory | /workspace/7.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.clkmgr_trans.2283483955 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 136939319 ps |
CPU time | 1.12 seconds |
Started | Apr 04 03:46:35 PM PDT 24 |
Finished | Apr 04 03:46:36 PM PDT 24 |
Peak memory | 200516 kb |
Host | smart-a7373a72-90a1-4df4-a6e9-daeb0cb54de2 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283483955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.2283483955 |
Directory | /workspace/7.clkmgr_trans/latest |
Test location | /workspace/coverage/default/8.clkmgr_alert_test.1291461692 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 17085428 ps |
CPU time | 0.69 seconds |
Started | Apr 04 03:46:41 PM PDT 24 |
Finished | Apr 04 03:46:42 PM PDT 24 |
Peak memory | 200460 kb |
Host | smart-53487774-8594-44bd-b570-451070bdb47a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291461692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm gr_alert_test.1291461692 |
Directory | /workspace/8.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.1149963086 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 38984285 ps |
CPU time | 0.85 seconds |
Started | Apr 04 03:46:43 PM PDT 24 |
Finished | Apr 04 03:46:44 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-88e1eb81-3729-4e62-9638-e76fc16f51ff |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149963086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.1149963086 |
Directory | /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/8.clkmgr_clk_status.3930265344 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 41491368 ps |
CPU time | 0.77 seconds |
Started | Apr 04 03:46:38 PM PDT 24 |
Finished | Apr 04 03:46:39 PM PDT 24 |
Peak memory | 200352 kb |
Host | smart-d31c36a3-f28e-4f25-afcd-75911812d921 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930265344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.3930265344 |
Directory | /workspace/8.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/8.clkmgr_div_intersig_mubi.94158976 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 24887445 ps |
CPU time | 0.87 seconds |
Started | Apr 04 03:46:40 PM PDT 24 |
Finished | Apr 04 03:46:41 PM PDT 24 |
Peak memory | 200640 kb |
Host | smart-b9fad040-65f5-4bc9-92f0-fc9356d308e1 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94158976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8. clkmgr_div_intersig_mubi.94158976 |
Directory | /workspace/8.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/8.clkmgr_extclk.3228569713 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 18505920 ps |
CPU time | 0.78 seconds |
Started | Apr 04 03:46:41 PM PDT 24 |
Finished | Apr 04 03:46:42 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-d59e3c9a-a39c-4cd2-ab71-e55f8245a95e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228569713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.3228569713 |
Directory | /workspace/8.clkmgr_extclk/latest |
Test location | /workspace/coverage/default/8.clkmgr_frequency_timeout.1363771454 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 1577635954 ps |
CPU time | 10.59 seconds |
Started | Apr 04 03:46:39 PM PDT 24 |
Finished | Apr 04 03:46:50 PM PDT 24 |
Peak memory | 200724 kb |
Host | smart-3d8f8c60-95de-47a2-8341-957281fced6d |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363771454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti meout.1363771454 |
Directory | /workspace/8.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.3886662521 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 76036952 ps |
CPU time | 1.03 seconds |
Started | Apr 04 03:46:38 PM PDT 24 |
Finished | Apr 04 03:46:39 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-b8650aa0-79fc-40c0-ba98-693551f792c7 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886662521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.3886662521 |
Directory | /workspace/8.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.1710514088 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 17906423 ps |
CPU time | 0.86 seconds |
Started | Apr 04 03:46:40 PM PDT 24 |
Finished | Apr 04 03:46:41 PM PDT 24 |
Peak memory | 200612 kb |
Host | smart-06b3be47-a3c2-44bc-97d4-424adbcb6926 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710514088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_clk_byp_req_intersig_mubi.1710514088 |
Directory | /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.2771310075 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 43705540 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:46:41 PM PDT 24 |
Finished | Apr 04 03:46:42 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-a679d227-7b5d-4350-8339-5d3f7da3562b |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771310075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_ctrl_intersig_mubi.2771310075 |
Directory | /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/8.clkmgr_peri.2616432723 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 47776062 ps |
CPU time | 0.88 seconds |
Started | Apr 04 03:46:40 PM PDT 24 |
Finished | Apr 04 03:46:40 PM PDT 24 |
Peak memory | 200412 kb |
Host | smart-355124a2-8e55-4a09-bc4f-7f465757cf8e |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616432723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.2616432723 |
Directory | /workspace/8.clkmgr_peri/latest |
Test location | /workspace/coverage/default/8.clkmgr_regwen.2411774621 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 219320640 ps |
CPU time | 1.8 seconds |
Started | Apr 04 03:46:41 PM PDT 24 |
Finished | Apr 04 03:46:42 PM PDT 24 |
Peak memory | 200576 kb |
Host | smart-77513cac-be20-43b2-aeba-b9ba34660631 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411774621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.2411774621 |
Directory | /workspace/8.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/8.clkmgr_smoke.3200912910 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 18210944 ps |
CPU time | 0.79 seconds |
Started | Apr 04 03:46:37 PM PDT 24 |
Finished | Apr 04 03:46:38 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-75a7520e-e4ce-4ef7-b891-dcc49bf1fb79 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200912910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.3200912910 |
Directory | /workspace/8.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/8.clkmgr_stress_all.3398716485 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 6580003277 ps |
CPU time | 25.79 seconds |
Started | Apr 04 03:46:41 PM PDT 24 |
Finished | Apr 04 03:47:07 PM PDT 24 |
Peak memory | 201052 kb |
Host | smart-b37bd029-0dcd-43fa-8246-2fbc9d676ab3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398716485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.3398716485 |
Directory | /workspace/8.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.482082374 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 112649482883 ps |
CPU time | 1203.24 seconds |
Started | Apr 04 03:46:39 PM PDT 24 |
Finished | Apr 04 04:06:42 PM PDT 24 |
Peak memory | 209360 kb |
Host | smart-3ed5a3fc-4ba4-4c4e-bb83-429685849973 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=482082374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.482082374 |
Directory | /workspace/8.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.clkmgr_trans.2881683097 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 39798232 ps |
CPU time | 1.03 seconds |
Started | Apr 04 03:46:46 PM PDT 24 |
Finished | Apr 04 03:46:47 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-f6af5385-bdd0-4087-ad86-752ae7a40423 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881683097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.2881683097 |
Directory | /workspace/8.clkmgr_trans/latest |
Test location | /workspace/coverage/default/9.clkmgr_alert_test.3035707270 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 13531192 ps |
CPU time | 0.72 seconds |
Started | Apr 04 03:46:55 PM PDT 24 |
Finished | Apr 04 03:46:56 PM PDT 24 |
Peak memory | 200428 kb |
Host | smart-52291bdc-2d08-497d-ba79-d879c210a7ea |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035707270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm gr_alert_test.3035707270 |
Directory | /workspace/9.clkmgr_alert_test/latest |
Test location | /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.38873375 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 34125033 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:46:53 PM PDT 24 |
Finished | Apr 04 03:46:54 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-3e46a287-bfbb-4945-890a-ac0e4db50bd2 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38873375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .clkmgr_clk_handshake_intersig_mubi.38873375 |
Directory | /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest |
Test location | /workspace/coverage/default/9.clkmgr_clk_status.1814169682 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 35778919 ps |
CPU time | 0.75 seconds |
Started | Apr 04 03:46:55 PM PDT 24 |
Finished | Apr 04 03:46:56 PM PDT 24 |
Peak memory | 199556 kb |
Host | smart-807b7c7e-bd7b-404f-bde1-0ec66fe31b09 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814169682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.1814169682 |
Directory | /workspace/9.clkmgr_clk_status/latest |
Test location | /workspace/coverage/default/9.clkmgr_div_intersig_mubi.2281411881 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 30210209 ps |
CPU time | 0.83 seconds |
Started | Apr 04 03:46:54 PM PDT 24 |
Finished | Apr 04 03:46:55 PM PDT 24 |
Peak memory | 200612 kb |
Host | smart-79c142c3-2230-488e-ae42-dc974242526a |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281411881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.2281411881 |
Directory | /workspace/9.clkmgr_div_intersig_mubi/latest |
Test location | /workspace/coverage/default/9.clkmgr_frequency.1246519321 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 1642333133 ps |
CPU time | 13.05 seconds |
Started | Apr 04 03:46:40 PM PDT 24 |
Finished | Apr 04 03:46:53 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-476c963f-26f6-45fb-8e23-68a73e1a8eed |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246519321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.1246519321 |
Directory | /workspace/9.clkmgr_frequency/latest |
Test location | /workspace/coverage/default/9.clkmgr_frequency_timeout.4281979305 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 659178371 ps |
CPU time | 3.1 seconds |
Started | Apr 04 03:46:42 PM PDT 24 |
Finished | Apr 04 03:46:46 PM PDT 24 |
Peak memory | 200720 kb |
Host | smart-d0c614ad-d434-438d-bc4c-fbef533a7227 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281979305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti meout.4281979305 |
Directory | /workspace/9.clkmgr_frequency_timeout/latest |
Test location | /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.3166753284 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 41084985 ps |
CPU time | 1.04 seconds |
Started | Apr 04 03:46:51 PM PDT 24 |
Finished | Apr 04 03:46:52 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-0be87b88-451f-466e-8a29-473b8bad1753 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166753284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.3166753284 |
Directory | /workspace/9.clkmgr_idle_intersig_mubi/latest |
Test location | /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.547225465 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 60125975 ps |
CPU time | 0.9 seconds |
Started | Apr 04 03:46:54 PM PDT 24 |
Finished | Apr 04 03:46:55 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-4b966158-df72-4510-9dd2-4b54b6cc2371 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547225465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.clkmgr_lc_clk_byp_req_intersig_mubi.547225465 |
Directory | /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest |
Test location | /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.449404378 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 182849987 ps |
CPU time | 1.26 seconds |
Started | Apr 04 03:46:51 PM PDT 24 |
Finished | Apr 04 03:46:53 PM PDT 24 |
Peak memory | 200672 kb |
Host | smart-5f2311a9-645c-4c9a-a043-56e5580e8dc6 |
User | root |
Command | /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449404378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.clkmgr_lc_ctrl_intersig_mubi.449404378 |
Directory | /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest |
Test location | /workspace/coverage/default/9.clkmgr_peri.1935083649 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 28032718 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:46:40 PM PDT 24 |
Finished | Apr 04 03:46:40 PM PDT 24 |
Peak memory | 200360 kb |
Host | smart-c3e234fc-7836-4f4e-91d2-835fddb3fad0 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935083649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.1935083649 |
Directory | /workspace/9.clkmgr_peri/latest |
Test location | /workspace/coverage/default/9.clkmgr_regwen.3533537110 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 125404787 ps |
CPU time | 1.06 seconds |
Started | Apr 04 03:46:55 PM PDT 24 |
Finished | Apr 04 03:46:56 PM PDT 24 |
Peak memory | 200592 kb |
Host | smart-2d5796b4-991b-4db8-bfc7-b05aa93f00f5 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533537110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.3533537110 |
Directory | /workspace/9.clkmgr_regwen/latest |
Test location | /workspace/coverage/default/9.clkmgr_smoke.3963938854 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 22496510 ps |
CPU time | 0.84 seconds |
Started | Apr 04 03:46:46 PM PDT 24 |
Finished | Apr 04 03:46:47 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-a5417c27-f8d3-4da6-8a19-cfca581864a4 |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963938854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.3963938854 |
Directory | /workspace/9.clkmgr_smoke/latest |
Test location | /workspace/coverage/default/9.clkmgr_stress_all.1738165002 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 6657903242 ps |
CPU time | 39.28 seconds |
Started | Apr 04 03:46:54 PM PDT 24 |
Finished | Apr 04 03:47:34 PM PDT 24 |
Peak memory | 201012 kb |
Host | smart-5b13acd6-d0ae-468e-967a-acf9390899b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738165002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.1738165002 |
Directory | /workspace/9.clkmgr_stress_all/latest |
Test location | /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.3879926458 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 13798290358 ps |
CPU time | 194.83 seconds |
Started | Apr 04 03:46:53 PM PDT 24 |
Finished | Apr 04 03:50:09 PM PDT 24 |
Peak memory | 209240 kb |
Host | smart-2149dea2-c385-4ba1-a87b-93a72f0e47a1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3879926458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.3879926458 |
Directory | /workspace/9.clkmgr_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.clkmgr_trans.4261534508 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 20106102 ps |
CPU time | 0.8 seconds |
Started | Apr 04 03:46:40 PM PDT 24 |
Finished | Apr 04 03:46:40 PM PDT 24 |
Peak memory | 200488 kb |
Host | smart-59e05c57-7731-419b-b203-e1ed69e8fbdb |
User | root |
Command | /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261534508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.4261534508 |
Directory | /workspace/9.clkmgr_trans/latest |
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