CSRNG Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	284.886us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	17.542us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	14.343us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	19.000s	929.404us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	86.218us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	18.319us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	14.343us	20	20	100.00
		csrng_csr_aliasing	5.000s	86.218us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	244.315us	200	200	100.00
V2	alerts	csrng_alert	8.000s	449.075us	500	500	100.00
V2	err	csrng_err	5.000s	27.934us	489	500	97.80
V2	cmds	csrng_cmds	1.700m	9.206ms	50	50	100.00
V2	life cycle	csrng_cmds	1.700m	9.206ms	50	50	100.00
V2	stress_all	csrng_stress_all	1.850m	2.291ms	47	50	94.00
V2	intr_test	csrng_intr_test	4.000s	23.943us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	49.661us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	22.000s	1.281ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	22.000s	1.281ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	17.542us	5	5	100.00
		csrng_csr_rw	4.000s	14.343us	20	20	100.00
		csrng_csr_aliasing	5.000s	86.218us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	86.199us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	17.542us	5	5	100.00
		csrng_csr_rw	4.000s	14.343us	20	20	100.00
		csrng_csr_aliasing	5.000s	86.218us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	86.199us	20	20	100.00
V2		TOTAL			1426	1440	99.03
V2S	tl_intg_err	csrng_sec_cm	6.000s	87.947us	5	5	100.00
		csrng_tl_intg_err	8.000s	422.116us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	105.442us	50	50	100.00
		csrng_csr_rw	4.000s	14.343us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	8.000s	449.075us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	1.850m	2.291ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
		csrng_sec_cm	6.000s	87.947us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
		csrng_sec_cm	6.000s	87.947us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
		csrng_sec_cm	6.000s	87.947us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
		csrng_sec_cm	6.000s	87.947us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
		csrng_sec_cm	6.000s	87.947us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
		csrng_sec_cm	6.000s	87.947us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
		csrng_sec_cm	6.000s	87.947us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	8.000s	449.075us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	1.850m	2.291ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	8.000s	449.075us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	8.000s	422.116us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
		csrng_sec_cm	6.000s	87.947us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
		csrng_sec_cm	6.000s	87.947us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	244.315us	200	200	100.00
		csrng_err	5.000s	27.934us	489	500	97.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	43.367m	38.420ms	4	50	8.00
V3		TOTAL			4	50	8.00
		TOTAL			1610	1670	96.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.83	93.32	84.23	95.38	86.43	92.29	100.00	97.50	96.11

Failure Buckets

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 21 failures:
- Test csrng_stress_all_with_rand_reset has 21 failures.
  - 2.csrng_stress_all_with_rand_reset.4237224219
    Line 340, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 17502835510 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x885e1794) == 0x6
  UVM_INFO @ 17502835510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.850664872
    Line 258, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10001291517 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x61845294) == 0x6
  UVM_INFO @ 10001291517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 19 failures:
- Test csrng_stress_all_with_rand_reset has 19 failures.
  - 6.csrng_stress_all_with_rand_reset.1778094977
    Line 245, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10003232038 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x3fdb6a14) == 0x6
  UVM_INFO @ 10003232038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.csrng_stress_all_with_rand_reset.3639484402
    Line 269, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10003136298 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x96119f94) == 0x6
  UVM_INFO @ 10003136298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 5 failures:

Test csrng_err has 5 failures.

79.csrng_err.2336031101
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/79.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 7369628 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 7369628 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 7369628 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   7369628 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   7369628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

195.csrng_err.1017654832
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/195.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1788569 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1788569 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1788569 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1788569 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1788569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 5 failures:

Test csrng_err has 5 failures.

104.csrng_err.2560526764
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/104.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 1720328 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1720328 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1720328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

194.csrng_err.3697434471
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/194.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3229138 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3229138 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3229138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 3 failures:

Test csrng_stress_all_with_rand_reset has 3 failures.

1.csrng_stress_all_with_rand_reset.1640876864
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
            Time: 59441123 PS + 13
  Verilog Stack Trace:

20.csrng_stress_all_with_rand_reset.3486649157
Line 346, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
            Time: 7382857367 PS + 11
  Verilog Stack Trace:

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:

Test csrng_stress_all has 3 failures.

19.csrng_stress_all.2218882287
Line 283, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_stress_all/latest/run.log

  UVM_ERROR @ 488381427 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 488381427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.csrng_stress_all.893011258
Line 261, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/25.csrng_stress_all/latest/run.log

  UVM_ERROR @ 301918286 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 301918286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

3.csrng_stress_all_with_rand_reset.4150643026
Line 450, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 22310845212 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 22310845212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.csrng_stress_all_with_rand_reset.802856451
Line 438, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/49.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 21018508369 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 21018508369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 26.csrng_stress_all_with_rand_reset.2784637681
    Line 561, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 38449704791 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 38449704791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

416.csrng_err.1006702591
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/416.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  416.csrng_err.1006702591
  
  coverage files:
    model(design data) :  /workspace/coverage/default/416.csrng_err.1006702591/icc_2fd05324_376d948a.ucm
    data               :  /workspace/coverage/default/416.csrng_err.1006702591/icc_2fd05324_376d948a.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 18, 2023 at 03:59:59 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:144: simulate] Error 1