CSRNG Simulation Results

Sunday September 24 2023 19:02:28 UTC

GitHub Revision: `8c6aecd4d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 2769371395

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	28.000s	22.210us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	14.000s	52.308us	5	5	100.00
V1	csr_rw	csrng_csr_rw	19.000s	86.360us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	26.000s	605.499us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	109.353us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	20.000s	48.461us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	19.000s	86.360us	20	20	100.00
		csrng_csr_aliasing	8.000s	109.353us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	28.000s	71.713us	200	200	100.00
V2	alerts	csrng_alert	34.000s	29.208us	500	500	100.00
V2	err	csrng_err	23.000s	24.656us	487	500	97.40
V2	cmds	csrng_cmds	9.350m	47.877ms	50	50	100.00
V2	life cycle	csrng_cmds	9.350m	47.877ms	50	50	100.00
V2	stress_all	csrng_stress_all	21.933m	70.916ms	47	50	94.00
V2	intr_test	csrng_intr_test	18.000s	85.401us	50	50	100.00
V2	alert_test	csrng_alert_test	23.000s	23.166us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	24.000s	1.529ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	24.000s	1.529ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	14.000s	52.308us	5	5	100.00
		csrng_csr_rw	19.000s	86.360us	20	20	100.00
		csrng_csr_aliasing	8.000s	109.353us	5	5	100.00
		csrng_same_csr_outstanding	18.000s	19.158us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	14.000s	52.308us	5	5	100.00
		csrng_csr_rw	19.000s	86.360us	20	20	100.00
		csrng_csr_aliasing	8.000s	109.353us	5	5	100.00
		csrng_same_csr_outstanding	18.000s	19.158us	20	20	100.00
V2		TOTAL			1424	1440	98.89
V2S	tl_intg_err	csrng_sec_cm	17.000s	244.782us	5	5	100.00
		csrng_tl_intg_err	26.000s	1.705ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	23.000s	35.486us	50	50	100.00
		csrng_csr_rw	19.000s	86.360us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	34.000s	29.208us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	21.933m	70.916ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
		csrng_sec_cm	17.000s	244.782us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
		csrng_sec_cm	17.000s	244.782us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
		csrng_sec_cm	17.000s	244.782us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
		csrng_sec_cm	17.000s	244.782us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
		csrng_sec_cm	17.000s	244.782us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
		csrng_sec_cm	17.000s	244.782us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
		csrng_sec_cm	17.000s	244.782us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	34.000s	29.208us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	21.933m	70.916ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	34.000s	29.208us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	26.000s	1.705ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
		csrng_sec_cm	17.000s	244.782us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
		csrng_sec_cm	17.000s	244.782us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	28.000s	71.713us	200	200	100.00
		csrng_err	23.000s	24.656us	487	500	97.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.906h	212.351ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			1636	1670	97.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.78	93.24	84.31	95.35	86.47	92.29	100.00	97.50	95.87

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 9 failures:

Test csrng_err has 9 failures.

32.csrng_err.2185312470
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 8538478 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 8538478 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 8538478 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   8538478 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   8538478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

123.csrng_err.2848131493
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/123.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1721426 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1721426 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1721426 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1721426 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1721426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 7 more failures.

UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 7 failures:

Test csrng_stress_all_with_rand_reset has 7 failures.

0.csrng_stress_all_with_rand_reset.2898899396
Line 1254, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 115774384754 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 115774384754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.csrng_stress_all_with_rand_reset.3314807879
Line 667, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 111992949163 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 111992949163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 3.csrng_stress_all_with_rand_reset.1908703876
    Line 628, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 198050970002 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 198050970002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.csrng_stress_all_with_rand_reset.2154253271
    Line 550, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 95905106326 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 95905106326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 4 failures:

Test csrng_stress_all_with_rand_reset has 4 failures.

5.csrng_stress_all_with_rand_reset.1630824740
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
            Time: 48068327 PS + 12
  Verilog Stack Trace:

6.csrng_stress_all_with_rand_reset.2906902322
Line 259, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
            Time: 22726846295 PS + 12
  Verilog Stack Trace:

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 3 failures:

Test csrng_err has 3 failures.

8.csrng_err.418543984
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 1591269 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1591269 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1591269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.csrng_err.2200618176
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/31.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3781379 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3781379 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3781379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:155) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

Test csrng_stress_all has 2 failures.

27.csrng_stress_all.3122063536
Line 269, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_stress_all/latest/run.log

  UVM_ERROR @ 10424284087 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 10424284087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.csrng_stress_all.3080814217
Line 262, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/37.csrng_stress_all/latest/run.log

  UVM_ERROR @  39384044 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  39384044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csrng_scoreboard.sv:155) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 5.csrng_stress_all.4009506980
    Line 270, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 18590209324 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 18590209324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 41.csrng_stress_all_with_rand_reset.2960885986
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/41.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f405b5b6-38b5-442b-bad2-2eb2d888d155
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

377.csrng_err.192314483
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/377.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  377.csrng_err.192314483
  
  coverage files:
    model(design data) :  /workspace/coverage/default/377.csrng_err.192314483/icc_238a3628_01cbe0a4.ucm
    data               :  /workspace/coverage/default/377.csrng_err.192314483/icc_238a3628_01cbe0a4.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Sep 24, 2023 at 12:58:33 PDT  (total: 00:00:10)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:150: simulate] Error 1