CSRNG Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: `671f2b57e2`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	33.239us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	12.000s	63.158us	5	5	100.00
V1	csr_rw	csrng_csr_rw	11.000s	58.405us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	46.000s	4.473ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	15.188us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	70.712us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	11.000s	58.405us	20	20	100.00
		csrng_csr_aliasing	7.000s	15.188us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	9.000s	49.538us	200	200	100.00
V2	alerts	csrng_alert	16.000s	313.292us	500	500	100.00
V2	err	csrng_err	13.000s	21.187us	480	500	96.00
V2	cmds	csrng_cmds	7.000m	36.077ms	50	50	100.00
V2	life cycle	csrng_cmds	7.000m	36.077ms	50	50	100.00
V2	stress_all	csrng_stress_all	25.900m	139.435ms	50	50	100.00
V2	intr_test	csrng_intr_test	16.000s	184.750us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	196.484us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	19.000s	1.373ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	19.000s	1.373ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	12.000s	63.158us	5	5	100.00
		csrng_csr_rw	11.000s	58.405us	20	20	100.00
		csrng_csr_aliasing	7.000s	15.188us	5	5	100.00
		csrng_same_csr_outstanding	17.000s	142.101us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	12.000s	63.158us	5	5	100.00
		csrng_csr_rw	11.000s	58.405us	20	20	100.00
		csrng_csr_aliasing	7.000s	15.188us	5	5	100.00
		csrng_same_csr_outstanding	17.000s	142.101us	20	20	100.00
V2		TOTAL			1420	1440	98.61
V2S	tl_intg_err	csrng_sec_cm	6.000s	245.111us	5	5	100.00
		csrng_tl_intg_err	23.000s	1.175ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	44.854us	50	50	100.00
		csrng_csr_rw	11.000s	58.405us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	16.000s	313.292us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.900m	139.435ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
		csrng_sec_cm	6.000s	245.111us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
		csrng_sec_cm	6.000s	245.111us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
		csrng_sec_cm	6.000s	245.111us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
		csrng_sec_cm	6.000s	245.111us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
		csrng_sec_cm	6.000s	245.111us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
		csrng_sec_cm	6.000s	245.111us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
		csrng_sec_cm	6.000s	245.111us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	16.000s	313.292us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.900m	139.435ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	16.000s	313.292us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	23.000s	1.175ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
		csrng_sec_cm	6.000s	245.111us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
		csrng_sec_cm	6.000s	245.111us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	9.000s	49.538us	200	200	100.00
		csrng_err	13.000s	21.187us	480	500	96.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.664h	669.196ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1627	1670	97.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	8	88.89
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.74	93.24	84.31	95.35	86.47	92.29	98.18	97.50	94.81

Failure Buckets

UVM_FATAL (csrng_scoreboard.sv:592) scoreboard [scoreboard] Invalid csrng_acmd: * has 11 failures:
- Test csrng_stress_all_with_rand_reset has 11 failures.
  - 1.csrng_stress_all_with_rand_reset.44640494251601963928380393160218083243560283754725434803757947165596175720865
    Line 1094, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 59577301584 ps: (csrng_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 59577301584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.93049768703836682796417287449509338608983287257754028803012033679853384879895
    Line 895, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 669195990950 ps: (csrng_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 669195990950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:592) scoreboard [scoreboard] Invalid csrng_acmd: * has 10 failures:
- Test csrng_stress_all_with_rand_reset has 10 failures.
  - 7.csrng_stress_all_with_rand_reset.98811358900180321876138776443469876910297943648198668456424677243584960731861
    Line 536, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 68706839040 ps: (csrng_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 68706839040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.csrng_stress_all_with_rand_reset.6417912333764725576995080432365921904350650744435414922283582718336156203537
    Line 368, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 8838457350 ps: (csrng_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 8838457350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 10 failures:

Test csrng_err has 10 failures.

59.csrng_err.63186645131188517894345865898461051777753847328357165478671520227429825987913
Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/59.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 8313541 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   8313541 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   8313541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

99.csrng_err.23292876773121415443534845078886551769523712856322299208992812207601106457504
Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/99.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 7907080 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   7907080 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   7907080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 8 failures:

Test csrng_err has 8 failures.

95.csrng_err.24278064746363732787951999031466735733678066869912356891793233765109090179248
Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/95.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 8029320 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 8029320 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 8029320 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   8029320 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   8029320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

104.csrng_err.78745074440166330628348826414706048054285013189342333174885600192724754566984
Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/104.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 10811642 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 10811642 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 10811642 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  10811642 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  10811642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 6 more failures.

Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 6.csrng_stress_all_with_rand_reset.21712173271111784288723437189053502887840779479992457114484049345899518361067
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:6dda591a-de51-4bbb-97c4-81ab41f449d3
```
  - 41.csrng_stress_all_with_rand_reset.12781701629338079847270455740725512721345161037594684694969349234655402362449
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/41.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1ea53c2d-196e-4db0-8213-39aa08c7e771
```
UVM_ERROR (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 123.csrng_err.77796238235880274747355541169555149826305710230872519816502219874503692009503
    Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/123.csrng_err/latest/run.log
```
  UVM_ERROR @   2515415 ps: (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   2515415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

441.csrng_err.20627992928371312552720627119192285792048387786996382249547043893014254948050
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/441.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  441.csrng_err.1427476178
  
  coverage files:
    model(design data) :  /workspace/coverage/default/441.csrng_err.1427476178/icc_238a3628_24e48c5b.ucm
    data               :  /workspace/coverage/default/441.csrng_err.1427476178/icc_238a3628_24e48c5b.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Dec 24, 2023 at 12:46:41 PST  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1