CSRNG Simulation Results

Wednesday November 01 2023 19:03:40 UTC

GitHub Revision: 81a099ffe

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 27873820941847380568675700688072806075234726090008181917214625014019073121880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	62.596us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	20.196us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	24.874us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	10.000s	202.296us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	42.179us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	22.434us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	24.874us	20	20	100.00
		csrng_csr_aliasing	5.000s	42.179us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	18.000s	71.756us	200	200	100.00
V2	alerts	csrng_alert	18.000s	88.396us	500	500	100.00
V2	err	csrng_err	15.000s	31.636us	500	500	100.00
V2	cmds	csrng_cmds	1.217m	4.218ms	50	50	100.00
V2	life cycle	csrng_cmds	1.217m	4.218ms	50	50	100.00
V2	stress_all	csrng_stress_all	7.550m	19.138ms	50	50	100.00
V2	intr_test	csrng_intr_test	8.000s	18.298us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	17.315us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	9.000s	66.043us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	9.000s	66.043us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	20.196us	5	5	100.00
		csrng_csr_rw	8.000s	24.874us	20	20	100.00
		csrng_csr_aliasing	5.000s	42.179us	5	5	100.00
		csrng_same_csr_outstanding	4.000s	34.518us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	20.196us	5	5	100.00
		csrng_csr_rw	8.000s	24.874us	20	20	100.00
		csrng_csr_aliasing	5.000s	42.179us	5	5	100.00
		csrng_same_csr_outstanding	4.000s	34.518us	20	20	100.00
V2		TOTAL			1440	1440	100.00
V2S	tl_intg_err	csrng_sec_cm	5.000s	83.721us	5	5	100.00
		csrng_tl_intg_err	8.000s	92.280us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	20.790us	50	50	100.00
		csrng_csr_rw	8.000s	24.874us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	18.000s	88.396us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	7.550m	19.138ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
		csrng_sec_cm	5.000s	83.721us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
		csrng_sec_cm	5.000s	83.721us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
		csrng_sec_cm	5.000s	83.721us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
		csrng_sec_cm	5.000s	83.721us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
		csrng_sec_cm	5.000s	83.721us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
		csrng_sec_cm	5.000s	83.721us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
		csrng_sec_cm	5.000s	83.721us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	18.000s	88.396us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	7.550m	19.138ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	18.000s	88.396us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	8.000s	92.280us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
		csrng_sec_cm	5.000s	83.721us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
		csrng_sec_cm	5.000s	83.721us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	18.000s	71.756us	200	200	100.00
		csrng_err	15.000s	31.636us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.561h	118.971ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1670	1670	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	9	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
90.18	91.57	80.24	93.81	85.22	91.85	81.82	93.50	71.46

Past Results

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