EDN Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: ac0bef2ce

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.960s	16.632us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.930s	15.918us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.950s	29.553us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.930s	173.484us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.330s	72.655us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.420s	34.707us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.950s	29.553us	20	20	100.00
		edn_csr_aliasing	1.330s	72.655us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.490s	92.867us	50	50	100.00
V2	csrng_commands	edn_genbits	1.490s	92.867us	50	50	100.00
V2	genbits	edn_genbits	1.490s	92.867us	50	50	100.00
V2	interrupts	edn_intr	1.290s	22.474us	50	50	100.00
V2	alerts	edn_alert	1.050s	19.081us	50	50	100.00
V2	errs	edn_err	1.120s	19.198us	50	50	100.00
V2	disable	edn_disable	0.930s	13.438us	49	50	98.00
		edn_disable_auto_req_mode	1.140s	104.928us	50	50	100.00
V2	stress_all	edn_stress_all	4.070s	1.231ms	50	50	100.00
V2	intr_test	edn_intr_test	0.920s	13.701us	50	50	100.00
V2	alert_test	edn_alert_test	1.250s	81.962us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.630s	121.265us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.630s	121.265us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.930s	15.918us	5	5	100.00
		edn_csr_rw	0.950s	29.553us	20	20	100.00
		edn_csr_aliasing	1.330s	72.655us	5	5	100.00
		edn_same_csr_outstanding	1.420s	281.749us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.930s	15.918us	5	5	100.00
		edn_csr_rw	0.950s	29.553us	20	20	100.00
		edn_csr_aliasing	1.330s	72.655us	5	5	100.00
		edn_same_csr_outstanding	1.420s	281.749us	20	20	100.00
V2		TOTAL			489	490	99.80
V2S	tl_intg_err	edn_sec_cm	6.120s	387.252us	5	5	100.00
		edn_tl_intg_err	3.250s	150.464us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.920s	15.918us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.050s	19.081us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.120s	387.252us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.120s	387.252us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.120s	387.252us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.050s	19.081us	50	50	100.00
		edn_sec_cm	6.120s	387.252us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.050s	19.081us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.250s	150.464us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	33.435m	92.126ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			679	680	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.23	99.03	94.43	96.79	72.37	98.62	99.77	98.61

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_disable has 1 failures.

    • 36.edn_disable.2579918610
      Line 222, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/36.edn_disable/latest/run.log

        UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.17_17.48.11
• 2023.05.16_19.13.43
• 2023.05.15_18.31.47
• 2023.05.14_17.57.46
• 2023.05.13_18.40.44
• 2023.05.12_18.31.42
• 2023.05.12_11.15.11