Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	189015908	8417957	0	0
boot_gen_cmd_rd_A	189015908	62012	0	0
boot_ins_cmd_rd_A	189015908	71353	0	0
ctrl_rd_A	189015908	63769	0	0
err_code_test_rd_A	189015908	62716	0	0
intr_enable_rd_A	189015908	69555	0	0
max_num_reqs_between_reseeds_rd_A	189015908	72892	0	0
regwen_rd_A	189015908	72589	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189015908	8417957	0	0
T25	151428	56097	0	0
T26	125985	53170	0	0
T27	102074	429718	0	0
T44	2820	0	0	0
T52	2350	0	0	0
T112	2761	0	0	0
T122	127569	53619	0	0
T123	0	324210	0	0
T127	0	223503	0	0
T128	0	261338	0	0
T130	0	5	0	0
T132	2405	0	0	0
T179	0	48	0	0
T180	0	7	0	0
T181	701	0	0	0
T182	1176	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189015908	62012	0	0
T25	151428	1713	0	0
T26	125985	0	0	0
T41	641	0	0	0
T45	1865	0	0	0
T52	2350	0	0	0
T127	559163	3536	0	0
T128	0	7298	0	0
T183	0	3	0	0
T184	0	18	0	0
T185	0	13	0	0
T186	0	6	0	0
T187	0	4	0	0
T188	0	21	0	0
T189	0	2	0	0
T190	1878	0	0	0
T191	1932	0	0	0
T192	1527	0	0	0
T193	1306	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189015908	71353	0	0
T25	151428	2026	0	0
T26	125985	0	0	0
T41	641	0	0	0
T45	1865	0	0	0
T52	2350	0	0	0
T127	559163	3585	0	0
T128	0	8335	0	0
T183	0	24	0	0
T184	0	6	0	0
T185	0	37	0	0
T187	0	8	0	0
T189	0	2	0	0
T190	1878	0	0	0
T191	1932	0	0	0
T192	1527	0	0	0
T193	1306	0	0	0
T194	0	10	0	0
T195	0	4	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189015908	63769	0	0
T9	2243	0	0	0
T25	151428	1739	0	0
T26	125985	0	0	0
T45	1865	0	0	0
T52	2350	0	0	0
T99	1335	3	0	0
T100	1047	0	0	0
T127	559163	3414	0	0
T128	0	7434	0	0
T183	0	7	0	0
T184	0	7	0	0
T185	0	51	0	0
T187	0	14	0	0
T188	0	48	0	0
T190	1878	0	0	0
T191	1932	0	0	0
T194	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189015908	62716	0	0
T25	151428	1637	0	0
T26	125985	0	0	0
T41	641	0	0	0
T45	1865	0	0	0
T52	2350	0	0	0
T127	559163	3419	0	0
T128	0	6887	0	0
T183	0	10	0	0
T184	0	13	0	0
T185	0	44	0	0
T187	0	15	0	0
T188	0	7	0	0
T190	1878	0	0	0
T191	1932	0	0	0
T192	1527	0	0	0
T193	1306	0	0	0
T195	0	8	0	0
T196	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189015908	69555	0	0
T25	151428	1779	0	0
T26	125985	0	0	0
T34	1121	0	0	0
T52	2350	0	0	0
T67	782	0	0	0
T125	13397	11	0	0
T126	1641	0	0	0
T127	0	3803	0	0
T128	0	7540	0	0
T180	0	90	0	0
T183	0	9	0	0
T184	0	19	0	0
T194	0	3	0	0
T197	0	7	0	0
T198	0	92	0	0
T199	3637	0	0	0
T200	1538	0	0	0
T201	1178	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189015908	72892	0	0
T25	151428	1948	0	0
T26	125985	0	0	0
T41	641	0	0	0
T45	1865	0	0	0
T52	2350	0	0	0
T127	559163	3673	0	0
T128	0	8370	0	0
T180	0	63	0	0
T183	0	17	0	0
T184	0	9	0	0
T185	0	22	0	0
T186	0	33	0	0
T190	1878	0	0	0
T191	1932	0	0	0
T192	1527	0	0	0
T193	1306	0	0	0
T194	0	4	0	0
T198	0	40	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189015908	72589	0	0
T25	151428	1762	0	0
T26	125985	0	0	0
T41	641	0	0	0
T45	1865	0	0	0
T52	2350	0	0	0
T127	559163	3831	0	0
T128	0	7820	0	0
T180	0	68	0	0
T183	0	8	0	0
T184	0	17	0	0
T185	0	81	0	0
T186	0	37	0	0
T190	1878	0	0	0
T191	1932	0	0	0
T192	1527	0	0	0
T193	1306	0	0	0
T194	0	5	0	0
T198	0	21	0	0